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Convert assert(0) to llvm_unreachable

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llvm-svn: 149816
This commit is contained in:
Craig Topper 2012-02-05 08:31:47 +00:00
parent 9db1b1bb0a
commit d218e7cb60
13 changed files with 41 additions and 46 deletions
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3
lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
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@ -25,6 +25,7 @@
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/Twine.h" #include "llvm/ADT/Twine.h"
#include "llvm/Support/Dwarf.h" #include "llvm/Support/Dwarf.h"
#include "llvm/Support/ErrorHandling.h"
using namespace llvm; using namespace llvm;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -110,7 +111,7 @@ unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const {
return 0; return 0;
switch (Encoding & 0x07) { switch (Encoding & 0x07) {
default: assert(0 && "Invalid encoded value."); default: llvm_unreachable("Invalid encoded value.");
case dwarf::DW_EH_PE_absptr: return TM.getTargetData()->getPointerSize(); case dwarf::DW_EH_PE_absptr: return TM.getTargetData()->getPointerSize();
case dwarf::DW_EH_PE_udata2: return 2; case dwarf::DW_EH_PE_udata2: return 2;
case dwarf::DW_EH_PE_udata4: return 4; case dwarf::DW_EH_PE_udata4: return 4;

2
lib/CodeGen/AsmPrinter/DIE.cpp
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@ -310,7 +310,7 @@ unsigned DIEBlock::ComputeSize(AsmPrinter *AP) {
/// ///
void DIEBlock::EmitValue(AsmPrinter *Asm, unsigned Form) const { void DIEBlock::EmitValue(AsmPrinter *Asm, unsigned Form) const {
switch (Form) { switch (Form) {
default: assert(0 && "Improper form for block"); break; default: llvm_unreachable("Improper form for block");
case dwarf::DW_FORM_block1: Asm->EmitInt8(Size); break; case dwarf::DW_FORM_block1: Asm->EmitInt8(Size); break;
case dwarf::DW_FORM_block2: Asm->EmitInt16(Size); break; case dwarf::DW_FORM_block2: Asm->EmitInt16(Size); break;
case dwarf::DW_FORM_block4: Asm->EmitInt32(Size); break; case dwarf::DW_FORM_block4: Asm->EmitInt32(Size); break;

8
lib/CodeGen/AsmPrinter/DwarfDebug.cpp
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@ -389,8 +389,7 @@ DIE *DwarfDebug::constructInlinedScopeDIE(CompileUnit *TheCU,
const MCSymbol *EndLabel = getLabelAfterInsn(RI->second); const MCSymbol *EndLabel = getLabelAfterInsn(RI->second);
if (StartLabel == 0 || EndLabel == 0) { if (StartLabel == 0 || EndLabel == 0) {
assert(0 && "Unexpected Start and End labels for a inlined scope!"); llvm_unreachable("Unexpected Start and End labels for a inlined scope!");
return 0;
} }
assert(StartLabel->isDefined() && assert(StartLabel->isDefined() &&
"Invalid starting label for an inlined scope!"); "Invalid starting label for an inlined scope!");
@ -956,8 +955,7 @@ static DotDebugLocEntry getDebugLocEntry(AsmPrinter *Asm,
if (MI->getOperand(0).isCImm()) if (MI->getOperand(0).isCImm())
return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getCImm()); return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getCImm());
assert(0 && "Unexpected 3 operand DBG_VALUE instruction!"); llvm_unreachable("Unexpected 3 operand DBG_VALUE instruction!");
return DotDebugLocEntry();
} }
/// collectVariableInfo - Find variables for each lexical scope. /// collectVariableInfo - Find variables for each lexical scope.
@ -1470,7 +1468,7 @@ void DwarfDebug::recordSourceLine(unsigned Line, unsigned Col, const MDNode *S,
Fn = DB.getFilename(); Fn = DB.getFilename();
Dir = DB.getDirectory(); Dir = DB.getDirectory();
} else } else
assert(0 && "Unexpected scope info"); llvm_unreachable("Unexpected scope info");
Src = GetOrCreateSourceID(Fn, Dir); Src = GetOrCreateSourceID(Fn, Dir);
} }

7
lib/CodeGen/AsmPrinter/DwarfException.cpp
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@ -31,6 +31,7 @@
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Dwarf.h" #include "llvm/Support/Dwarf.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h" #include "llvm/Support/FormattedStream.h"
#include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringExtras.h"
@ -714,17 +715,17 @@ void DwarfException::EmitExceptionTable() {
/// EndModule - Emit all exception information that should come after the /// EndModule - Emit all exception information that should come after the
/// content. /// content.
void DwarfException::EndModule() { void DwarfException::EndModule() {
assert(0 && "Should be implemented"); llvm_unreachable("Should be implemented");
} }
/// BeginFunction - Gather pre-function exception information. Assumes it's /// BeginFunction - Gather pre-function exception information. Assumes it's
/// being emitted immediately after the function entry point. /// being emitted immediately after the function entry point.
void DwarfException::BeginFunction(const MachineFunction *MF) { void DwarfException::BeginFunction(const MachineFunction *MF) {
assert(0 && "Should be implemented"); llvm_unreachable("Should be implemented");
} }
/// EndFunction - Gather and emit post-function exception information. /// EndFunction - Gather and emit post-function exception information.
/// ///
void DwarfException::EndFunction() { void DwarfException::EndFunction() {
assert(0 && "Should be implemented"); llvm_unreachable("Should be implemented");
} }

11
lib/CodeGen/IfConversion.cpp
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@ -315,8 +315,7 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
bool RetVal = false; bool RetVal = false;
switch (Kind) { switch (Kind) {
default: assert(false && "Unexpected!"); default: llvm_unreachable("Unexpected!");
break;
case ICSimple: case ICSimple:
case ICSimpleFalse: { case ICSimpleFalse: {
bool isFalse = Kind == ICSimpleFalse; bool isFalse = Kind == ICSimpleFalse;
@ -1036,7 +1035,7 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
if (Kind == ICSimpleFalse) if (Kind == ICSimpleFalse)
if (TII->ReverseBranchCondition(Cond)) if (TII->ReverseBranchCondition(Cond))
assert(false && "Unable to reverse branch condition!"); llvm_unreachable("Unable to reverse branch condition!");
// Initialize liveins to the first BB. These are potentiall redefined by // Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions. // predicated instructions.
@ -1109,7 +1108,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev) if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
if (TII->ReverseBranchCondition(Cond)) if (TII->ReverseBranchCondition(Cond))
assert(false && "Unable to reverse branch condition!"); llvm_unreachable("Unable to reverse branch condition!");
if (Kind == ICTriangleRev || Kind == ICTriangleFRev) { if (Kind == ICTriangleRev || Kind == ICTriangleFRev) {
if (ReverseBranchCondition(*CvtBBI)) { if (ReverseBranchCondition(*CvtBBI)) {
@ -1156,7 +1155,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(), SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
CvtBBI->BrCond.end()); CvtBBI->BrCond.end());
if (TII->ReverseBranchCondition(RevCond)) if (TII->ReverseBranchCondition(RevCond))
assert(false && "Unable to reverse branch condition!"); llvm_unreachable("Unable to reverse branch condition!");
TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond, dl); TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond, dl);
BBI.BB->addSuccessor(CvtBBI->FalseBB); BBI.BB->addSuccessor(CvtBBI->FalseBB);
} }
@ -1228,7 +1227,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
BBInfo *BBI2 = &FalseBBI; BBInfo *BBI2 = &FalseBBI;
SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
if (TII->ReverseBranchCondition(RevCond)) if (TII->ReverseBranchCondition(RevCond))
assert(false && "Unable to reverse branch condition!"); llvm_unreachable("Unable to reverse branch condition!");
SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond; SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
SmallVector<MachineOperand, 4> *Cond2 = &RevCond; SmallVector<MachineOperand, 4> *Cond2 = &RevCond;

6
lib/CodeGen/MachineFunction.cpp
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@ -528,6 +528,7 @@ unsigned MachineJumpTableInfo::getEntrySize(const TargetData &TD) const {
// The size of a jump table entry is 4 bytes unless the entry is just the // The size of a jump table entry is 4 bytes unless the entry is just the
// address of a block, in which case it is the pointer size. // address of a block, in which case it is the pointer size.
switch (getEntryKind()) { switch (getEntryKind()) {
default: llvm_unreachable("Unknown jump table encoding!");
case MachineJumpTableInfo::EK_BlockAddress: case MachineJumpTableInfo::EK_BlockAddress:
return TD.getPointerSize(); return TD.getPointerSize();
case MachineJumpTableInfo::EK_GPRel64BlockAddress: case MachineJumpTableInfo::EK_GPRel64BlockAddress:
@ -539,8 +540,6 @@ unsigned MachineJumpTableInfo::getEntrySize(const TargetData &TD) const {
case MachineJumpTableInfo::EK_Inline: case MachineJumpTableInfo::EK_Inline:
return 0; return 0;
} }
assert(0 && "Unknown jump table encoding!");
return ~0;
} }
/// getEntryAlignment - Return the alignment of each entry in the jump table. /// getEntryAlignment - Return the alignment of each entry in the jump table.
@ -549,6 +548,7 @@ unsigned MachineJumpTableInfo::getEntryAlignment(const TargetData &TD) const {
// entry is just the address of a block, in which case it is the pointer // entry is just the address of a block, in which case it is the pointer
// alignment. // alignment.
switch (getEntryKind()) { switch (getEntryKind()) {
default: llvm_unreachable("Unknown jump table encoding!");
case MachineJumpTableInfo::EK_BlockAddress: case MachineJumpTableInfo::EK_BlockAddress:
return TD.getPointerABIAlignment(); return TD.getPointerABIAlignment();
case MachineJumpTableInfo::EK_GPRel64BlockAddress: case MachineJumpTableInfo::EK_GPRel64BlockAddress:
@ -560,8 +560,6 @@ unsigned MachineJumpTableInfo::getEntryAlignment(const TargetData &TD) const {
case MachineJumpTableInfo::EK_Inline: case MachineJumpTableInfo::EK_Inline:
return 1; return 1;
} }
assert(0 && "Unknown jump table encoding!");
return ~0;
} }
/// createJumpTableIndex - Create a new jump table entry in the jump table info. /// createJumpTableIndex - Create a new jump table entry in the jump table info.

6
lib/CodeGen/MachineModuleInfo.cpp
View File

@ -268,9 +268,9 @@ MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI,
MachineModuleInfo::MachineModuleInfo() MachineModuleInfo::MachineModuleInfo()
: ImmutablePass(ID), : ImmutablePass(ID),
Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0) { Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0) {
assert(0 && "This MachineModuleInfo constructor should never be called, MMI " llvm_unreachable("This MachineModuleInfo constructor should never be called, "
"should always be explicitly constructed by LLVMTargetMachine"); "MMI should always be explicitly constructed by "
abort(); "LLVMTargetMachine");
} }
MachineModuleInfo::~MachineModuleInfo() { MachineModuleInfo::~MachineModuleInfo() {

2
lib/CodeGen/RegAllocPBQP.cpp
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@ -529,7 +529,7 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
// We need another round if spill intervals were added. // We need another round if spill intervals were added.
anotherRoundNeeded |= !LRE.empty(); anotherRoundNeeded |= !LRE.empty();
} else { } else {
assert(false && "Unknown allocation option."); llvm_unreachable("Unknown allocation option.");
} }
} }

28
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -893,7 +893,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
Node->dump( &DAG); Node->dump( &DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
assert(0 && "Do not know how to legalize this operator!"); llvm_unreachable("Do not know how to legalize this operator!");
case ISD::CALLSEQ_START: case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END: case ISD::CALLSEQ_END:
@ -910,7 +910,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
Tmp4 = SDValue(Node, 1); Tmp4 = SDValue(Node, 1);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) { switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal: case TargetLowering::Legal:
// If this is an unaligned load and the target doesn't support it, // If this is an unaligned load and the target doesn't support it,
// expand it. // expand it.
@ -1079,7 +1079,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
Tmp2 = Ch; Tmp2 = Ch;
} else { } else {
switch (TLI.getLoadExtAction(ExtType, SrcVT)) { switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
default: assert(0 && "This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Custom: case TargetLowering::Custom:
isCustom = true; isCustom = true;
// FALLTHROUGH // FALLTHROUGH
@ -1185,7 +1185,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
Tmp3 = ST->getValue(); Tmp3 = ST->getValue();
EVT VT = Tmp3.getValueType(); EVT VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) { switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: assert(0 && "This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal: case TargetLowering::Legal:
// If this is an unaligned store and the target doesn't support it, // If this is an unaligned store and the target doesn't support it,
// expand it. // expand it.
@ -1290,7 +1290,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
ReplaceNode(SDValue(Node, 0), Result); ReplaceNode(SDValue(Node, 0), Result);
} else { } else {
switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
default: assert(0 && "This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal: case TargetLowering::Legal:
// If this is an unaligned store and the target doesn't support it, // If this is an unaligned store and the target doesn't support it,
// expand it. // expand it.
@ -1556,7 +1556,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
EVT OpVT = LHS.getValueType(); EVT OpVT = LHS.getValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (TLI.getCondCodeAction(CCCode, OpVT)) { switch (TLI.getCondCodeAction(CCCode, OpVT)) {
default: assert(0 && "Unknown condition code action!"); default: llvm_unreachable("Unknown condition code action!");
case TargetLowering::Legal: case TargetLowering::Legal:
// Nothing to do. // Nothing to do.
break; break;
@ -1564,7 +1564,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
unsigned Opc = 0; unsigned Opc = 0;
switch (CCCode) { switch (CCCode) {
default: assert(0 && "Don't know how to expand this condition!"); default: llvm_unreachable("Don't know how to expand this condition!");
case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
@ -1866,7 +1866,7 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
RTLIB::Libcall Call_PPCF128) { RTLIB::Libcall Call_PPCF128) {
RTLIB::Libcall LC; RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT().SimpleTy) { switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: assert(0 && "Unexpected request for libcall!"); default: llvm_unreachable("Unexpected request for libcall!");
case MVT::f32: LC = Call_F32; break; case MVT::f32: LC = Call_F32; break;
case MVT::f64: LC = Call_F64; break; case MVT::f64: LC = Call_F64; break;
case MVT::f80: LC = Call_F80; break; case MVT::f80: LC = Call_F80; break;
@ -1883,7 +1883,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
RTLIB::Libcall Call_I128) { RTLIB::Libcall Call_I128) {
RTLIB::Libcall LC; RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT().SimpleTy) { switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: assert(0 && "Unexpected request for libcall!"); default: llvm_unreachable("Unexpected request for libcall!");
case MVT::i8: LC = Call_I8; break; case MVT::i8: LC = Call_I8; break;
case MVT::i16: LC = Call_I16; break; case MVT::i16: LC = Call_I16; break;
case MVT::i32: LC = Call_I32; break; case MVT::i32: LC = Call_I32; break;
@ -1898,7 +1898,7 @@ static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
const TargetLowering &TLI) { const TargetLowering &TLI) {
RTLIB::Libcall LC; RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT().SimpleTy) { switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: assert(0 && "Unexpected request for libcall!"); default: llvm_unreachable("Unexpected request for libcall!");
case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
@ -1943,7 +1943,7 @@ SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
RTLIB::Libcall LC; RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT().SimpleTy) { switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: assert(0 && "Unexpected request for libcall!"); default: llvm_unreachable("Unexpected request for libcall!");
case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
@ -2160,7 +2160,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
// offset depending on the data type. // offset depending on the data type.
uint64_t FF; uint64_t FF;
switch (Op0.getValueType().getSimpleVT().SimpleTy) { switch (Op0.getValueType().getSimpleVT().SimpleTy) {
default: assert(0 && "Unsupported integer type!"); default: llvm_unreachable("Unsupported integer type!");
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
@ -2282,7 +2282,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
EVT SHVT = TLI.getShiftAmountTy(VT); EVT SHVT = TLI.getShiftAmountTy(VT);
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
default: assert(0 && "Unhandled Expand type in BSWAP!"); default: llvm_unreachable("Unhandled Expand type in BSWAP!");
case MVT::i16: case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@ -2339,7 +2339,7 @@ static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
DebugLoc dl) { DebugLoc dl) {
switch (Opc) { switch (Opc) {
default: assert(0 && "Cannot expand this yet!"); default: llvm_unreachable("Cannot expand this yet!");
case ISD::CTPOP: { case ISD::CTPOP: {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
EVT ShVT = TLI.getShiftAmountTy(VT); EVT ShVT = TLI.getShiftAmountTy(VT);

4
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -672,7 +672,7 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
case ISD::SETUEQ: case ISD::SETUEQ:
LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break; break;
default: assert(false && "Do not know how to soften this setcc!"); default: llvm_unreachable("Do not know how to soften this setcc!");
} }
} }
@ -1212,7 +1212,7 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
switch (SrcVT.getSimpleVT().SimpleTy) { switch (SrcVT.getSimpleVT().SimpleTy) {
default: default:
assert(false && "Unsupported UINT_TO_FP!"); llvm_unreachable("Unsupported UINT_TO_FP!");
case MVT::i32: case MVT::i32:
Parts = TwoE32; Parts = TwoE32;
break; break;

2
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -2787,7 +2787,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
else if (SrcVT == MVT::i128) else if (SrcVT == MVT::i128)
FF = APInt(32, F32TwoE128); FF = APInt(32, F32TwoE128);
else else
assert(false && "Unsupported UINT_TO_FP!"); llvm_unreachable("Unsupported UINT_TO_FP!");
// Check whether the sign bit is set. // Check whether the sign bit is set.
SDValue Lo, Hi; SDValue Lo, Hi;

2
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -141,7 +141,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
EVT ValVT = ST->getValue().getValueType(); EVT ValVT = ST->getValue().getValueType();
if (StVT.isVector() && ST->isTruncatingStore()) if (StVT.isVector() && ST->isTruncatingStore())
switch (TLI.getTruncStoreAction(ValVT, StVT)) { switch (TLI.getTruncStoreAction(ValVT, StVT)) {
default: assert(0 && "This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal: case TargetLowering::Legal:
return TranslateLegalizeResults(Op, Result); return TranslateLegalizeResults(Op, Result);
case TargetLowering::Custom: case TargetLowering::Custom:

6
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1039,10 +1039,8 @@ SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
apf.convert(*EVTToAPFloatSemantics(EltVT), APFloat::rmNearestTiesToEven, apf.convert(*EVTToAPFloatSemantics(EltVT), APFloat::rmNearestTiesToEven,
&ignored); &ignored);
return getConstantFP(apf, VT, isTarget); return getConstantFP(apf, VT, isTarget);
} else { } else
assert(0 && "Unsupported type in getConstantFP"); llvm_unreachable("Unsupported type in getConstantFP");
return SDValue();
}
} }
SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, DebugLoc DL, SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, DebugLoc DL,