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[ARM] FP16 codegen support for VSEL

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This implements lowering of SELECT_CC for f16s, which enables
codegen of VSEL with f16 types.

Differential Revision: https://reviews.llvm.org/D44518

llvm-svn: 327695
This commit is contained in:
Sjoerd Meijer 2018-03-16 08:06:25 +00:00
parent 658a8b28bb
commit d21c6cef5d
3 changed files with 42 additions and 3 deletions
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1
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1048,6 +1048,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SELECT, MVT::i32, Custom); setOperationAction(ISD::SELECT, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::f32, Custom); setOperationAction(ISD::SELECT, MVT::f32, Custom);
setOperationAction(ISD::SELECT, MVT::f64, Custom); setOperationAction(ISD::SELECT, MVT::f64, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);

4
lib/Target/ARM/ARMInstrVFP.td
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@ -451,9 +451,9 @@ multiclass vsel_inst<string op, bits<2> opc, int CC> {
let DecoderNamespace = "VFPV8", PostEncoderMethod = "", let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
Uses = [CPSR], AddedComplexity = 4 in { Uses = [CPSR], AddedComplexity = 4 in {
def H : AHbInp<0b11100, opc, 0, def H : AHbInp<0b11100, opc, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
[]>, [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, CC))]>,
Requires<[HasFullFP16]>; Requires<[HasFullFP16]>;
def S : ASbInp<0b11100, opc, 0, def S : ASbInp<0b11100, opc, 0,

40
test/CodeGen/ARM/fp16-instructions.ll
View File

@ -687,6 +687,7 @@ entry:
; CHECK-HARDFP-FULLFP16: vnmul.f16 s0, s0, s1 ; CHECK-HARDFP-FULLFP16: vnmul.f16 s0, s0, s1
} }
; TODO:
; 28. VRINTA ; 28. VRINTA
; 29. VRINTM ; 29. VRINTM
; 30. VRINTN ; 30. VRINTN
@ -694,11 +695,48 @@ entry:
; 32. VRINTR ; 32. VRINTR
; 33. VRINTX ; 33. VRINTX
; 34. VRINTZ ; 34. VRINTZ
; 35. VSELEQ ; 35. VSELEQ
define half @select_cc1() {
%1 = fcmp nsz oeq half undef, 0xH0001
%2 = select i1 %1, half 0xHC000, half 0xH0002
ret half %2
; CHECK-LABEL: select_cc1:
; CHECK-HARDFP-FULLFP16: vseleq.f16 s0, s{{.}}, s{{.}}
}
; 36. VSELGE ; 36. VSELGE
define half @select_cc2() {
%1 = fcmp nsz oge half undef, 0xH0001
%2 = select i1 %1, half 0xHC000, half 0xH0002
ret half %2
; CHECK-LABEL: select_cc2:
; CHECK-HARDFP-FULLFP16: vselge.f16 s0, s{{.}}, s{{.}}
}
; 37. VSELGT ; 37. VSELGT
define half @select_cc3() {
%1 = fcmp nsz ogt half undef, 0xH0001
%2 = select i1 %1, half 0xHC000, half 0xH0002
ret half %2
; CHECK-LABEL: select_cc3:
; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
}
; 38. VSELVS ; 38. VSELVS
; 39. VSQRT define half @select_cc4() {
%1 = fcmp nsz ueq half undef, 0xH0001
%2 = select i1 %1, half 0xHC000, half 0xH0002
ret half %2
; CHECK-LABEL: select_cc4:
; CHECK-HARDFP-FULLFP16: vselvs.f16 s0, s{{.}}, s{{.}}
}
; 39. VSQRT - TODO
; 40. VSUB ; 40. VSUB
define float @Sub(float %a.coerce, float %b.coerce) { define float @Sub(float %a.coerce, float %b.coerce) {