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Fix PR14204
- Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled. llvm-svn: 166947
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@ -5850,6 +5850,21 @@ let Predicates = [HasAVX2] in {
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def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
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def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
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def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
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(VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
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(VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
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(VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
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(VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
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(VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
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(VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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}
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let Predicates = [HasAVX] in {
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15
test/CodeGen/X86/pr14204.ll
Normal file
15
test/CodeGen/X86/pr14204.ll
Normal file
@ -0,0 +1,15 @@
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; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=core-avx2 | FileCheck %s
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; FIXME: vpmovsxwd should be generated instead of vpmovzxwd followed by
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; SLL/SRA.
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define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
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entry:
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%s = sext <8 x i1> %bar to <8 x i32>
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ret <8 x i32> %s
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; CHECK: foo
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; CHECK: vpmovzxwd
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; CHECK: vpslld
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; CHECK: vpsrad
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; CHECK: ret
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}
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