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[Sparc] Add support for parsing branch instructions and conditional moves.
llvm-svn: 198738
This commit is contained in:
Venkatraman Govindaraju
parent
24d99bb391
commit
d26e61b5c9
@ -537,10 +537,30 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op)
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Parser.Lex(); // Eat the '%'.
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unsigned RegNo;
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if (matchRegisterName(Parser.getTok(), RegNo, false, false)) {
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StringRef name = Parser.getTok().getString();
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Parser.Lex(); // Eat the identifier token.
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E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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switch (RegNo) {
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default:
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Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E);
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break;
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case Sparc::Y:
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Op = SparcOperand::CreateToken("%y", S);
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break;
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case Sparc::ICC:
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if (name == "xcc")
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Op = SparcOperand::CreateToken("%xcc", S);
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else
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Op = SparcOperand::CreateToken("%icc", S);
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break;
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case Sparc::FCC:
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assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
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Op = SparcOperand::CreateToken("%fcc0", S);
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break;
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}
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break;
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}
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if (matchSparcAsmModifiers(EVal, E)) {
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E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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@ -82,6 +82,17 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
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raw_ostream &O)
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{
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int CC = (int)MI->getOperand(opNum).getImm();
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switch (MI->getOpcode()) {
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default: break;
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case SP::FBCOND:
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case SP::MOVFCCrr:
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case SP::MOVFCCri:
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case SP::FMOVS_FCC:
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case SP::FMOVD_FCC:
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case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag.
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CC = (CC < 16) ? (CC + 16) : CC;
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break;
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}
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O << SPARCCondCodeToString((SPCC::CondCodes)CC);
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}
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@ -333,32 +333,42 @@ class XBranchSP<dag ins, string asmstr, list<dag> pattern>
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let Predicates = [Is64Bit] in {
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let Uses = [ICC] in
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def BPXCC : XBranchSP<(ins brtarget:$imm22, CCOp:$cond),
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"b$cond %xcc, $imm22",
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[(SPbrxcc bb:$imm22, imm:$cond)]>;
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def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond),
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"b$cond %xcc, $imm19",
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[(SPbrxcc bb:$imm19, imm:$cond)]>;
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// Conditional moves on %xcc.
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let Uses = [ICC], Constraints = "$f = $rd" in {
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def MOVXCCrr : Pseudo<(outs IntRegs:$rd),
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let cc = 0b110 in {
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def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
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(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $rs2, $rd",
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[(set i32:$rd,
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(SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
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def MOVXCCri : Pseudo<(outs IntRegs:$rd),
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(ins i32imm:$i, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $i, $rd",
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def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
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(ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $simm11, $rd",
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[(set i32:$rd,
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(SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
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def FMOVS_XCC : Pseudo<(outs FPRegs:$rd),
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(SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
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} // cc
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let opf_cc = 0b110 in {
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def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
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(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
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"fmovs$cond %xcc, $rs2, $rd",
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[(set f32:$rd,
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(SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
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def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
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def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
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(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
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"fmovd$cond %xcc, $rs2, $rd",
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[(set f64:$rd,
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(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
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def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovq$cond %xcc, $rs2, $rd",
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[(set f128:$rd,
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(SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
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} // opf_cc
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} // Uses, Constraints
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//===----------------------------------------------------------------------===//
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119
lib/Target/Sparc/SparcInstrAliases.td
Normal file
119
lib/Target/Sparc/SparcInstrAliases.td
Normal file
@ -0,0 +1,119 @@
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//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction aliases for Sparc.
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//===----------------------------------------------------------------------===//
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// Instruction aliases for conditional moves.
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// mov<cond> <ccreg> rs2, rd
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multiclass cond_mov_alias<string cond, int condVal, string ccreg,
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Instruction movrr, Instruction movri,
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Instruction fmovs, Instruction fmovd> {
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// mov<cond> (%icc|%xcc|%fcc0), rs2, rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
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", $rs2, $rd"),
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(movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
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// mov<cond> (%icc|%xcc|%fcc0), simm11, rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
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", $simm11, $rd"),
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(movri IntRegs:$rd, i32imm:$simm11, condVal)>;
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// fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
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", $rs2, $rd"),
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(fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
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// fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
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", $rs2, $rd"),
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(fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
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}
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// Instruction aliases for integer conditional branches and moves.
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multiclass int_cond_alias<string cond, int condVal> {
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// b<cond> $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
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(BCOND brtarget:$imm, condVal)>;
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// b<cond> %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
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(BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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defm : cond_mov_alias<cond, condVal, " %icc",
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MOVICCrr, MOVICCri,
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FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
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defm : cond_mov_alias<cond, condVal, " %xcc",
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MOVXCCrr, MOVXCCri,
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FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
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// fmovq<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
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(FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[HasV9, HasHardQuad]>;
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
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(FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[Is64Bit, HasHardQuad]>;
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}
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// Instruction aliases for floating point conditional branches and moves.
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multiclass fp_cond_alias<string cond, int condVal> {
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// fb<cond> $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
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(FBCOND brtarget:$imm, condVal), 0>;
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defm : cond_mov_alias<cond, condVal, " %fcc0",
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MOVFCCrr, MOVFCCri,
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FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
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// fmovq<cond> %fcc0, $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
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(FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[HasV9, HasHardQuad]>;
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}
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defm : int_cond_alias<"a", 0b1000>;
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defm : int_cond_alias<"n", 0b0000>;
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defm : int_cond_alias<"ne", 0b1001>;
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defm : int_cond_alias<"e", 0b0001>;
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defm : int_cond_alias<"g", 0b1010>;
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defm : int_cond_alias<"le", 0b0010>;
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defm : int_cond_alias<"ge", 0b1011>;
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defm : int_cond_alias<"l", 0b0011>;
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defm : int_cond_alias<"gu", 0b1100>;
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defm : int_cond_alias<"leu", 0b0100>;
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defm : int_cond_alias<"cc", 0b1101>;
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defm : int_cond_alias<"cs", 0b0101>;
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defm : int_cond_alias<"pos", 0b1110>;
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defm : int_cond_alias<"neg", 0b0110>;
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defm : int_cond_alias<"vc", 0b1111>;
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defm : int_cond_alias<"vs", 0b0111>;
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defm : fp_cond_alias<"u", 0b0111>;
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defm : fp_cond_alias<"g", 0b0110>;
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defm : fp_cond_alias<"ug", 0b0101>;
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defm : fp_cond_alias<"l", 0b0100>;
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defm : fp_cond_alias<"ul", 0b0011>;
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defm : fp_cond_alias<"lg", 0b0010>;
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defm : fp_cond_alias<"ne", 0b0001>;
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defm : fp_cond_alias<"e", 0b1001>;
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defm : fp_cond_alias<"ue", 0b1010>;
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defm : fp_cond_alias<"ge", 0b1011>;
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defm : fp_cond_alias<"uge", 0b1100>;
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defm : fp_cond_alias<"le", 0b1101>;
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defm : fp_cond_alias<"ule", 0b1110>;
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defm : fp_cond_alias<"o", 0b1111>;
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@ -928,8 +928,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in {
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def FMOVQ_ICC
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: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovd$cond %icc, $rs2, $rd",
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[(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
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"fmovq$cond %icc, $rs2, $rd",
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[(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
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Requires<[HasHardQuad]>;
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}
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let Uses = [FCC], opf_cc = 0b000 in {
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@ -946,8 +947,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in {
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def FMOVQ_FCC
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: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovd$cond %fcc0, $rs2, $rd",
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[(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
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"fmovq$cond %fcc0, $rs2, $rd",
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[(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
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Requires<[HasHardQuad]>;
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}
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}
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@ -1092,3 +1094,4 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
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include "SparcInstr64Bit.td"
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include "SparcInstrAliases.td"
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@ -80,3 +80,90 @@
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# CHECK: subxcc %g1, %g2, %g3
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0x86 0xe0 0x40 0x02
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# CHECK: ba 4194303
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0x10 0xbf 0xff 0xff
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# CHECK: bne 4194303
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0x12 0xbf 0xff 0xff
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# CHECK: be 4194303
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0x02 0xbf 0xff 0xff
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# CHECK: bg 4194303
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0x14 0xbf 0xff 0xff
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# CHECK: ble 4194303
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0x04 0xbf 0xff 0xff
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# CHECK: bge 4194303
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0x16 0xbf 0xff 0xff
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# CHECK: bl 4194303
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0x06 0xbf 0xff 0xff
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# CHECK: bgu 4194303
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0x18 0xbf 0xff 0xff
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# CHECK: bleu 4194303
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0x08 0xbf 0xff 0xff
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# CHECK: bcc 4194303
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0x1a 0xbf 0xff 0xff
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# CHECK: bcs 4194303
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0x0a 0xbf 0xff 0xff
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# CHECK: bpos 4194303
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0x1c 0xbf 0xff 0xff
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# CHECK: bneg 4194303
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0x0c 0xbf 0xff 0xff
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# CHECK: bvc 4194303
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0x1e 0xbf 0xff 0xff
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# CHECK: bvs 4194303
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0x0e 0xbf 0xff 0xff
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# CHECK: fbu 4194303
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0x0f 0xbf 0xff 0xff
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# CHECK: fbg 4194303
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0x0d 0xbf 0xff 0xff
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# CHECK: fbug 4194303
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0x0b 0xbf 0xff 0xff
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# CHECK: fbl 4194303
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0x09 0xbf 0xff 0xff
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# CHECK: fbul 4194303
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0x07 0xbf 0xff 0xff
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# CHECK: fblg 4194303
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0x05 0xbf 0xff 0xff
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# CHECK: fbne 4194303
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0x03 0xbf 0xff 0xff
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# CHECK: fbe 4194303
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0x13 0xbf 0xff 0xff
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# CHECK: fbue 4194303
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0x15 0xbf 0xff 0xff
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# CHECK: fbge 4194303
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0x17 0xbf 0xff 0xff
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# CHECK: fbuge 4194303
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0x19 0xbf 0xff 0xff
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# CHECK: fble 4194303
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0x1b 0xbf 0xff 0xff
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# CHECK: fbule 4194303
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0x1d 0xbf 0xff 0xff
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# CHECK: fbo 4194303
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0x1f 0xbf 0xff 0xff
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@ -31,3 +31,117 @@
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! CHECK-NEXT: ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10
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jmp %g1+%lo(sym)
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! CHECK: ba .BB0 ! encoding: [0x10,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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ba .BB0
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! CHECK: bne .BB0 ! encoding: [0x12,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bne .BB0
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! CHECK: be .BB0 ! encoding: [0x02,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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be .BB0
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! CHECK: bg .BB0 ! encoding: [0x14,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bg .BB0
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! CHECK: ble .BB0 ! encoding: [0x04,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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ble .BB0
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! CHECK: bge .BB0 ! encoding: [0x16,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bge .BB0
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! CHECK: bl .BB0 ! encoding: [0x06,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bl .BB0
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! CHECK: bgu .BB0 ! encoding: [0x18,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bgu .BB0
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! CHECK: bleu .BB0 ! encoding: [0x08,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bleu .BB0
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! CHECK: bcc .BB0 ! encoding: [0x1a,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bcc .BB0
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! CHECK: bcs .BB0 ! encoding: [0x0a,0b10AAAAAA,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
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bcs .BB0
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|
||||
! CHECK: bpos .BB0 ! encoding: [0x1c,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
bpos .BB0
|
||||
|
||||
! CHECK: bneg .BB0 ! encoding: [0x0c,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
bneg .BB0
|
||||
|
||||
! CHECK: bvc .BB0 ! encoding: [0x1e,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
bvc .BB0
|
||||
|
||||
! CHECK: bvs .BB0 ! encoding: [0x0e,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
bvs .BB0
|
||||
|
||||
! CHECK: fbu .BB0 ! encoding: [0x0f,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbu .BB0
|
||||
|
||||
! CHECK: fbg .BB0 ! encoding: [0x0d,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbg .BB0
|
||||
! CHECK: fbug .BB0 ! encoding: [0x0b,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbug .BB0
|
||||
|
||||
! CHECK: fbl .BB0 ! encoding: [0x09,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbl .BB0
|
||||
|
||||
! CHECK: fbul .BB0 ! encoding: [0x07,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbul .BB0
|
||||
|
||||
! CHECK: fblg .BB0 ! encoding: [0x05,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fblg .BB0
|
||||
|
||||
! CHECK: fbne .BB0 ! encoding: [0x03,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbne .BB0
|
||||
|
||||
! CHECK: fbe .BB0 ! encoding: [0x13,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbe .BB0
|
||||
|
||||
! CHECK: fbue .BB0 ! encoding: [0x15,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbue .BB0
|
||||
|
||||
! CHECK: fbge .BB0 ! encoding: [0x17,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbge .BB0
|
||||
|
||||
! CHECK: fbuge .BB0 ! encoding: [0x19,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbuge .BB0
|
||||
|
||||
! CHECK: fble .BB0 ! encoding: [0x1b,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fble .BB0
|
||||
|
||||
! CHECK: fbule .BB0 ! encoding: [0x1d,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbule .BB0
|
||||
|
||||
! CHECK: fbo .BB0 ! encoding: [0x1f,0b10AAAAAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
|
||||
fbo .BB0
|
||||
|
||||
235
test/MC/Sparc/sparc64-ctrl-instructions.s
Normal file
235
test/MC/Sparc/sparc64-ctrl-instructions.s
Normal file
@ -0,0 +1,235 @@
|
||||
! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s
|
||||
|
||||
|
||||
! CHECK: bne %xcc, .BB0 ! encoding: [0x12,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bne %xcc, .BB0
|
||||
|
||||
! CHECK: be %xcc, .BB0 ! encoding: [0x02,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
be %xcc, .BB0
|
||||
|
||||
! CHECK: bg %xcc, .BB0 ! encoding: [0x14,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bg %xcc, .BB0
|
||||
|
||||
! CHECK: ble %xcc, .BB0 ! encoding: [0x04,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
ble %xcc, .BB0
|
||||
|
||||
! CHECK: bge %xcc, .BB0 ! encoding: [0x16,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bge %xcc, .BB0
|
||||
|
||||
! CHECK: bl %xcc, .BB0 ! encoding: [0x06,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bl %xcc, .BB0
|
||||
|
||||
! CHECK: bgu %xcc, .BB0 ! encoding: [0x18,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bgu %xcc, .BB0
|
||||
|
||||
! CHECK: bleu %xcc, .BB0 ! encoding: [0x08,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bleu %xcc, .BB0
|
||||
|
||||
! CHECK: bcc %xcc, .BB0 ! encoding: [0x1a,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bcc %xcc, .BB0
|
||||
|
||||
! CHECK: bcs %xcc, .BB0 ! encoding: [0x0a,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bcs %xcc, .BB0
|
||||
|
||||
! CHECK: bpos %xcc, .BB0 ! encoding: [0x1c,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bpos %xcc, .BB0
|
||||
|
||||
! CHECK: bneg %xcc, .BB0 ! encoding: [0x0c,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bneg %xcc, .BB0
|
||||
|
||||
! CHECK: bvc %xcc, .BB0 ! encoding: [0x1e,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bvc %xcc, .BB0
|
||||
|
||||
! CHECK: bvs %xcc, .BB0 ! encoding: [0x0e,0b01101AAA,A,A]
|
||||
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
|
||||
bvs %xcc, .BB0
|
||||
|
||||
|
||||
! CHECK: movne %icc, %g1, %g2 ! encoding: [0x85,0x66,0x40,0x01]
|
||||
! CHECK: move %icc, %g1, %g2 ! encoding: [0x85,0x64,0x40,0x01]
|
||||
! CHECK: movg %icc, %g1, %g2 ! encoding: [0x85,0x66,0x80,0x01]
|
||||
! CHECK: movle %icc, %g1, %g2 ! encoding: [0x85,0x64,0x80,0x01]
|
||||
! CHECK: movge %icc, %g1, %g2 ! encoding: [0x85,0x66,0xc0,0x01]
|
||||
! CHECK: movl %icc, %g1, %g2 ! encoding: [0x85,0x64,0xc0,0x01]
|
||||
! CHECK: movgu %icc, %g1, %g2 ! encoding: [0x85,0x67,0x00,0x01]
|
||||
! CHECK: movleu %icc, %g1, %g2 ! encoding: [0x85,0x65,0x00,0x01]
|
||||
! CHECK: movcc %icc, %g1, %g2 ! encoding: [0x85,0x67,0x40,0x01]
|
||||
! CHECK: movcs %icc, %g1, %g2 ! encoding: [0x85,0x65,0x40,0x01]
|
||||
! CHECK: movpos %icc, %g1, %g2 ! encoding: [0x85,0x67,0x80,0x01]
|
||||
! CHECK: movneg %icc, %g1, %g2 ! encoding: [0x85,0x65,0x80,0x01]
|
||||
! CHECK: movvc %icc, %g1, %g2 ! encoding: [0x85,0x67,0xc0,0x01]
|
||||
! CHECK: movvs %icc, %g1, %g2 ! encoding: [0x85,0x65,0xc0,0x01]
|
||||
movne %icc, %g1, %g2
|
||||
move %icc, %g1, %g2
|
||||
movg %icc, %g1, %g2
|
||||
movle %icc, %g1, %g2
|
||||
movge %icc, %g1, %g2
|
||||
movl %icc, %g1, %g2
|
||||
movgu %icc, %g1, %g2
|
||||
movleu %icc, %g1, %g2
|
||||
movcc %icc, %g1, %g2
|
||||
movcs %icc, %g1, %g2
|
||||
movpos %icc, %g1, %g2
|
||||
movneg %icc, %g1, %g2
|
||||
movvc %icc, %g1, %g2
|
||||
movvs %icc, %g1, %g2
|
||||
|
||||
! CHECK: movne %xcc, %g1, %g2 ! encoding: [0x85,0x66,0x50,0x01]
|
||||
! CHECK: move %xcc, %g1, %g2 ! encoding: [0x85,0x64,0x50,0x01]
|
||||
! CHECK: movg %xcc, %g1, %g2 ! encoding: [0x85,0x66,0x90,0x01]
|
||||
! CHECK: movle %xcc, %g1, %g2 ! encoding: [0x85,0x64,0x90,0x01]
|
||||
! CHECK: movge %xcc, %g1, %g2 ! encoding: [0x85,0x66,0xd0,0x01]
|
||||
! CHECK: movl %xcc, %g1, %g2 ! encoding: [0x85,0x64,0xd0,0x01]
|
||||
! CHECK: movgu %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x10,0x01]
|
||||
! CHECK: movleu %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x10,0x01]
|
||||
! CHECK: movcc %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x50,0x01]
|
||||
! CHECK: movcs %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x50,0x01]
|
||||
! CHECK: movpos %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x90,0x01]
|
||||
! CHECK: movneg %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x90,0x01]
|
||||
! CHECK: movvc %xcc, %g1, %g2 ! encoding: [0x85,0x67,0xd0,0x01]
|
||||
! CHECK: movvs %xcc, %g1, %g2 ! encoding: [0x85,0x65,0xd0,0x01]
|
||||
movne %xcc, %g1, %g2
|
||||
move %xcc, %g1, %g2
|
||||
movg %xcc, %g1, %g2
|
||||
movle %xcc, %g1, %g2
|
||||
movge %xcc, %g1, %g2
|
||||
movl %xcc, %g1, %g2
|
||||
movgu %xcc, %g1, %g2
|
||||
movleu %xcc, %g1, %g2
|
||||
movcc %xcc, %g1, %g2
|
||||
movcs %xcc, %g1, %g2
|
||||
movpos %xcc, %g1, %g2
|
||||
movneg %xcc, %g1, %g2
|
||||
movvc %xcc, %g1, %g2
|
||||
movvs %xcc, %g1, %g2
|
||||
|
||||
! CHECK: movu %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0xc0,0x01]
|
||||
! CHECK: movg %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x80,0x01]
|
||||
! CHECK: movug %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x40,0x01]
|
||||
! CHECK: movl %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x00,0x01]
|
||||
! CHECK: movul %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0xc0,0x01]
|
||||
! CHECK: movlg %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x80,0x01]
|
||||
! CHECK: movne %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x40,0x01]
|
||||
! CHECK: move %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x40,0x01]
|
||||
! CHECK: movue %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x80,0x01]
|
||||
! CHECK: movge %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0xc0,0x01]
|
||||
! CHECK: movuge %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x00,0x01]
|
||||
! CHECK: movle %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x40,0x01]
|
||||
! CHECK: movule %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x80,0x01]
|
||||
! CHECK: movo %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0xc0,0x01]
|
||||
movu %fcc0, %g1, %g2
|
||||
movg %fcc0, %g1, %g2
|
||||
movug %fcc0, %g1, %g2
|
||||
movl %fcc0, %g1, %g2
|
||||
movul %fcc0, %g1, %g2
|
||||
movlg %fcc0, %g1, %g2
|
||||
movne %fcc0, %g1, %g2
|
||||
move %fcc0, %g1, %g2
|
||||
movue %fcc0, %g1, %g2
|
||||
movge %fcc0, %g1, %g2
|
||||
movuge %fcc0, %g1, %g2
|
||||
movle %fcc0, %g1, %g2
|
||||
movule %fcc0, %g1, %g2
|
||||
movo %fcc0, %g1, %g2
|
||||
|
||||
|
||||
! CHECK fmovsne %icc, %f1, %f2 ! encoding: [0x85,0xaa,0x60,0x21]
|
||||
! CHECK fmovse %icc, %f1, %f2 ! encoding: [0x85,0xa8,0x60,0x21]
|
||||
! CHECK fmovsg %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xa0,0x21]
|
||||
! CHECK fmovsle %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xa0,0x21]
|
||||
! CHECK fmovsge %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xe0,0x21]
|
||||
! CHECK fmovsl %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xe0,0x21]
|
||||
! CHECK fmovsgu %icc, %f1, %f2 ! encoding: [0x85,0xab,0x20,0x21]
|
||||
! CHECK fmovsleu %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x20,0x21]
|
||||
! CHECK fmovscc %icc, %f1, %f2 ! encoding: [0x85,0xab,0x60,0x21]
|
||||
! CHECK fmovscs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x60,0x21]
|
||||
! CHECK fmovspos %icc, %f1, %f2 ! encoding: [0x85,0xab,0xa0,0x21]
|
||||
! CHECK fmovsneg %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xa0,0x21]
|
||||
! CHECK fmovsvc %icc, %f1, %f2 ! encoding: [0x85,0xab,0xe0,0x21]
|
||||
! CHECK fmovsvs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xe0,0x21]
|
||||
fmovsne %icc, %f1, %f2
|
||||
fmovse %icc, %f1, %f2
|
||||
fmovsg %icc, %f1, %f2
|
||||
fmovsle %icc, %f1, %f2
|
||||
fmovsge %icc, %f1, %f2
|
||||
fmovsl %icc, %f1, %f2
|
||||
fmovsgu %icc, %f1, %f2
|
||||
fmovsleu %icc, %f1, %f2
|
||||
fmovscc %icc, %f1, %f2
|
||||
fmovscs %icc, %f1, %f2
|
||||
fmovspos %icc, %f1, %f2
|
||||
fmovsneg %icc, %f1, %f2
|
||||
fmovsvc %icc, %f1, %f2
|
||||
fmovsvs %icc, %f1, %f2
|
||||
|
||||
! CHECK fmovsne %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0x70,0x21]
|
||||
! CHECK fmovse %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0x70,0x21]
|
||||
! CHECK fmovsg %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xb0,0x21]
|
||||
! CHECK fmovsle %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xb0,0x21]
|
||||
! CHECK fmovsge %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xf0,0x21]
|
||||
! CHECK fmovsl %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xf0,0x21]
|
||||
! CHECK fmovsgu %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x30,0x21]
|
||||
! CHECK fmovsleu %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x30,0x21]
|
||||
! CHECK fmovscc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x70,0x21]
|
||||
! CHECK fmovscs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x70,0x21]
|
||||
! CHECK fmovspos %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xb0,0x21]
|
||||
! CHECK fmovsneg %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xb0,0x21]
|
||||
! CHECK fmovsvc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xf0,0x21]
|
||||
! CHECK fmovsvs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xf0,0x21]
|
||||
fmovsne %xcc, %f1, %f2
|
||||
fmovse %xcc, %f1, %f2
|
||||
fmovsg %xcc, %f1, %f2
|
||||
fmovsle %xcc, %f1, %f2
|
||||
fmovsge %xcc, %f1, %f2
|
||||
fmovsl %xcc, %f1, %f2
|
||||
fmovsgu %xcc, %f1, %f2
|
||||
fmovsleu %xcc, %f1, %f2
|
||||
fmovscc %xcc, %f1, %f2
|
||||
fmovscs %xcc, %f1, %f2
|
||||
fmovspos %xcc, %f1, %f2
|
||||
fmovsneg %xcc, %f1, %f2
|
||||
fmovsvc %xcc, %f1, %f2
|
||||
fmovsvs %xcc, %f1, %f2
|
||||
|
||||
! CHECK fmovsu %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0xc0,0x21]
|
||||
! CHECK fmovsg %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x80,0x21]
|
||||
! CHECK fmovsug %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x40,0x21]
|
||||
! CHECK fmovsl %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x00,0x21]
|
||||
! CHECK fmovsul %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0xc0,0x21]
|
||||
! CHECK fmovslg %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x80,0x21]
|
||||
! CHECK fmovsne %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x40,0x21]
|
||||
! CHECK fmovse %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x40,0x21]
|
||||
! CHECK fmovsue %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x80,0x21]
|
||||
! CHECK fmovsge %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0xc0,0x21]
|
||||
! CHECK fmovsuge %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x00,0x21]
|
||||
! CHECK fmovsle %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x40,0x21]
|
||||
! CHECK fmovsule %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x80,0x21]
|
||||
! CHECK fmovso %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0xc0,0x21]
|
||||
fmovsu %fcc0, %f1, %f2
|
||||
fmovsg %fcc0, %f1, %f2
|
||||
fmovsug %fcc0, %f1, %f2
|
||||
fmovsl %fcc0, %f1, %f2
|
||||
fmovsul %fcc0, %f1, %f2
|
||||
fmovslg %fcc0, %f1, %f2
|
||||
fmovsne %fcc0, %f1, %f2
|
||||
fmovse %fcc0, %f1, %f2
|
||||
fmovsue %fcc0, %f1, %f2
|
||||
fmovsge %fcc0, %f1, %f2
|
||||
fmovsuge %fcc0, %f1, %f2
|
||||
fmovsle %fcc0, %f1, %f2
|
||||
fmovsule %fcc0, %f1, %f2
|
||||
fmovso %fcc0, %f1, %f2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user