RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00
Code Issues Projects Releases Wiki Activity

[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT

Browse Source 
There's no need to call verifyVectorElementMatch since we already know
that the source and destination types are identical.

Differential Revision: https://reviews.llvm.org/D96589
This commit is contained in:
Jay Foad 2021-02-12 11:29:13 +00:00
parent 6bb03a7eef
commit d27645b72c
3 changed files with 2 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/MachineVerifier.cpp
View File

@ -949,9 +949,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
Register Dst = MI->getOperand(0).getReg();
Register Src = MI->getOperand(1).getReg();
LLT DstTy = MRI->getType(Dst);
LLT SrcTy = MRI->getType(Src);
verifyVectorElementMatch(DstTy, SrcTy, MI);
int64_t Imm = MI->getOperand(2).getImm();
if (Imm <= 0) {
report("G_ASSERT_ZEXT size must be >= 1", MI);
@ -1398,10 +1396,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
break;
}
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
verifyVectorElementMatch(DstTy, SrcTy, MI);
int64_t Imm = MI->getOperand(2).getImm();
if (Imm <= 0)
report("G_SEXT_INREG size must be >= 1", MI);

4
test/MachineVerifier/test_g_assert_zext.mir
View File

@ -19,11 +19,9 @@ body: |
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
%assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT %0, 8
; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT
%assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT %1, 8

4
test/MachineVerifier/test_g_sext_inreg.mir
View File

@ -36,11 +36,9 @@ body: |
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
%4(<2 x s32>) = G_SEXT_INREG %0, 8
; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
%5(<2 x s32>) = G_SEXT_INREG %1, 8