RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

[InstCombine] Fix a crash in getSelectCondition if we happen to have two inverse vectors of i1 constants.

Browse Source 
We used to try to truncate the constant vector to vXi1, but if it's already i1 this would fail. Instead we now use IRBuilder::getZExtOrTrunc which should check the type and only create a trunc if needed. I believe this should trigger constant folding in the IRBuilder and ultimately do the same thing just with the additional type check.

llvm-svn: 310639
This commit is contained in:
Craig Topper 2017-08-10 17:48:14 +00:00
parent 3a6cf94f85
commit d294d8b0ac
2 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
View File

@ -1494,8 +1494,9 @@ static Value *getSelectCondition(Value *A, Value *B,
// If both operands are constants, see if the constants are inverse bitmasks.
Constant *AC, *BC;
if (match(A, m_Constant(AC)) && match(B, m_Constant(BC)) &&
areInverseVectorBitmasks(AC, BC))
return ConstantExpr::getTrunc(AC, CmpInst::makeCmpResultType(Ty));
areInverseVectorBitmasks(AC, BC)) {
return Builder.CreateZExtOrTrunc(AC, CmpInst::makeCmpResultType(Ty));
}
// If both operands are xor'd with constants using the same sexted boolean
// operand, see if the constants are inverse bitmasks.

12
test/Transforms/InstCombine/or.ll
View File

@ -828,3 +828,15 @@ define i1 @orn_and_cmp_4(i32 %a, i32 %b, i32 %c) {
%or = or i1 %and, %x_inv
ret i1 %or
}
; The constant vectors are inverses. Make sure we can turn this into a select without crashing trying to truncate the constant to 16xi1.
define <16 x i1> @test51(<16 x i1> %arg, <16 x i1> %arg1) {
; CHECK-LABEL: @test51(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i1> [[ARG:%.*]], <16 x i1> [[ARG1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 24, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: ret <16 x i1> [[TMP1]]
;
%tmp = and <16 x i1> %arg, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
%tmp2 = and <16 x i1> %arg1, <i1 false, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true>
%tmp3 = or <16 x i1> %tmp, %tmp2
ret <16 x i1> %tmp3
}