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Make some arrays 'static const'

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llvm-svn: 186307
This commit is contained in:
Craig Topper 2013-07-15 06:39:13 +00:00
parent 38ebc8e7f2
commit d2ea089f09
4 changed files with 11 additions and 11 deletions
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2
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -78,7 +78,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::UDIVREM, MVT::i32, Custom); setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
setOperationAction(ISD::UREM, MVT::i32, Expand); setOperationAction(ISD::UREM, MVT::i32, Expand);
int types[] = { static const int types[] = {
(int)MVT::v2i32, (int)MVT::v2i32,
(int)MVT::v4i32 (int)MVT::v4i32
}; };

8
lib/Target/R600/AMDILISelLowering.cpp
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@ -39,7 +39,7 @@ using namespace llvm;
// TargetLowering Class Implementation Begins // TargetLowering Class Implementation Begins
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void AMDGPUTargetLowering::InitAMDILLowering() { void AMDGPUTargetLowering::InitAMDILLowering() {
int types[] = { static const int types[] = {
(int)MVT::i8, (int)MVT::i8,
(int)MVT::i16, (int)MVT::i16,
(int)MVT::i32, (int)MVT::i32,
@ -58,19 +58,19 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
(int)MVT::v2i64 (int)MVT::v2i64
}; };
int IntTypes[] = { static const int IntTypes[] = {
(int)MVT::i8, (int)MVT::i8,
(int)MVT::i16, (int)MVT::i16,
(int)MVT::i32, (int)MVT::i32,
(int)MVT::i64 (int)MVT::i64
}; };
int FloatTypes[] = { static const int FloatTypes[] = {
(int)MVT::f32, (int)MVT::f32,
(int)MVT::f64 (int)MVT::f64
}; };
int VectorTypes[] = { static const int VectorTypes[] = {
(int)MVT::v2i8, (int)MVT::v2i8,
(int)MVT::v4i8, (int)MVT::v4i8,
(int)MVT::v2i16, (int)MVT::v2i16,

2
lib/Target/R600/R600ControlFlowFinalizer.cpp
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@ -172,7 +172,7 @@ private:
} }
void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const { void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const {
unsigned LiteralRegs[] = { static const unsigned LiteralRegs[] = {
AMDGPU::ALU_LITERAL_X, AMDGPU::ALU_LITERAL_X,
AMDGPU::ALU_LITERAL_Y, AMDGPU::ALU_LITERAL_Y,
AMDGPU::ALU_LITERAL_Z, AMDGPU::ALU_LITERAL_Z,

10
lib/Target/R600/SIInstrInfo.cpp
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@ -42,27 +42,27 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// never be necessary. // never be necessary.
assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
const int16_t Sub0_15[] = { static const int16_t Sub0_15[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
}; };
const int16_t Sub0_7[] = { static const int16_t Sub0_7[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
}; };
const int16_t Sub0_3[] = { static const int16_t Sub0_3[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
}; };
const int16_t Sub0_2[] = { static const int16_t Sub0_2[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
}; };
const int16_t Sub0_1[] = { static const int16_t Sub0_1[] = {
AMDGPU::sub0, AMDGPU::sub1, 0 AMDGPU::sub0, AMDGPU::sub1, 0
}; };