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[ARM] Better patterns for fp <> predicate vectors
These are some better patterns for converting between predicates and floating points. Much like the extends, we select "1"/"-1" or "0" depending on the predicate value. Or we perform a compare against 0 to convert to a predicate. Differential Revision: https://reviews.llvm.org/D65103 llvm-svn: 367191
This commit is contained in:
David Green
parent
be00ed3113
commit
d3183024b0
@ -349,10 +349,6 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
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setOperationAction(ISD::FP_TO_SINT, VT, Expand);
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setOperationAction(ISD::FP_TO_UINT, VT, Expand);
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setOperationAction(ISD::SINT_TO_FP, VT, Expand);
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setOperationAction(ISD::UINT_TO_FP, VT, Expand);
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}
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}
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@ -4561,6 +4561,7 @@ let Predicates = [HasMVEInt] in {
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(v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0,
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(MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), 1)))>;
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// Pred <-> Int
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def : Pat<(v16i8 (zext (v16i1 VCCR:$pred))),
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(v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), 0, VCCR:$pred))>;
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def : Pat<(v8i16 (zext (v8i1 VCCR:$pred))),
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@ -4583,6 +4584,31 @@ let Predicates = [HasMVEInt] in {
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(v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), 0, VCCR:$pred))>;
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}
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let Predicates = [HasMVEFloat] in {
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// Pred <-> Float
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// 112 is 1.0 in float
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def : Pat<(v4f32 (uint_to_fp (v4i1 VCCR:$pred))),
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(v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 112)), (v4f32 (MVE_VMOVimmi32 0)), 0, VCCR:$pred))>;
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// 2620 in 1.0 in half
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def : Pat<(v8f16 (uint_to_fp (v8i1 VCCR:$pred))),
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(v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2620)), (v8f16 (MVE_VMOVimmi16 0)), 0, VCCR:$pred))>;
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// 240 is -1.0 in float
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def : Pat<(v4f32 (sint_to_fp (v4i1 VCCR:$pred))),
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(v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 240)), (v4f32 (MVE_VMOVimmi32 0)), 0, VCCR:$pred))>;
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// 2748 is -1.0 in half
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def : Pat<(v8f16 (sint_to_fp (v8i1 VCCR:$pred))),
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(v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2748)), (v8f16 (MVE_VMOVimmi16 0)), 0, VCCR:$pred))>;
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def : Pat<(v4i1 (fp_to_uint (v4f32 MQPR:$v1))),
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(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, 1))>;
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def : Pat<(v8i1 (fp_to_uint (v8f16 MQPR:$v1))),
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(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, 1))>;
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def : Pat<(v4i1 (fp_to_sint (v4f32 MQPR:$v1))),
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(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, 1))>;
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def : Pat<(v8i1 (fp_to_sint (v8f16 MQPR:$v1))),
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(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, 1))>;
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}
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def MVE_VPNOT : MVE_p<(outs), (ins), NoItinerary,
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"vpnot", "", "", vpred_n, "", []> {
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let Inst{31-0} = 0b11111110001100010000111101001101;
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@ -166,20 +166,10 @@ entry:
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define arm_aapcs_vfpcc <4 x float> @uitofp_v4i1_v4f32(<4 x i32> %src) {
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; CHECK-LABEL: uitofp_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vcmp.s32 gt, q0, zr
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: ubfx r1, r0, #8, #1
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; CHECK-NEXT: ubfx r2, r0, #12, #1
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; CHECK-NEXT: vmov s0, r2
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: vcvt.f32.u32 s3, s0
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; CHECK-NEXT: ubfx r2, r0, #4, #1
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; CHECK-NEXT: vcvt.f32.u32 s2, s4
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: vmov s4, r2
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; CHECK-NEXT: vcvt.f32.u32 s1, s4
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; CHECK-NEXT: vmov s4, r0
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; CHECK-NEXT: vcvt.f32.u32 s0, s4
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <4 x i32> %src, zeroinitializer
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@ -190,24 +180,10 @@ entry:
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define arm_aapcs_vfpcc <4 x float> @sitofp_v4i1_v4f32(<4 x i32> %src) {
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; CHECK-LABEL: sitofp_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.f32 q2, #-1.000000e+00
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; CHECK-NEXT: vcmp.s32 gt, q0, zr
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: and r1, r0, #1
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; CHECK-NEXT: ubfx r2, r0, #8, #1
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; CHECK-NEXT: ubfx r3, r0, #4, #1
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; CHECK-NEXT: ubfx r0, r0, #12, #1
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; CHECK-NEXT: rsbs r2, r2, #0
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; CHECK-NEXT: rsbs r0, r0, #0
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; CHECK-NEXT: vmov s4, r2
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: rsbs r0, r3, #0
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; CHECK-NEXT: vcvt.f32.s32 s3, s0
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; CHECK-NEXT: vcvt.f32.s32 s2, s4
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; CHECK-NEXT: vmov s4, r0
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; CHECK-NEXT: rsbs r0, r1, #0
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; CHECK-NEXT: vcvt.f32.s32 s1, s4
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; CHECK-NEXT: vmov s4, r0
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; CHECK-NEXT: vcvt.f32.s32 s0, s4
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <4 x i32> %src, zeroinitializer
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@ -218,26 +194,9 @@ entry:
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define arm_aapcs_vfpcc <4 x float> @fptoui_v4i1_v4f32(<4 x float> %src) {
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; CHECK-LABEL: fptoui_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcvt.s32.f32 s4, s0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vcvt.s32.f32 s4, s1
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: bfi r0, r1, #0, #4
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vcvt.s32.f32 s4, s2
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; CHECK-NEXT: vcvt.s32.f32 s0, s3
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: bfi r0, r1, #4, #4
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: bfi r0, r1, #8, #4
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: bfi r0, r1, #12, #4
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vcmp.f32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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@ -249,22 +208,9 @@ entry:
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define arm_aapcs_vfpcc <4 x float> @fptosi_v4i1_v4f32(<4 x float> %src) {
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; CHECK-LABEL: fptosi_v4i1_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcvt.s32.f32 s4, s0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vcvt.s32.f32 s4, s1
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; CHECK-NEXT: bfi r0, r1, #0, #4
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vcvt.s32.f32 s4, s2
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; CHECK-NEXT: bfi r0, r1, #4, #4
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; CHECK-NEXT: vcvt.s32.f32 s0, s3
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: bfi r0, r1, #8, #4
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bfi r0, r1, #12, #4
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
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; CHECK-NEXT: vcmp.f32 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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@ -273,3 +219,60 @@ entry:
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ret <4 x float> %s
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}
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define arm_aapcs_vfpcc <8 x half> @uitofp_v8i1_v8f16(<8 x i16> %src) {
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; CHECK-LABEL: uitofp_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x3c00
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; CHECK-NEXT: vcmp.s16 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <8 x i16> %src, zeroinitializer
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%0 = uitofp <8 x i1> %c to <8 x half>
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <8 x half> @sitofp_v8i1_v8f16(<8 x i16> %src) {
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; CHECK-LABEL: sitofp_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0xbc00
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; CHECK-NEXT: vcmp.s16 gt, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp sgt <8 x i16> %src, zeroinitializer
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%0 = sitofp <8 x i1> %c to <8 x half>
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <8 x half> @fptoui_v8i1_v8f16(<8 x half> %src) {
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; CHECK-LABEL: fptoui_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x3c00
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; CHECK-NEXT: vcmp.f16 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = fptoui <8 x half> %src to <8 x i1>
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%s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
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ret <8 x half> %s
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}
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define arm_aapcs_vfpcc <8 x half> @fptosi_v8i1_v8f16(<8 x half> %src) {
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; CHECK-LABEL: fptosi_v8i1_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vmov.i16 q2, #0x3c00
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; CHECK-NEXT: vcmp.f16 ne, q0, zr
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; CHECK-NEXT: vpsel q0, q2, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = fptosi <8 x half> %src to <8 x i1>
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%s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
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ret <8 x half> %s
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}
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