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Add first bunch of SPE instructions. As they overlap with Altivec, mark
them as parser-only until the disassembler is extended to handle predicates properly. llvm-svn: 215102
This commit is contained in:
Joerg Sonnenberger
parent
bd7efdfe72
commit
d344d15c74
@ -56,6 +56,8 @@ def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
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"Use condition-register bits individually">;
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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"Enable Altivec instructions">;
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def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
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"Enable SPE instructions">;
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def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
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"Enable the MFOCRF instruction">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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@ -632,6 +632,7 @@ def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
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def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
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def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
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def IsE500 : Predicate<"PPCSubTarget->isE500()">;
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def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
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//===----------------------------------------------------------------------===//
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// PowerPC Multiclass Definitions.
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@ -2521,6 +2522,7 @@ def : Pat<(fcopysign f32:$frB, f64:$frA),
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(FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
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include "PPCInstrAltivec.td"
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include "PPCInstrSPE.td"
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include "PPCInstr64Bit.td"
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include "PPCInstrVSX.td"
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@ -3325,6 +3327,9 @@ def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
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def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
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def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
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def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
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def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
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def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
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def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
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@ -3637,4 +3642,3 @@ defm : TrapExtendedMnemonic<"lgt", 1>;
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defm : TrapExtendedMnemonic<"lnl", 5>;
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defm : TrapExtendedMnemonic<"lng", 6>;
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defm : TrapExtendedMnemonic<"u", 31>;
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68
lib/Target/PowerPC/PPCInstrSPE.td
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68
lib/Target/PowerPC/PPCInstrSPE.td
Normal file
@ -0,0 +1,68 @@
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//=======-- PPCInstrSPE.td - The PowerPC SPE Extension -*- tablegen -*-=======//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Signal Processing Engine extension to
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// the PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> {
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bits<5> RT;
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bits<5> RA;
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bits<5> RB;
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let Pattern = [];
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let Inst{6-10} = RT;
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let Inst{11-15} = RA;
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let Inst{16-20} = RB;
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let Inst{21-31} = xo;
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}
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let Predicates = [HasSPE], isAsmParserOnly = 1 in {
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def EVMRA : EVXForm_1<1220, (outs gprc:$RT), (ins gprc:$RA),
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"evmra $RT, $RA", IIC_VecFP> {
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let RB = 0;
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}
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def EVLDDX : EVXForm_1<768, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlddx $RT, $RA, $RB", IIC_VecFP>;
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def EVLDWX : EVXForm_1<770, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evldwx $RT, $RA, $RB", IIC_VecFP>;
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def EVLDHX : EVXForm_1<772, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evldhx $RT, $RA, $RB", IIC_VecFP>;
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def EVLHHESPLATX : EVXForm_1<776, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlhhesplatx $RT, $RA, $RB", IIC_VecFP>;
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def EVLHHOUSPLATX : EVXForm_1<780, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlhhousplatx $RT, $RA, $RB", IIC_VecFP>;
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def EVLHHOSSPLATX : EVXForm_1<782, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlhhossplatx $RT, $RA, $RB", IIC_VecFP>;
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def EVLWHEX : EVXForm_1<784, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlwhex $RT, $RA, $RB", IIC_VecFP>;
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def EVLWHOUX : EVXForm_1<788, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlwhoux $RT, $RA, $RB", IIC_VecFP>;
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def EVLWHOSX : EVXForm_1<790, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlwhosx $RT, $RA, $RB", IIC_VecFP>;
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def EVLWWSPLATX : EVXForm_1<792, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlwwsplatx $RT, $RA, $RB", IIC_VecFP>;
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def EVLWHSPLATX : EVXForm_1<796, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evlwhsplatx $RT, $RA, $RB", IIC_VecFP>;
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def EVMERGEHI : EVXForm_1<556, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evmergehi $RT, $RA, $RB", IIC_VecFP>;
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def EVMERGELO : EVXForm_1<557, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evmergelo $RT, $RA, $RB", IIC_VecFP>;
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def EVMERGEHILO : EVXForm_1<558, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evmergehilo $RT, $RA, $RB", IIC_VecFP>;
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def EVMERGELOHI : EVXForm_1<559, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"evmergelohi $RT, $RA, $RB", IIC_VecFP>;
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} // HasSPE
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@ -119,6 +119,7 @@ void PPCSubtarget::initializeEnvironment() {
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Use64BitRegs = false;
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UseCRBits = false;
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HasAltivec = false;
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HasSPE = false;
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HasQPX = false;
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HasVSX = false;
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HasFCPSGN = false;
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@ -83,6 +83,7 @@ protected:
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bool UseCRBits;
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bool IsPPC64;
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bool HasAltivec;
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bool HasSPE;
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bool HasQPX;
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bool HasVSX;
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bool HasFCPSGN;
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@ -225,6 +226,7 @@ public:
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bool hasFPRND() const { return HasFPRND; }
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bool hasFPCVT() const { return HasFPCVT; }
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bool hasAltivec() const { return HasAltivec; }
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bool hasSPE() const { return HasSPE; }
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bool hasQPX() const { return HasQPX; }
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bool hasVSX() const { return HasVSX; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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50
test/MC/PowerPC/ppc64-encoding-spe.s
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50
test/MC/PowerPC/ppc64-encoding-spe.s
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@ -0,0 +1,50 @@
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
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# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
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# Instructions from the Signal Processing Engine extension:
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# CHECK-BE: evlddx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x00]
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# CHECK-LE: evlddx 14, 21, 28 # encoding: [0x00,0xe3,0xd5,0x11]
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evlddx %r14, %r21, %r28
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# CHECK-BE: evldwx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x02]
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# CHECK-LE: evldwx 14, 21, 28 # encoding: [0x02,0xe3,0xd5,0x11]
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evldwx %r14, %r21, %r28
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# CHECK-BE: evldhx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x04]
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# CHECK-LE: evldhx 14, 21, 28 # encoding: [0x04,0xe3,0xd5,0x11]
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evldhx %r14, %r21, %r28
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# CHECK-BE: evlhhesplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x08]
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# CHECK-LE: evlhhesplatx 14, 21, 28 # encoding: [0x08,0xe3,0xd5,0x11]
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evlhhesplatx %r14, %r21, %r28
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# CHECK-BE: evlhhousplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x0c]
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# CHECK-LE: evlhhousplatx 14, 21, 28 # encoding: [0x0c,0xe3,0xd5,0x11]
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evlhhousplatx %r14, %r21, %r28
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# CHECK-BE: evlhhossplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x0e]
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# CHECK-LE: evlhhossplatx 14, 21, 28 # encoding: [0x0e,0xe3,0xd5,0x11]
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evlhhossplatx %r14, %r21, %r28
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# CHECK-BE: evlwhex 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x10]
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# CHECK-LE: evlwhex 14, 21, 28 # encoding: [0x10,0xe3,0xd5,0x11]
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evlwhex %r14, %r21, %r28
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# CHECK-BE: evlwhoux 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x14]
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# CHECK-LE: evlwhoux 14, 21, 28 # encoding: [0x14,0xe3,0xd5,0x11]
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evlwhoux %r14, %r21, %r28
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# CHECK-BE: evlwhosx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x16]
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# CHECK-LE: evlwhosx 14, 21, 28 # encoding: [0x16,0xe3,0xd5,0x11]
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evlwhosx %r14, %r21, %r28
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# CHECK-BE: evlwwsplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x18]
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# CHECK-LE: evlwwsplatx 14, 21, 28 # encoding: [0x18,0xe3,0xd5,0x11]
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evlwwsplatx %r14, %r21, %r28
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# CHECK-BE: evlwhsplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x1c]
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# CHECK-LE: evlwhsplatx 14, 21, 28 # encoding: [0x1c,0xe3,0xd5,0x11]
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evlwhsplatx %r14, %r21, %r28
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# CHECK-BE: evmergehi 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2c]
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# CHECK-LE: evmergehi 14, 21, 28 # encoding: [0x2c,0xe2,0xd5,0x11]
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evmergehi %r14, %r21, %r28
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# CHECK-BE: evmergelo 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2d]
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# CHECK-LE: evmergelo 14, 21, 28 # encoding: [0x2d,0xe2,0xd5,0x11]
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evmergelo %r14, %r21, %r28
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# CHECK-BE: evmergehilo 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2e]
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# CHECK-LE: evmergehilo 14, 21, 28 # encoding: [0x2e,0xe2,0xd5,0x11]
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evmergehilo %r14, %r21, %r28
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# CHECK-BE: evmergelohi 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2f]
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# CHECK-LE: evmergelohi 14, 21, 28 # encoding: [0x2f,0xe2,0xd5,0x11]
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evmergelohi %r14, %r21, %r28
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