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CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis

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This avoids rerunning it a few times.
This commit is contained in:
Matt Arsenault 2021-05-12 17:10:24 -04:00
parent de55d90906
commit d3598a0449
3 changed files with 2 additions and 7 deletions
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4
lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
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@ -93,7 +93,7 @@ static const char ore_name[] = "Machine Optimization Remark Emitter";
#define ORE_NAME "machine-opt-remark-emitter" #define ORE_NAME "machine-opt-remark-emitter"
INITIALIZE_PASS_BEGIN(MachineOptimizationRemarkEmitterPass, ORE_NAME, ore_name, INITIALIZE_PASS_BEGIN(MachineOptimizationRemarkEmitterPass, ORE_NAME, ore_name,
false, true) true, true)
INITIALIZE_PASS_DEPENDENCY(LazyMachineBlockFrequencyInfoPass) INITIALIZE_PASS_DEPENDENCY(LazyMachineBlockFrequencyInfoPass)
INITIALIZE_PASS_END(MachineOptimizationRemarkEmitterPass, ORE_NAME, ore_name, INITIALIZE_PASS_END(MachineOptimizationRemarkEmitterPass, ORE_NAME, ore_name,
false, true) true, true)

4
test/CodeGen/AMDGPU/llc-pipeline.ll
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@ -338,7 +338,6 @@
; GCN-O1-NEXT: SI lower SGPR spill instructions ; GCN-O1-NEXT: SI lower SGPR spill instructions
; GCN-O1-NEXT: Virtual Register Map ; GCN-O1-NEXT: Virtual Register Map
; GCN-O1-NEXT: Live Register Matrix ; GCN-O1-NEXT: Live Register Matrix
; GCN-O1-NEXT: Machine Optimization Remark Emitter
; GCN-O1-NEXT: Greedy Register Allocator ; GCN-O1-NEXT: Greedy Register Allocator
; GCN-O1-NEXT: GCN NSA Reassign ; GCN-O1-NEXT: GCN NSA Reassign
; GCN-O1-NEXT: Virtual Register Rewriter ; GCN-O1-NEXT: Virtual Register Rewriter
@ -620,7 +619,6 @@
; GCN-O1-OPTS-NEXT: SI lower SGPR spill instructions ; GCN-O1-OPTS-NEXT: SI lower SGPR spill instructions
; GCN-O1-OPTS-NEXT: Virtual Register Map ; GCN-O1-OPTS-NEXT: Virtual Register Map
; GCN-O1-OPTS-NEXT: Live Register Matrix ; GCN-O1-OPTS-NEXT: Live Register Matrix
; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter
; GCN-O1-OPTS-NEXT: Greedy Register Allocator ; GCN-O1-OPTS-NEXT: Greedy Register Allocator
; GCN-O1-OPTS-NEXT: GCN NSA Reassign ; GCN-O1-OPTS-NEXT: GCN NSA Reassign
; GCN-O1-OPTS-NEXT: Virtual Register Rewriter ; GCN-O1-OPTS-NEXT: Virtual Register Rewriter
@ -905,7 +903,6 @@
; GCN-O2-NEXT: SI lower SGPR spill instructions ; GCN-O2-NEXT: SI lower SGPR spill instructions
; GCN-O2-NEXT: Virtual Register Map ; GCN-O2-NEXT: Virtual Register Map
; GCN-O2-NEXT: Live Register Matrix ; GCN-O2-NEXT: Live Register Matrix
; GCN-O2-NEXT: Machine Optimization Remark Emitter
; GCN-O2-NEXT: Greedy Register Allocator ; GCN-O2-NEXT: Greedy Register Allocator
; GCN-O2-NEXT: GCN NSA Reassign ; GCN-O2-NEXT: GCN NSA Reassign
; GCN-O2-NEXT: Virtual Register Rewriter ; GCN-O2-NEXT: Virtual Register Rewriter
@ -1203,7 +1200,6 @@
; GCN-O3-NEXT: SI lower SGPR spill instructions ; GCN-O3-NEXT: SI lower SGPR spill instructions
; GCN-O3-NEXT: Virtual Register Map ; GCN-O3-NEXT: Virtual Register Map
; GCN-O3-NEXT: Live Register Matrix ; GCN-O3-NEXT: Live Register Matrix
; GCN-O3-NEXT: Machine Optimization Remark Emitter
; GCN-O3-NEXT: Greedy Register Allocator ; GCN-O3-NEXT: Greedy Register Allocator
; GCN-O3-NEXT: GCN NSA Reassign ; GCN-O3-NEXT: GCN NSA Reassign
; GCN-O3-NEXT: Virtual Register Rewriter ; GCN-O3-NEXT: Virtual Register Rewriter

1
test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
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@ -20,7 +20,6 @@
; DEFAULT-NEXT: SI lower SGPR spill instructions ; DEFAULT-NEXT: SI lower SGPR spill instructions
; DEFAULT-NEXT: Virtual Register Map ; DEFAULT-NEXT: Virtual Register Map
; DEFAULT-NEXT: Live Register Matrix ; DEFAULT-NEXT: Live Register Matrix
; DEFAULT-NEXT: Machine Optimization Remark Emitter
; DEFAULT-NEXT: Greedy Register Allocator ; DEFAULT-NEXT: Greedy Register Allocator
; DEFAULT-NEXT: GCN NSA Reassign ; DEFAULT-NEXT: GCN NSA Reassign
; DEFAULT-NEXT: Virtual Register Rewriter ; DEFAULT-NEXT: Virtual Register Rewriter