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https://github.com/RPCS3/llvm-mirror.git
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[AArch64LoadStoreOptimizer] Skip debug insts during pattern matching [12/14]
Do not count the presence of debug insts against the limit set by LdStLimit, and allow the optimizer to find matching insts by skipping over debug insts. Differential Revision: https://reviews.llvm.org/D78411
This commit is contained in:
Vedant Kumar
parent
3b1d3cce73
commit
d36c3656f3
@ -678,14 +678,14 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
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assert(isPromotableZeroStoreInst(*I) && isPromotableZeroStoreInst(*MergeMI) &&
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"Expected promotable zero stores.");
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MachineBasicBlock::iterator NextI = I;
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++NextI;
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator NextI = next_nodbg(I, E);
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// If NextI is the second of the two instructions to be merged, we need
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// to skip one further. Either way we merge will invalidate the iterator,
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// and we don't need to scan the new instruction, as it's a pairwise
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// instruction, which we're not considering for further action anyway.
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if (NextI == MergeMI)
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++NextI;
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NextI = next_nodbg(NextI, E);
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unsigned Opc = I->getOpcode();
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bool IsScaled = !TII->isUnscaledLdSt(Opc);
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@ -748,18 +748,17 @@ static bool forAllMIsUntilDef(MachineInstr &MI, MCPhysReg DefReg,
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const TargetRegisterInfo *TRI, unsigned Limit,
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std::function<bool(MachineInstr &, bool)> &Fn) {
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auto MBB = MI.getParent();
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for (MachineBasicBlock::reverse_iterator I = MI.getReverseIterator(),
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E = MBB->rend();
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I != E; I++) {
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for (MachineInstr &I :
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instructionsWithoutDebug(MI.getReverseIterator(), MBB->instr_rend())) {
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if (!Limit)
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return false;
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--Limit;
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bool isDef = any_of(I->operands(), [DefReg, TRI](MachineOperand &MOP) {
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bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) {
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return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
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TRI->regsOverlap(MOP.getReg(), DefReg);
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});
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if (!Fn(*I, isDef))
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if (!Fn(I, isDef))
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return false;
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if (isDef)
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break;
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@ -783,14 +782,14 @@ MachineBasicBlock::iterator
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AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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const LdStPairFlags &Flags) {
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MachineBasicBlock::iterator NextI = I;
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++NextI;
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator NextI = next_nodbg(I, E);
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// If NextI is the second of the two instructions to be merged, we need
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// to skip one further. Either way we merge will invalidate the iterator,
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// and we don't need to scan the new instruction, as it's a pairwise
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// instruction, which we're not considering for further action anyway.
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if (NextI == Paired)
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++NextI;
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NextI = next_nodbg(NextI, E);
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int SExtIdx = Flags.getSExtIdx();
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unsigned Opc =
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@ -1009,8 +1008,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator
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AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
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MachineBasicBlock::iterator StoreI) {
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MachineBasicBlock::iterator NextI = LoadI;
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++NextI;
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MachineBasicBlock::iterator NextI =
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next_nodbg(LoadI, LoadI->getParent()->end());
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int LoadSize = TII->getMemScale(*LoadI);
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int StoreSize = TII->getMemScale(*StoreI);
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@ -1188,7 +1187,7 @@ bool AArch64LoadStoreOpt::findMatchingStore(
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unsigned Count = 0;
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do {
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--MBBI;
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MBBI = prev_nodbg(MBBI, B);
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MachineInstr &MI = *MBBI;
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// Don't count transient instructions towards the search limit since there
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@ -1440,7 +1439,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator MBBI = I;
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MachineBasicBlock::iterator MBBIWithRenameReg;
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MachineInstr &FirstMI = *I;
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++MBBI;
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MBBI = next_nodbg(MBBI, E);
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bool MayLoad = FirstMI.mayLoad();
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bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
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@ -1468,7 +1467,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// Remember any instructions that read/write memory between FirstMI and MI.
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SmallVector<MachineInstr *, 4> MemInsns;
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for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
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for (unsigned Count = 0; MBBI != E && Count < Limit;
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MBBI = next_nodbg(MBBI, E)) {
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MachineInstr &MI = *MBBI;
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UsedInBetween.accumulate(MI);
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@ -1637,12 +1637,13 @@ AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
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assert((Update->getOpcode() == AArch64::ADDXri ||
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Update->getOpcode() == AArch64::SUBXri) &&
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"Unexpected base register update instruction to merge!");
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MachineBasicBlock::iterator NextI = I;
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator NextI = next_nodbg(I, E);
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// Return the instruction following the merged instruction, which is
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// the instruction following our unmerged load. Unless that's the add/sub
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// instruction we're merging, in which case it's the one after that.
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if (++NextI == Update)
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++NextI;
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if (NextI == Update)
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NextI = next_nodbg(NextI, E);
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int Value = Update->getOperand(2).getImm();
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assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
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@ -1780,7 +1781,7 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
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// insn (inclusive) and the second insn.
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ModifiedRegUnits.clear();
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UsedRegUnits.clear();
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++MBBI;
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MBBI = next_nodbg(MBBI, E);
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// We can't post-increment the stack pointer if any instruction between
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// the memory access (I) and the increment (MBBI) can access the memory
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@ -1796,7 +1797,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
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return E;
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}
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for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
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for (unsigned Count = 0; MBBI != E && Count < Limit;
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MBBI = next_nodbg(MBBI, E)) {
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MachineInstr &MI = *MBBI;
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// Don't count transient instructions towards the search limit since there
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@ -1854,7 +1856,7 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
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UsedRegUnits.clear();
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unsigned Count = 0;
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do {
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--MBBI;
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MBBI = prev_nodbg(MBBI, B);
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MachineInstr &MI = *MBBI;
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// Don't count transient instructions towards the search limit since there
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377
test/CodeGen/AArch64/ldst-opt-mte-with-dbg.mir
Normal file
377
test/CodeGen/AArch64/ldst-opt-mte-with-dbg.mir
Normal file
@ -0,0 +1,377 @@
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# Strip out debug info, then run ldst-opt with limit=1.
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# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -run-pass mir-strip-debug,aarch64-ldst-opt -mir-strip-debugify-only=0 -verify-machineinstrs -o - %s | FileCheck %s
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#
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# Run ldst-opt with limit=1, then strip out debug info.
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# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt,mir-strip-debug -mir-strip-debugify-only=0 -verify-machineinstrs -o - %s | FileCheck %s
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---
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### STG and its offset limits
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# CHECK-LABEL: name: test_STG_post
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# CHECK: STGPostIndex $x0, $x0, 7
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name: test_STG_post
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post_same_reg
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# CHECK: STGPostIndex $x1, $x0, 7
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name: test_STG_post_same_reg
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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STGOffset $x1, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post_unaligned
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# CHECK: STGOffset $x0, $x0, 0
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# CHECK-NEXT: ADDXri $x0, 8, 0
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name: test_STG_post_unaligned
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 8, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post2
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# CHECK: STGPostIndex $x0, $x0, -256
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name: test_STG_post2
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = SUBXri $x0, 4096, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post3
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# CHECK: STGOffset $x0, $x0, 0
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# CHECK-NEXT: SUBXri $x0, 4112, 0
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name: test_STG_post3
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = SUBXri $x0, 4112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post4
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# CHECK: STGPostIndex $x0, $x0, 255
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name: test_STG_post4
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 4080, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post5
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# CHECK: STGOffset $x0, $x0, 0
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# CHECK-NEXT: ADDXri $x0, 4096, 0
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name: test_STG_post5
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 4096, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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### The rest of ST*G variants.
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# CHECK-LABEL: name: test_STZG_post
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# CHECK: STZGPostIndex $x0, $x0, 7
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name: test_STZG_post
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body: |
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bb.0.entry:
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liveins: $x0
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STZGOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_ST2G_post
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# CHECK: ST2GPostIndex $x0, $x0, 7
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name: test_ST2G_post
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body: |
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bb.0.entry:
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liveins: $x0
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ST2GOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STZ2G_post
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# CHECK: STZ2GPostIndex $x0, $x0, 7
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name: test_STZ2G_post
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body: |
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bb.0.entry:
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liveins: $x0
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STZ2GOffset $x0, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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### STGP and its offset limits
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# CHECK-LABEL: name: test_STGP_post
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# CHECK: STGPpost $x1, $x2, $x0, 7
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name: test_STGP_post
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 112, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post2
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# CHECK: STGPpost $x1, $x2, $x0, -64
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name: test_STGP_post2
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = SUBXri $x0, 1024, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post3
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# CHECK: STGPi $x1, $x2, $x0, 0
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# CHECK-NEXT: SUBXri $x0, 1040, 0
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name: test_STGP_post3
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = SUBXri $x0, 1040, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post4
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# CHECK: STGPpost $x1, $x2, $x0, 63
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name: test_STGP_post4
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 1008, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post5
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# CHECK: STGPi $x1, $x2, $x0, 0
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# CHECK-NEXT: ADDXri $x0, 1024, 0
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name: test_STGP_post5
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 1024, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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### Pre-indexed forms
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# CHECK-LABEL: name: test_STG_pre
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# CHECK: STGPreIndex $x0, $x0, 10
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name: test_STG_pre
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 10
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 160, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_pre
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# CHECK: STGPpre $x1, $x2, $x0, 10
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name: test_STGP_pre
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 10
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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$x0 = ADDXri $x0, 160, 0
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DBG_VALUE $x0, 0
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DBG_VALUE $x0, 0
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||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
### Pre-indexed forms with add/sub coming before the store.
|
||||
|
||||
# CHECK-LABEL: name: test_STG_pre_back
|
||||
# CHECK: STGPreIndex $x0, $x0, 2
|
||||
name: test_STG_pre_back
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
$x0 = ADDXri $x0, 32, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
STGOffset $x0, $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: test_STGP_pre_back
|
||||
# CHECK: STGPpre $x1, $x2, $x0, -3
|
||||
name: test_STGP_pre_back
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0, $x1, $x2
|
||||
|
||||
$x0 = SUBXri $x0, 48, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
STGPi $x1, $x2, $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
### STGP with source register == address register
|
||||
|
||||
# CHECK-LABEL: name: test_STGP_post_same_reg
|
||||
# CHECK: STGPpost $x0, $x0, $x0, 7
|
||||
name: test_STGP_post_same_reg
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
STGPi $x0, $x0, $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
$x0 = ADDXri $x0, 112, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: test_STGP_pre_same_reg
|
||||
# CHECK: STGPpre $x0, $x0, $x0, 7
|
||||
name: test_STGP_pre_same_reg
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
STGPi $x0, $x0, $x0, 7
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
$x0 = ADDXri $x0, 112, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
# This case can not be merged because the source register is always read before writeback.
|
||||
# CHECK-LABEL: name: test_STGP_pre_back_same_reg
|
||||
# CHECK: SUBXri $x0, 48, 0
|
||||
# CHECK-NEXT: STGPi $x0, $x0, $x0, 0
|
||||
name: test_STGP_pre_back_same_reg
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
$x0 = SUBXri $x0, 48, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
STGPi $x0, $x0, $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
DBG_VALUE $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
|
||||
# RUN: llc -debugify-and-strip-all-safe -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
|
||||
---
|
||||
|
||||
### STG and its offset limits
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user