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[cleanup] Hoist an if-else chain on ISD opcodes (really designed for

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switches) into a switch, and sink them into a dispatch function that can
return the result rather than awkward variable setting with breaks.

llvm-svn: 212166
This commit is contained in:
Chandler Carruth 2014-07-02 06:23:34 +00:00
parent 0418802b47
commit d3bf1762bd
1 changed files with 28 additions and 17 deletions
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45
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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@ -59,6 +59,12 @@ class VectorLegalizer {
/// \brief Implements unrolling a VSETCC. /// \brief Implements unrolling a VSETCC.
SDValue UnrollVSETCC(SDValue Op); SDValue UnrollVSETCC(SDValue Op);
/// \brief Implement expand-based legalization of vector operations.
///
/// This is just a high-level routine to dispatch to specific code paths for
/// operations to legalize them.
SDValue Expand(SDValue Op);
/// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
/// FSUB isn't legal. /// FSUB isn't legal.
/// ///
@ -295,23 +301,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
// FALL THROUGH // FALL THROUGH
} }
case TargetLowering::Expand: case TargetLowering::Expand:
if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) Result = Expand(Op);
Result = ExpandSEXTINREG(Op);
else if (Node->getOpcode() == ISD::BSWAP)
Result = ExpandBSWAP(Op);
else if (Node->getOpcode() == ISD::VSELECT)
Result = ExpandVSELECT(Op);
else if (Node->getOpcode() == ISD::SELECT)
Result = ExpandSELECT(Op);
else if (Node->getOpcode() == ISD::UINT_TO_FP)
Result = ExpandUINT_TO_FLOAT(Op);
else if (Node->getOpcode() == ISD::FNEG)
Result = ExpandFNEG(Op);
else if (Node->getOpcode() == ISD::SETCC)
Result = UnrollVSETCC(Op);
else
Result = DAG.UnrollVectorOp(Op.getNode());
break;
} }
// Make sure that the generated code is itself legal. // Make sure that the generated code is itself legal.
@ -620,6 +610,27 @@ SDValue VectorLegalizer::ExpandStore(SDValue Op) {
return TF; return TF;
} }
SDValue VectorLegalizer::Expand(SDValue Op) {
switch (Op->getOpcode()) {
case ISD::SIGN_EXTEND_INREG:
return ExpandSEXTINREG(Op);
case ISD::BSWAP:
return ExpandBSWAP(Op);
case ISD::VSELECT:
return ExpandVSELECT(Op);
case ISD::SELECT:
return ExpandSELECT(Op);
case ISD::UINT_TO_FP:
return ExpandUINT_TO_FLOAT(Op);
case ISD::FNEG:
return ExpandFNEG(Op);
case ISD::SETCC:
return UnrollVSETCC(Op);
default:
return DAG.UnrollVectorOp(Op.getNode());
}
}
SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
// Lower a select instruction where the condition is a scalar and the // Lower a select instruction where the condition is a scalar and the
// operands are vectors. Lower this select to VSELECT and implement it // operands are vectors. Lower this select to VSELECT and implement it