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[AMDGPU] Regenerate some f16/i16 tests.
Prep work for D51589 llvm-svn: 356340
This commit is contained in:
Simon Pilgrim
parent
e9a00fefdc
commit
d3e664c5d8
@ -1,10 +1,52 @@
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VIPLUS %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=VIPLUS %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,VI
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; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,GFX9
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_imax_sge_i16:
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; VIPLUS: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
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; VI-LABEL: v_test_imax_sge_i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s7
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; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: flat_load_ushort v2, v[2:3]
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; VI-NEXT: flat_load_ushort v3, v[0:1]
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_max_i16_e32 v2, v3, v2
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; VI-NEXT: flat_store_short v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_test_imax_sge_i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; GFX9-NEXT: v_lshlrev_b32_e32 v4, 1, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v1, s7
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: v_mov_b32_e32 v3, s1
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; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
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; GFX9-NEXT: global_load_ushort v2, v[2:3], off
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; GFX9-NEXT: global_load_ushort v3, v[0:1], off
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; GFX9-NEXT: v_mov_b32_e32 v1, s5
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_max_i16_e32 v2, v3, v2
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; GFX9-NEXT: global_store_short v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
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@ -18,12 +60,52 @@ define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 addrs
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_imax_sge_v2i16:
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; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_max_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX9: v_pk_max_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_imax_sge_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
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; VI-LABEL: v_test_imax_sge_v2i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s7
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; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: flat_load_dword v2, v[2:3]
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; VI-NEXT: flat_load_dword v3, v[0:1]
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; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_max_i16_e32 v4, v3, v2
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; VI-NEXT: v_max_i16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: v_or_b32_e32 v2, v4, v2
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_test_imax_sge_v2i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v1, s7
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: v_mov_b32_e32 v3, s1
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; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
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; GFX9-NEXT: global_load_dword v2, v[2:3], off
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; GFX9-NEXT: global_load_dword v3, v[0:1], off
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; GFX9-NEXT: v_mov_b32_e32 v1, s5
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_pk_max_i16 v2, v3, v2
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
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@ -37,15 +119,69 @@ define amdgpu_kernel void @v_test_imax_sge_v2i16(<2 x i16> addrspace(1)* %out, <
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_imax_sge_v3i16:
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; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_max_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI-NOT: v_max_i16
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; GFX9: v_pk_max_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_pk_max_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind {
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; VI-LABEL: v_test_imax_sge_v3i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: v_lshlrev_b32_e32 v8, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v3, s7
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v8
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v8
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v0
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; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v6, vcc, 4, v2
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; VI-NEXT: flat_load_dword v9, v[0:1]
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; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
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; VI-NEXT: flat_load_ushort v4, v[4:5]
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; VI-NEXT: flat_load_dword v5, v[2:3]
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; VI-NEXT: flat_load_ushort v6, v[6:7]
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v8
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
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; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
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; VI-NEXT: v_max_i16_e32 v7, v5, v9
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; VI-NEXT: v_max_i16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_max_i16_e32 v4, v6, v4
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; VI-NEXT: v_or_b32_e32 v5, v7, v5
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; VI-NEXT: flat_store_dword v[0:1], v5
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; VI-NEXT: flat_store_short v[2:3], v4
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_test_imax_sge_v3i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v1, s7
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: v_mov_b32_e32 v3, s1
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; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
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; GFX9-NEXT: global_load_dword v6, v[2:3], off
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; GFX9-NEXT: global_load_dword v7, v[0:1], off
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; GFX9-NEXT: v_mov_b32_e32 v5, s5
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; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v8, v7
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; GFX9-NEXT: v_pk_max_i16 v7, v7, v6
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; GFX9-NEXT: global_load_short_d16 v6, v[2:3], off offset:4
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; GFX9-NEXT: global_load_short_d16 v8, v[0:1], off offset:4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_pk_max_i16 v0, v8, v6
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; GFX9-NEXT: global_store_dword v[4:5], v7, off
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; GFX9-NEXT: global_store_short v[4:5], v0, off offset:4
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; GFX9-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
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@ -59,15 +195,56 @@ define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_imax_sge_v4i16:
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; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_max_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_max_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX9: v_pk_max_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_pk_max_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_imax_sge_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %aptr, <4 x i16> addrspace(1)* %bptr) nounwind {
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; VI-LABEL: v_test_imax_sge_v4i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s7
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; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
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; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v5, s5
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; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
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; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_max_i16_e32 v6, v1, v3
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; VI-NEXT: v_max_i16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: v_max_i16_e32 v3, v0, v2
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; VI-NEXT: v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: v_or_b32_e32 v1, v6, v1
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; VI-NEXT: v_or_b32_e32 v0, v3, v0
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; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_test_imax_sge_v4i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off
|
||||
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
|
||||
; GFX9-NEXT: v_mov_b32_e32 v5, s5
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_pk_max_i16 v1, v1, v3
|
||||
; GFX9-NEXT: v_pk_max_i16 v0, v0, v2
|
||||
; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep0 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %bptr, i32 %tid
|
||||
@ -81,9 +258,50 @@ define amdgpu_kernel void @v_test_imax_sge_v4i16(<4 x i16> addrspace(1)* %out, <
|
||||
}
|
||||
|
||||
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
||||
; GCN-LABEL: {{^}}v_test_imax_sgt_i16:
|
||||
; VIPLUS: v_max_i16_e32
|
||||
define amdgpu_kernel void @v_test_imax_sgt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
||||
; VI-LABEL: v_test_imax_sgt_i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: v_mov_b32_e32 v3, s1
|
||||
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; VI-NEXT: flat_load_ushort v2, v[2:3]
|
||||
; VI-NEXT: flat_load_ushort v3, v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s5
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_max_i16_e32 v2, v3, v2
|
||||
; VI-NEXT: flat_store_short v[0:1], v2
|
||||
; VI-NEXT: s_endpgm
|
||||
;
|
||||
; GFX9-LABEL: v_test_imax_sgt_i16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; GFX9-NEXT: global_load_ushort v2, v[2:3], off
|
||||
; GFX9-NEXT: global_load_ushort v3, v[0:1], off
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_max_i16_e32 v2, v3, v2
|
||||
; GFX9-NEXT: global_store_short v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
||||
@ -97,9 +315,50 @@ define amdgpu_kernel void @v_test_imax_sgt_i16(i16 addrspace(1)* %out, i16 addrs
|
||||
}
|
||||
|
||||
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
||||
; GCN-LABEL: {{^}}v_test_umax_uge_i16:
|
||||
; VIPLUS: v_max_u16_e32
|
||||
define amdgpu_kernel void @v_test_umax_uge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
||||
; VI-LABEL: v_test_umax_uge_i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: v_mov_b32_e32 v3, s1
|
||||
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; VI-NEXT: flat_load_ushort v2, v[2:3]
|
||||
; VI-NEXT: flat_load_ushort v3, v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s5
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_max_u16_e32 v2, v3, v2
|
||||
; VI-NEXT: flat_store_short v[0:1], v2
|
||||
; VI-NEXT: s_endpgm
|
||||
;
|
||||
; GFX9-LABEL: v_test_umax_uge_i16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; GFX9-NEXT: global_load_ushort v2, v[2:3], off
|
||||
; GFX9-NEXT: global_load_ushort v3, v[0:1], off
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_max_u16_e32 v2, v3, v2
|
||||
; GFX9-NEXT: global_store_short v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
||||
@ -113,9 +372,50 @@ define amdgpu_kernel void @v_test_umax_uge_i16(i16 addrspace(1)* %out, i16 addrs
|
||||
}
|
||||
|
||||
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
||||
; GCN-LABEL: {{^}}v_test_umax_ugt_i16:
|
||||
; VIPLUS: v_max_u16_e32
|
||||
define amdgpu_kernel void @v_test_umax_ugt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
||||
; VI-LABEL: v_test_umax_ugt_i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: v_mov_b32_e32 v3, s1
|
||||
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; VI-NEXT: flat_load_ushort v2, v[2:3]
|
||||
; VI-NEXT: flat_load_ushort v3, v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s5
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_max_u16_e32 v2, v3, v2
|
||||
; VI-NEXT: flat_store_short v[0:1], v2
|
||||
; VI-NEXT: s_endpgm
|
||||
;
|
||||
; GFX9-LABEL: v_test_umax_ugt_i16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; GFX9-NEXT: global_load_ushort v2, v[2:3], off
|
||||
; GFX9-NEXT: global_load_ushort v3, v[0:1], off
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_max_u16_e32 v2, v3, v2
|
||||
; GFX9-NEXT: global_store_short v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
||||
@ -128,12 +428,52 @@ define amdgpu_kernel void @v_test_umax_ugt_i16(i16 addrspace(1)* %out, i16 addrs
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umax_ugt_v2i16:
|
||||
; VI: v_max_u16_e32
|
||||
; VI: v_max_u16_sdwa
|
||||
|
||||
; GFX9: v_pk_max_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
define amdgpu_kernel void @v_test_umax_ugt_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
|
||||
; VI-LABEL: v_test_umax_ugt_v2i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: v_mov_b32_e32 v3, s1
|
||||
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
||||
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; VI-NEXT: flat_load_dword v2, v[2:3]
|
||||
; VI-NEXT: flat_load_dword v3, v[0:1]
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s5
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_max_u16_e32 v4, v3, v2
|
||||
; VI-NEXT: v_max_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; VI-NEXT: v_or_b32_e32 v2, v4, v2
|
||||
; VI-NEXT: flat_store_dword v[0:1], v2
|
||||
; VI-NEXT: s_endpgm
|
||||
;
|
||||
; GFX9-LABEL: v_test_umax_ugt_v2i16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
||||
; GFX9-NEXT: global_load_dword v2, v[2:3], off
|
||||
; GFX9-NEXT: global_load_dword v3, v[0:1], off
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
|
||||
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_pk_max_u16 v2, v3, v2
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
|
||||
|
||||
@ -1,23 +1,78 @@
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
|
||||
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
|
||||
|
||||
; GCN-LABEL: {{^}}select_f16:
|
||||
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
|
||||
; SI-DAG: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
|
||||
; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
|
||||
; SI-DAG: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
|
||||
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
||||
; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
|
||||
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
|
||||
; GCN: buffer_store_short v[[R_F16]]
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_f16(
|
||||
; SI-LABEL: select_f16:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
|
||||
; SI-NEXT: s_mov_b32 s15, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s14, -1
|
||||
; SI-NEXT: s_mov_b32 s22, s14
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s10
|
||||
; SI-NEXT: s_mov_b32 s17, s11
|
||||
; SI-NEXT: s_mov_b32 s10, s14
|
||||
; SI-NEXT: s_mov_b32 s11, s15
|
||||
; SI-NEXT: s_mov_b32 s20, s6
|
||||
; SI-NEXT: s_mov_b32 s21, s7
|
||||
; SI-NEXT: s_mov_b32 s23, s15
|
||||
; SI-NEXT: s_mov_b32 s2, s14
|
||||
; SI-NEXT: s_mov_b32 s3, s15
|
||||
; SI-NEXT: s_mov_b32 s18, s14
|
||||
; SI-NEXT: s_mov_b32 s19, s15
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[20:23], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
|
||||
; SI-NEXT: buffer_load_ushort v2, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_ushort v3, off, s[0:3], 0
|
||||
; SI-NEXT: s_mov_b32 s12, s4
|
||||
; SI-NEXT: s_mov_b32 s13, s5
|
||||
; SI-NEXT: s_waitcnt vmcnt(3)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: buffer_store_short v0, off, s[12:15], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_f16:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
|
||||
; VI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s2, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s2
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s0, s4
|
||||
; VI-NEXT: s_mov_b32 s1, s5
|
||||
; VI-NEXT: s_mov_b32 s16, s10
|
||||
; VI-NEXT: s_mov_b32 s17, s11
|
||||
; VI-NEXT: s_mov_b32 s4, s6
|
||||
; VI-NEXT: s_mov_b32 s5, s7
|
||||
; VI-NEXT: s_mov_b32 s10, s2
|
||||
; VI-NEXT: s_mov_b32 s11, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s2
|
||||
; VI-NEXT: s_mov_b32 s7, s3
|
||||
; VI-NEXT: s_mov_b32 s15, s3
|
||||
; VI-NEXT: s_mov_b32 s18, s2
|
||||
; VI-NEXT: s_mov_b32 s19, s3
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
|
||||
; VI-NEXT: buffer_load_ushort v2, off, s[16:19], 0
|
||||
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
|
||||
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %a,
|
||||
half addrspace(1)* %b,
|
||||
@ -34,21 +89,67 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_f16_imm_a:
|
||||
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
|
||||
; SI-DAG: v_cmp_lt_f32_e32 vcc, 0.5, v[[B_F32]]
|
||||
; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
|
||||
; SI-DAG: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
|
||||
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
||||
; VI: v_cmp_lt_f16_e32 vcc, 0.5, v[[B_F16]]
|
||||
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
|
||||
; GCN: buffer_store_short v[[R_F16]]
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_f16_imm_a(
|
||||
; SI-LABEL: select_f16_imm_a:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0.5, v0
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_f16_imm_a:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %b,
|
||||
half addrspace(1)* %c,
|
||||
@ -63,22 +164,67 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_f16_imm_b:
|
||||
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
||||
; SI-DAG: v_cmp_gt_f32_e32 vcc, 0.5, v[[A_F32]]
|
||||
; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
|
||||
; SI-DAG: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
|
||||
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
||||
|
||||
; VI: v_cmp_gt_f16_e32 vcc, 0.5, v[[A_F16]]
|
||||
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
|
||||
; GCN: buffer_store_short v[[R_F16]]
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_f16_imm_b(
|
||||
; SI-LABEL: select_f16_imm_b:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0.5, v0
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_f16_imm_b:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %a,
|
||||
half addrspace(1)* %c,
|
||||
@ -93,23 +239,68 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_f16_imm_c:
|
||||
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
|
||||
; SI: v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
|
||||
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[D_F32]], vcc
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
||||
|
||||
; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x3800{{$}}
|
||||
; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
|
||||
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[C_F16]], v[[D_F16]], vcc
|
||||
; GCN: buffer_store_short v[[R_F16]]
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_f16_imm_c(
|
||||
; SI-LABEL: select_f16_imm_c:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_f16_imm_c:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
||||
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
||||
; VI-NEXT: s_waitcnt vmcnt(1)
|
||||
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
||||
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %a,
|
||||
half addrspace(1)* %b,
|
||||
@ -124,22 +315,68 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_f16_imm_d:
|
||||
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
|
||||
; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
|
||||
; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
|
||||
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[C_F32]]
|
||||
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
||||
; VI: v_mov_b32_e32 v[[D_F16:[0-9]+]], 0x3800{{$}}
|
||||
; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
|
||||
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
|
||||
; GCN: buffer_store_short v[[R_F16]]
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_f16_imm_d(
|
||||
; SI-LABEL: select_f16_imm_d:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_f16_imm_d:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
||||
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
||||
; VI-NEXT: s_waitcnt vmcnt(1)
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
||||
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %a,
|
||||
half addrspace(1)* %b,
|
||||
@ -154,25 +391,99 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_v2f16:
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cmp_lt_f32_e32
|
||||
; SI: v_cndmask_b32_e32
|
||||
; SI: v_cmp_lt_f32_e32
|
||||
; SI: v_cndmask_b32_e32
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
|
||||
; VI: v_cmp_lt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
; VI: v_cmp_lt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_v2f16(
|
||||
; SI-LABEL: select_v2f16:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
|
||||
; SI-NEXT: s_mov_b32 s15, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s14, -1
|
||||
; SI-NEXT: s_mov_b32 s22, s14
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s10
|
||||
; SI-NEXT: s_mov_b32 s17, s11
|
||||
; SI-NEXT: s_mov_b32 s10, s14
|
||||
; SI-NEXT: s_mov_b32 s11, s15
|
||||
; SI-NEXT: s_mov_b32 s20, s6
|
||||
; SI-NEXT: s_mov_b32 s21, s7
|
||||
; SI-NEXT: s_mov_b32 s23, s15
|
||||
; SI-NEXT: s_mov_b32 s2, s14
|
||||
; SI-NEXT: s_mov_b32 s3, s15
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[20:23], 0
|
||||
; SI-NEXT: s_mov_b32 s18, s14
|
||||
; SI-NEXT: s_mov_b32 s19, s15
|
||||
; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0
|
||||
; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0
|
||||
; SI-NEXT: buffer_load_dword v3, off, s[16:19], 0
|
||||
; SI-NEXT: s_mov_b32 s12, s4
|
||||
; SI-NEXT: s_mov_b32 s13, s5
|
||||
; SI-NEXT: s_waitcnt vmcnt(3)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v4, v2
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v5, v6
|
||||
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_v2f16:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
|
||||
; VI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s2, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s2
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s0, s4
|
||||
; VI-NEXT: s_mov_b32 s1, s5
|
||||
; VI-NEXT: s_mov_b32 s16, s10
|
||||
; VI-NEXT: s_mov_b32 s17, s11
|
||||
; VI-NEXT: s_mov_b32 s4, s6
|
||||
; VI-NEXT: s_mov_b32 s5, s7
|
||||
; VI-NEXT: s_mov_b32 s10, s2
|
||||
; VI-NEXT: s_mov_b32 s11, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s2
|
||||
; VI-NEXT: s_mov_b32 s7, s3
|
||||
; VI-NEXT: s_mov_b32 s15, s3
|
||||
; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
|
||||
; VI-NEXT: s_mov_b32 s18, s2
|
||||
; VI-NEXT: s_mov_b32 s19, s3
|
||||
; VI-NEXT: buffer_load_dword v1, off, s[8:11], 0
|
||||
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
||||
; VI-NEXT: buffer_load_dword v3, off, s[16:19], 0
|
||||
; VI-NEXT: s_waitcnt vmcnt(3)
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v6, v5
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
<2 x half> addrspace(1)* %r,
|
||||
<2 x half> addrspace(1)* %a,
|
||||
<2 x half> addrspace(1)* %b,
|
||||
@ -189,28 +500,87 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_v2f16_imm_a:
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
|
||||
; SI: v_cmp_lt_f32_e32
|
||||
; SI: v_cndmask_b32_e32
|
||||
; SI: v_cmp_lt_f32_e32 vcc, 0.5
|
||||
; SI: v_cndmask_b32_e32
|
||||
|
||||
; VI: v_cmp_lt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
; VI: v_cmp_lt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_v2f16_imm_a(
|
||||
; SI-LABEL: select_v2f16_imm_a:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
||||
; SI-NEXT: s_mov_b32 s2, 0x3f200000
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
|
||||
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0.5, v0
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_v2f16_imm_a:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
||||
; VI-NEXT: s_movk_i32 s0, 0x3900
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, s0, v3
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
<2 x half> addrspace(1)* %r,
|
||||
<2 x half> addrspace(1)* %b,
|
||||
<2 x half> addrspace(1)* %c,
|
||||
@ -225,28 +595,87 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_v2f16_imm_b:
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
|
||||
; SI: v_cmp_gt_f32_e32
|
||||
; SI: v_cndmask_b32_e32
|
||||
; SI: v_cmp_gt_f32_e32 vcc, 0.5
|
||||
; SI: v_cndmask_b32_e32
|
||||
|
||||
; VI: v_cmp_gt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
; VI: v_cmp_gt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_v2f16_imm_b(
|
||||
; SI-LABEL: select_v2f16_imm_b:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
||||
; SI-NEXT: s_mov_b32 s2, 0x3f200000
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
|
||||
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
|
||||
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0.5, v0
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_v2f16_imm_b:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
||||
; VI-NEXT: s_movk_i32 s0, 0x3900
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
||||
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
||||
; VI-NEXT: v_cmp_gt_f16_e32 vcc, s0, v3
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
<2 x half> addrspace(1)* %r,
|
||||
<2 x half> addrspace(1)* %a,
|
||||
<2 x half> addrspace(1)* %c,
|
||||
@ -261,29 +690,89 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_v2f16_imm_c:
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
|
||||
; SI: v_cmp_nlt_f32_e32
|
||||
; SI: v_cndmask_b32_e32
|
||||
; SI: v_cmp_nlt_f32_e32
|
||||
; SI-DAG: v_cndmask_b32_e32
|
||||
|
||||
; VI: v_cmp_nlt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
|
||||
; VI: v_cmp_nlt_f16_e32
|
||||
; VI: v_cndmask_b32_e32
|
||||
|
||||
; SI-DAG: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_v2f16_imm_c(
|
||||
; SI-LABEL: select_v2f16_imm_c:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: buffer_load_dword v3, off, s[4:7], 0
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
||||
; SI-NEXT: v_mov_b32_e32 v2, 0x3f200000
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v5
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
|
||||
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v4, v3
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, 0.5, v1, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
||||
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_v2f16_imm_c:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_dword v4, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
||||
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
||||
; VI-NEXT: v_mov_b32_e32 v3, 0x3900
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(1)
|
||||
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v4
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v6, v5
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
<2 x half> addrspace(1)* %r,
|
||||
<2 x half> addrspace(1)* %a,
|
||||
<2 x half> addrspace(1)* %b,
|
||||
@ -298,28 +787,89 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}select_v2f16_imm_d:
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
; SI: v_cvt_f32_f16_e32
|
||||
|
||||
; SI: v_cmp_lt_f32_e32
|
||||
; SI: v_cndmask_b32
|
||||
; SI: v_cmp_lt_f32_e32
|
||||
; SI: v_cndmask_b32
|
||||
|
||||
; VI: v_cmp_lt_f16_e32
|
||||
; VI: v_cndmask_b32
|
||||
; VI: v_cmp_lt_f16_e32
|
||||
; VI: v_cndmask_b32
|
||||
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @select_v2f16_imm_d(
|
||||
; SI-LABEL: select_v2f16_imm_d:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s18, s10
|
||||
; SI-NEXT: s_mov_b32 s19, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: s_mov_b32 s16, s2
|
||||
; SI-NEXT: s_mov_b32 s17, s3
|
||||
; SI-NEXT: buffer_load_dword v3, off, s[4:7], 0
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
||||
; SI-NEXT: v_mov_b32_e32 v2, 0x3f200000
|
||||
; SI-NEXT: s_mov_b32 s8, s0
|
||||
; SI-NEXT: s_mov_b32 s9, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5
|
||||
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
|
||||
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v1, vcc
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_v2f16_imm_d:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s10
|
||||
; VI-NEXT: s_mov_b32 s15, s11
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s8, s0
|
||||
; VI-NEXT: s_mov_b32 s9, s1
|
||||
; VI-NEXT: s_mov_b32 s12, s6
|
||||
; VI-NEXT: s_mov_b32 s13, s7
|
||||
; VI-NEXT: s_mov_b32 s0, s2
|
||||
; VI-NEXT: s_mov_b32 s1, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s10
|
||||
; VI-NEXT: s_mov_b32 s7, s11
|
||||
; VI-NEXT: s_mov_b32 s2, s10
|
||||
; VI-NEXT: s_mov_b32 s3, s11
|
||||
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
||||
; VI-NEXT: buffer_load_dword v4, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
||||
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
||||
; VI-NEXT: v_mov_b32_e32 v3, 0x3900
|
||||
; VI-NEXT: s_waitcnt vmcnt(2)
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(1)
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v4
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v6, v5
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
<2 x half> addrspace(1)* %r,
|
||||
<2 x half> addrspace(1)* %a,
|
||||
<2 x half> addrspace(1)* %b,
|
||||
|
||||
@ -1,13 +1,55 @@
|
||||
; RUN: llc -march=amdgcn -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=amdgcn-- -mattr=-fp64-fp16-denormals -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
|
||||
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
|
||||
|
||||
; GCN-LABEL: {{^}}madak_f16
|
||||
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
|
||||
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
|
||||
; VI: v_madak_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], 0x4900{{$}}
|
||||
; VI: buffer_store_short v[[R_F16]]
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @madak_f16(
|
||||
; SI-LABEL: madak_f16:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s2, s10
|
||||
; SI-NEXT: s_mov_b32 s3, s11
|
||||
; SI-NEXT: s_mov_b32 s14, s10
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[0:3], 0
|
||||
; SI-NEXT: s_mov_b32 s8, s4
|
||||
; SI-NEXT: s_mov_b32 s9, s5
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: v_madak_f32 v0, v0, v1, 0x41200000
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: madak_f16:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
||||
; VI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s2, -1
|
||||
; VI-NEXT: s_mov_b32 s10, s2
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s0, s4
|
||||
; VI-NEXT: s_mov_b32 s1, s5
|
||||
; VI-NEXT: s_mov_b32 s4, s6
|
||||
; VI-NEXT: s_mov_b32 s5, s7
|
||||
; VI-NEXT: s_mov_b32 s11, s3
|
||||
; VI-NEXT: s_mov_b32 s6, s2
|
||||
; VI-NEXT: s_mov_b32 s7, s3
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_madak_f16 v0, v0, v1, 0x4900
|
||||
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r,
|
||||
half addrspace(1)* %a,
|
||||
half addrspace(1)* %b) {
|
||||
@ -22,13 +64,74 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}madak_f16_use_2
|
||||
; SI: v_madak_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 0x41200000
|
||||
; SI: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; VI: v_madak_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 0x4900
|
||||
; VI: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @madak_f16_use_2(
|
||||
; SI-LABEL: madak_f16_use_2:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
|
||||
; SI-NEXT: s_mov_b32 s15, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s14, -1
|
||||
; SI-NEXT: s_mov_b32 s2, s14
|
||||
; SI-NEXT: s_mov_b32 s3, s15
|
||||
; SI-NEXT: s_mov_b32 s18, s14
|
||||
; SI-NEXT: s_mov_b32 s19, s15
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s10
|
||||
; SI-NEXT: s_mov_b32 s17, s11
|
||||
; SI-NEXT: s_mov_b32 s10, s14
|
||||
; SI-NEXT: s_mov_b32 s11, s15
|
||||
; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
|
||||
; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
|
||||
; SI-NEXT: buffer_load_ushort v2, off, s[0:3], 0
|
||||
; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
|
||||
; SI-NEXT: s_mov_b32 s12, s6
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s6, s14
|
||||
; SI-NEXT: s_mov_b32 s7, s15
|
||||
; SI-NEXT: s_waitcnt vmcnt(2)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
||||
; SI-NEXT: s_waitcnt vmcnt(1)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
||||
; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
|
||||
; SI-NEXT: v_mac_f32_e32 v3, v0, v2
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
|
||||
; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
|
||||
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_store_short v1, off, s[12:15], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: madak_f16_use_2:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
|
||||
; VI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s2, -1
|
||||
; VI-NEXT: s_mov_b32 s14, s2
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mov_b32 s16, s10
|
||||
; VI-NEXT: s_mov_b32 s17, s11
|
||||
; VI-NEXT: s_mov_b32 s15, s3
|
||||
; VI-NEXT: s_mov_b32 s18, s2
|
||||
; VI-NEXT: s_mov_b32 s19, s3
|
||||
; VI-NEXT: s_mov_b32 s10, s2
|
||||
; VI-NEXT: s_mov_b32 s11, s3
|
||||
; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
|
||||
; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
|
||||
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
||||
; VI-NEXT: v_mov_b32_e32 v2, 0x4900
|
||||
; VI-NEXT: s_mov_b32 s0, s6
|
||||
; VI-NEXT: s_mov_b32 s1, s7
|
||||
; VI-NEXT: s_mov_b32 s6, s2
|
||||
; VI-NEXT: s_mov_b32 s7, s3
|
||||
; VI-NEXT: s_waitcnt vmcnt(1)
|
||||
; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: v_mac_f16_e32 v2, v0, v3
|
||||
; VI-NEXT: buffer_store_short v1, off, s[4:7], 0
|
||||
; VI-NEXT: buffer_store_short v2, off, s[0:3], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
half addrspace(1)* %r0,
|
||||
half addrspace(1)* %r1,
|
||||
half addrspace(1)* %a,
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user