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[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions

Browse Source 
Differential Revision: http://reviews.llvm.org/D14010

llvm-svn: 253041
This commit is contained in:
Zlatko Buljan 2015-11-13 13:14:25 +00:00
parent 2ba97c3d3b
commit d3e8d95829
11 changed files with 189 additions and 25 deletions
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26
lib/Target/Mips/MicroMipsDSPInstrFormats.td
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@ -102,3 +102,29 @@ class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
let Inst{10} = 0b0;
let Inst{9-0} = op;
}
class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
bits<5> rt;
bits<5> rs;
bits<4> sa;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-12} = sa;
let Inst{11} = 0b0;
let Inst{10-0} = op;
}
class POOL32A_2RSA4OP6_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
bits<5> rt;
bits<5> rs;
bits<4> sa;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-12} = sa;
let Inst{11-6} = op;
let Inst{5-0} = 0b111100;
}

49
lib/Target/Mips/MicroMipsDSPInstrInfo.td
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@ -55,6 +55,18 @@ class SHLLV_S_W_MM_ENC : POOL32A_3RB0_FMT<"shllv_s.w", 0b1111010101>;
class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>;
class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>;
class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>;
class SHRA_PH_MM_ENC : POOL32A_2RSA4B0_FMT<"shra.ph", 0b01100110101>;
class SHRA_R_PH_MM_ENC : POOL32A_2RSA4B0_FMT<"shra_r.ph", 0b11100110101>;
class SHRAV_PH_MM_ENC : POOL32A_3R_FMT<"shrav.ph", 0b00110001101>;
class SHRAV_R_PH_MM_ENC : POOL32A_3R_FMT<"shrav_r.ph", 0b10110001101>;
class SHRAV_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav.qb", 0b00111001101>;
class SHRAV_R_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav_r.qb", 0b10111001101>;
class SHRAV_R_W_MM_ENC : POOL32A_3RB0_FMT<"shrav_r.w", 0b1011010101>;
class SHRA_R_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shra_r.w", 0b1011110101>;
class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>;
class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>;
class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>;
class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>;
// Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@ -99,6 +111,16 @@ class SHRA_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
"shra.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>;
class SHRA_R_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
"shra_r.qb", int_mips_shra_r_qb, immZExt3, NoItinerary, DSPROpnd, uimm3>;
class SHRA_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
"shra.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>;
class SHRA_R_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
"shra_r.ph", int_mips_shra_r_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>;
class SHRA_R_W_MM_DESC : SHLL_R2_MM_DESC_BASE<
"shra_r.w", int_mips_shra_r_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>;
class SHRL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE<
"shrl.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>;
class SHRL_PH_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
"shrl.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>;
class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand RO> {
@ -117,6 +139,20 @@ class SHLLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
"shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
class SHLLV_S_W_MM_DESC : SHLLV_R3_MM_DESC_BASE<
"shllv_s.w", int_mips_shll_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag22]>;
class SHRAV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
"shrav.ph", int_mips_shra_ph, NoItinerary, DSPROpnd>;
class SHRAV_R_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
"shrav_r.ph", int_mips_shra_r_ph, NoItinerary, DSPROpnd>;
class SHRAV_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
"shrav.qb", int_mips_shra_qb, NoItinerary, DSPROpnd>;
class SHRAV_R_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
"shrav_r.qb", int_mips_shra_r_qb, NoItinerary, DSPROpnd>;
class SHRAV_R_W_MM_DESC : SHLLV_R3_MM_DESC_BASE<
"shrav_r.w", int_mips_shra_r_w, NoItinerary, GPR32Opnd>;
class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
"shrlv.ph", int_mips_shrl_ph, NoItinerary, DSPROpnd>;
class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
"shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>;
// Instruction defs.
// microMIPS DSP Rev 1
@ -148,6 +184,14 @@ def SHLLV_S_PH_MM : DspMMRel, SHLLV_S_PH_MM_ENC, SHLLV_S_PH_MM_DESC;
def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC;
def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC;
def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC;
def SHRA_PH_MM : DspMMRel, SHRA_PH_MM_ENC, SHRA_PH_MM_DESC;
def SHRA_R_PH_MM : DspMMRel, SHRA_R_PH_MM_ENC, SHRA_R_PH_MM_DESC;
def SHRAV_PH_MM : DspMMRel, SHRAV_PH_MM_ENC, SHRAV_PH_MM_DESC;
def SHRAV_R_PH_MM : DspMMRel, SHRAV_R_PH_MM_ENC, SHRAV_R_PH_MM_DESC;
def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC;
def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC;
def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC;
def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC;
// microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2;
@ -168,3 +212,8 @@ def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2;
def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
ISA_DSPR2;
def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2;
def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC,
ISA_DSPR2;
def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2;
def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2;

55
lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -340,9 +340,9 @@ class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
SDPatternOperator ImmPat, InstrItinClass itin,
RegisterOperand RO> {
RegisterOperand RO, Operand ImmOpnd> {
dag OutOperandList = (outs RO:$rd);
dag InOperandList = (ins RO:$rt, uimm16:$rs_sa);
dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
InstrItinClass Itinerary = itin;
@ -649,7 +649,7 @@ class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
// Shift
class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
NoItinerary, DSPROpnd>,
NoItinerary, DSPROpnd, uimm3>,
Defs<[DSPOutFlag22]>;
class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
@ -657,13 +657,13 @@ class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
Defs<[DSPOutFlag22]>;
class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
NoItinerary, DSPROpnd>;
NoItinerary, DSPROpnd, uimm3>;
class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
NoItinerary, DSPROpnd>;
class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
NoItinerary, DSPROpnd>,
NoItinerary, DSPROpnd, uimm4>,
Defs<[DSPOutFlag22]>;
class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
@ -671,7 +671,8 @@ class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
Defs<[DSPOutFlag22]>;
class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
immZExt4, NoItinerary, DSPROpnd>,
immZExt4, NoItinerary, DSPROpnd,
uimm4>,
Defs<[DSPOutFlag22]>;
class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
@ -679,19 +680,21 @@ class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
Defs<[DSPOutFlag22]>;
class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
NoItinerary, DSPROpnd>;
NoItinerary, DSPROpnd, uimm4>;
class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
NoItinerary, DSPROpnd>;
class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
immZExt4, NoItinerary, DSPROpnd>;
immZExt4, NoItinerary, DSPROpnd,
uimm4>;
class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
NoItinerary, DSPROpnd>;
class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
immZExt5, NoItinerary, GPR32Opnd>,
immZExt5, NoItinerary, GPR32Opnd,
uimm5>,
Defs<[DSPOutFlag22]>;
class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
@ -699,7 +702,8 @@ class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
Defs<[DSPOutFlag22]>;
class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
immZExt5, NoItinerary, GPR32Opnd>;
immZExt5, NoItinerary, GPR32Opnd,
uimm5>;
class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
NoItinerary, GPR32Opnd>;
@ -1049,19 +1053,20 @@ class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
// Shift
class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
NoItinerary, DSPROpnd>;
NoItinerary, DSPROpnd, uimm3>;
class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
NoItinerary, DSPROpnd>;
class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
immZExt3, NoItinerary, DSPROpnd>;
immZExt3, NoItinerary, DSPROpnd,
uimm3>;
class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
NoItinerary, DSPROpnd>;
class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
NoItinerary, DSPROpnd>;
NoItinerary, DSPROpnd, uimm4>;
class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
NoItinerary, DSPROpnd>;
@ -1114,20 +1119,20 @@ def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
@ -1237,11 +1242,11 @@ def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
def APPEND : APPEND_ENC, APPEND_DESC;
def BALIGN : BALIGN_ENC, BALIGN_DESC;
def PREPEND : PREPEND_ENC, PREPEND_DESC;

8
test/MC/Disassembler/Mips/micromips-dsp/valid.txt
View File

@ -28,3 +28,11 @@
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
0x00 0x64 0x53 0x35 # CHECK: shra.ph $3, $4, 5
0x00 0x64 0x57 0x35 # CHECK: shra_r.ph $3, $4, 5
0x00 0x85 0x19 0x8d # CHECK: shrav.ph $3, $4, $5
0x00 0x85 0x1d 0x8d # CHECK: shrav_r.ph $3, $4, $5
0x00 0x85 0x1a 0xd5 # CHECK: shrav_r.w $3, $4, $5
0x00 0x64 0x2a 0xf5 # CHECK: shra_r.w $3, $4, 5
0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5
0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5

4
test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
View File

@ -15,3 +15,7 @@
0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1
0x00 0x64 0xa1 0xfc # CHECK: shra.qb $3, $4, 5
0x00 0x64 0xb1 0xfc # CHECK: shra_r.qb $3, $4, 5
0x00 0x85 0x19 0xcd # CHECK: shrav.qb $3, $4, $5
0x00 0x85 0x1d 0xcd # CHECK: shrav_r.qb $3, $4, $5
0x00 0x64 0x53 0xfc # CHECK: shrl.ph $3, $4, 5
0x00 0x85 0x1b 0x15 # CHECK: shrlv.ph $3, $4, $5

21
test/MC/Mips/dsp/invalid.s Normal file
View File

@ -0,0 +1,21 @@
# RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dsp 2>%t1
# RUN: FileCheck %s < %t1
shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
// FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
// FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate

9
test/MC/Mips/dspr2/invalid.s Normal file
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@ -0,0 +1,9 @@
# RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dspr2 2>%t1
# RUN: FileCheck %s < %t1
shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate

21
test/MC/Mips/micromips-dsp/invalid.s Normal file
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@ -0,0 +1,21 @@
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp 2>%t1
# RUN: FileCheck %s < %t1
shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
// FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
// FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate

8
test/MC/Mips/micromips-dsp/valid.s
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@ -29,3 +29,11 @@
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
shra.ph $3, $4, 5 # CHECK: shra.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0x35]
shra_r.ph $3, $4, 5 # CHECK: shra_r.ph $3, $4, 5 # encoding: [0x00,0x64,0x57,0x35]
shrav.ph $3, $4, $5 # CHECK: shrav.ph $3, $4, $5 # encoding: [0x00,0x85,0x19,0x8d]
shrav_r.ph $3, $4, $5 # CHECK: shrav_r.ph $3, $4, $5 # encoding: [0x00,0x85,0x1d,0x8d]
shrav_r.w $3, $4, $5 # CHECK: shrav_r.w $3, $4, $5 # encoding: [0x00,0x85,0x1a,0xd5]
shra_r.w $3, $4, 5 # CHECK: shra_r.w $3, $4, 5 # encoding: [0x00,0x64,0x2a,0xf5]
shrl.qb $3, $4, 5 # CHECK: shrl.qb $3, $4, 5 # encoding: [0x00,0x64,0xb8,0x7c]
shrlv.qb $3, $4, $5 # CHECK: shrlv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x55]

9
test/MC/Mips/micromips-dspr2/invalid.s Normal file
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@ -0,0 +1,9 @@
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1
# RUN: FileCheck %s < %t1
shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate

4
test/MC/Mips/micromips-dspr2/valid.s
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@ -16,3 +16,7 @@
dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc]
shra.qb $3, $4, 5 # CHECK: shra.qb $3, $4, 5 # encoding: [0x00,0x64,0xa1,0xfc]
shra_r.qb $3, $4, 5 # CHECK: shra_r.qb $3, $4, 5 # encoding: [0x00,0x64,0xb1,0xfc]
shrav.qb $3, $4, $5 # CHECK: shrav.qb $3, $4, $5 # encoding: [0x00,0x85,0x19,0xcd]
shrav_r.qb $3, $4, $5 # CHECK: shrav_r.qb $3, $4, $5 # encoding: [0x00,0x85,0x1d,0xcd]
shrl.ph $3, $4, 5 # CHECK: shrl.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xfc]
shrlv.ph $3, $4, $5 # CHECK: shrlv.ph $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x15]