R600/SI: Fix verifier error from a branch on IMPLICIT_DEF

SIILowerI1Copies wasn't correctly handling this case.

llvm-svn: 222020

lib/Target/R600/SILowerI1Copies.cpp

@@ -109,6 +109,14 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
         continue;
       }
 
+      if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
+        unsigned Reg = MI.getOperand(0).getReg();
+        const TargetRegisterClass *RC = MRI.getRegClass(Reg);
+        if (RC == &AMDGPU::VReg_1RegClass)
+          MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
+        continue;
+      }
+
       if (MI.getOpcode() != AMDGPU::COPY ||
           !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
           !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))

test/CodeGen/R600/i1-copy-implicit-def.ll

@@ -0,0 +1,21 @@
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+
+; SILowerI1Copies was not handling IMPLICIT_DEF
+; SI-LABEL: @br_implicit_def
+; SI: BB#0:
+; SI-NEXT: s_and_saveexec_b64
+; SI-NEXT: s_xor_b64
+; SI-NEXT: BB#1:
+define void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 {
+bb:
+  br i1 undef, label %bb1, label %bb2
+
+bb1:
+  store volatile i32 123, i32 addrspace(1)* %out
+  ret void
+
+bb2:
+  ret void
+}
+
+attributes #0 = { nounwind }

test/CodeGen/R600/v-cmp-vreg1-src-error.ll

@@ -1,22 +0,0 @@
-; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s
-
-define void @init_data_cost_reduce_0(i32 %arg) #0 {
-bb:
-  br i1 undef, label %bb1, label %bb2
-
-bb1:                                              ; preds = %bb
-  br label %bb2
-
-bb2:                                              ; preds = %bb1, %bb
-  br i1 undef, label %bb3, label %bb4
-
-bb3:                                              ; preds = %bb2
-  %tmp = mul i32 undef, %arg
-  br label %bb4
-
-bb4:                                              ; preds = %bb3, %bb2
-  unreachable
-}
-
-attributes #0 = { nounwind }