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[FPEnv] Default NoFPExcept SDNodeFlag to false
The NoFPExcept bit in SDNodeFlags currently defaults to true, unlike all other such flags. This is a problem, because it implies that all code that transforms SDNodes without copying flags can introduce a correctness bug, not just a missed optimization. This patch changes the default to false. This makes it necessary to move setting the (No)FPExcept flag for constrained intrinsics from the visitConstrainedIntrinsic routine to the generic visit routine at the place where the other flags are set, or else the intersectFlagsWith call would erase the NoFPExcept flag again. In order to avoid making non-strict FP code worse, whenever SelectionDAGISel::SelectCodeCommon matches on a set of orignal nodes none of which can raise FP exceptions, it will preserve this property on all results nodes generated, by setting the NoFPExcept flag on those result nodes that would otherwise be considered as raising an FP exception. To check whether or not an SD node should be considered as raising an FP exception, the following logic applies: - For machine nodes, check the mayRaiseFPException property of the underlying MI instruction - For regular nodes, check isStrictFPOpcode - For target nodes, check a newly introduced isTargetStrictFPOpcode The latter is implemented by reserving a range of target opcodes, similarly to how memory opcodes are identified. (Note that there a bit of a quirk in identifying target nodes that are both memory nodes and strict FP nodes. To simplify the logic, right now all target memory nodes are automatically also considered strict FP nodes -- this could be fixed by adding one more range.) Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D71841
This commit is contained in:
Ulrich Weigand
parent
d4f51b5c4f
commit
d43411f026
@ -937,11 +937,16 @@ namespace ISD {
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BUILTIN_OP_END
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};
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/// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
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/// which cannot raise FP exceptions should be less than this value.
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/// Those that do must not be less than this value.
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static const int FIRST_TARGET_STRICTFP_OPCODE = BUILTIN_OP_END+400;
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/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
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/// which do not reference a specific memory location should be less than
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/// this value. Those that do must not be less than this value, and can
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/// be used with SelectionDAG::getMemIntrinsicNode.
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static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400;
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static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+500;
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//===--------------------------------------------------------------------===//
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/// MemIndexedMode enum - This enum defines the load / store indexed
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@ -310,6 +310,9 @@ public:
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return false;
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}
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/// Return whether the node may raise an FP exception.
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bool mayRaiseFPException(SDNode *Node) const;
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bool isOrEquivalentToAdd(const SDNode *N) const;
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private:
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@ -387,7 +387,7 @@ public:
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Exact(false), NoNaNs(false), NoInfs(false),
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NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
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AllowContract(false), ApproximateFuncs(false),
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AllowReassociation(false), NoFPExcept(true) {}
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AllowReassociation(false), NoFPExcept(false) {}
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/// Propagate the fast-math-flags from an IR FPMathOperator.
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void copyFMF(const FPMathOperator &FPMO) {
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@ -450,9 +450,9 @@ public:
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setDefined();
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AllowReassociation = b;
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}
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void setFPExcept(bool b) {
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void setNoFPExcept(bool b) {
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setDefined();
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NoFPExcept = !b;
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NoFPExcept = b;
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}
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// These are accessors for each flag.
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@ -467,7 +467,7 @@ public:
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bool hasAllowContract() const { return AllowContract; }
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bool hasApproximateFuncs() const { return ApproximateFuncs; }
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bool hasAllowReassociation() const { return AllowReassociation; }
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bool hasFPExcept() const { return !NoFPExcept; }
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bool hasNoFPExcept() const { return NoFPExcept; }
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bool isFast() const {
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return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
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@ -666,6 +666,15 @@ public:
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/// \<target\>ISD namespace).
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bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
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/// Test if this node has a target-specific opcode that may raise
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/// FP exceptions (in the \<target\>ISD namespace and greater than
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/// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
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/// opcode are currently automatically considered to possibly raise
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/// FP exceptions as well.
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bool isTargetStrictFPOpcode() const {
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return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
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}
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/// Test if this node has a target-specific
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/// memory-referencing opcode (in the \<target\>ISD namespace and
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/// greater than FIRST_TARGET_MEMORY_OPCODE).
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@ -882,7 +882,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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if (Flags.hasExact())
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MI->setFlag(MachineInstr::MIFlag::IsExact);
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if (Flags.hasFPExcept())
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if (MI->getDesc().mayRaiseFPException() && !Flags.hasNoFPExcept())
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MI->setFlag(MachineInstr::MIFlag::FPExcept);
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}
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@ -1108,6 +1108,15 @@ void SelectionDAGBuilder::visit(const Instruction &I) {
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Node->intersectFlagsWith(IncomingFlags);
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}
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}
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// Constrained FP intrinsics with fpexcept.ignore should also get
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// the NoFPExcept flag.
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if (auto *FPI = dyn_cast<ConstrainedFPIntrinsic>(&I))
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if (FPI->getExceptionBehavior() == fp::ExceptionBehavior::ebIgnore)
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if (SDNode *Node = getNodeForIRValue(&I)) {
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SDNodeFlags Flags = Node->getFlags();
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Flags.setNoFPExcept(true);
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Node->setFlags(Flags);
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}
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if (!I.isTerminator() && !HasTailCall &&
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!isStatepoint(&I)) // statepoints handle their exports internally
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@ -6972,12 +6981,6 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
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SDVTList VTs = DAG.getVTList(ValueVTs);
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SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers);
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if (FPI.getExceptionBehavior() != fp::ExceptionBehavior::ebIgnore) {
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SDNodeFlags Flags;
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Flags.setFPExcept(true);
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Result->setFlags(Flags);
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}
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assert(Result.getNode()->getNumValues() == 2);
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// See above -- chain is handled like for loads here.
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SDValue OutChain = Result.getValue(1);
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@ -547,8 +547,8 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
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if (getFlags().hasVectorReduction())
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OS << " vector-reduction";
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if (getFlags().hasFPExcept())
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OS << " fpexcept";
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if (getFlags().hasNoFPExcept())
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OS << " nofpexcept";
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if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(this)) {
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if (!MN->memoperands_empty()) {
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@ -3458,6 +3458,17 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
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if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
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Ops.push_back(InputGlue);
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// Check whether any matched node could raise an FP exception. Since all
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// such nodes must have a chain, it suffices to check ChainNodesMatched.
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// We need to perform this check before potentially modifying one of the
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// nodes via MorphNode.
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bool MayRaiseFPException = false;
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for (auto *N : ChainNodesMatched)
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if (mayRaiseFPException(N) && !N->getFlags().hasNoFPExcept()) {
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MayRaiseFPException = true;
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break;
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}
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// Create the node.
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MachineSDNode *Res = nullptr;
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bool IsMorphNodeTo = Opcode == OPC_MorphNodeTo ||
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@ -3489,6 +3500,14 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
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Ops, EmitNodeInfo));
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}
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// Set the NoFPExcept flag when no original matched node could
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// raise an FP exception, but the new node potentially might.
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if (!MayRaiseFPException && mayRaiseFPException(Res)) {
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SDNodeFlags Flags = Res->getFlags();
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Flags.setNoFPExcept(true);
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Res->setFlags(Flags);
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}
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// If the node had chain/glue results, update our notion of the current
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// chain and glue.
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if (EmitNodeInfo & OPFL_GlueOutput) {
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@ -3644,6 +3663,21 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
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}
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}
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/// Return whether the node may raise an FP exception.
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bool SelectionDAGISel::mayRaiseFPException(SDNode *N) const {
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// For machine opcodes, consult the MCID flag.
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if (N->isMachineOpcode()) {
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const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
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return MCID.mayRaiseFPException();
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}
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// For ISD opcodes, only StrictFP opcodes may raise an FP
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// exception.
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if (N->isTargetOpcode())
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return N->isTargetStrictFPOpcode();
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return N->isStrictFPOpcode();
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}
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bool SelectionDAGISel::isOrEquivalentToAdd(const SDNode *N) const {
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assert(N->getOpcode() == ISD::OR && "Unexpected opcode");
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auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
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@ -6190,8 +6190,10 @@ bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result,
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// incoming STRICT_UINT_TO_FP node; the STRICT_FADD node can
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// never raise any exception.
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SDNodeFlags Flags;
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Flags.setFPExcept(Node->getFlags().hasFPExcept());
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Flags.setNoFPExcept(Node->getFlags().hasNoFPExcept());
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Fast->setFlags(Flags);
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Flags.setNoFPExcept(true);
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Slow->setFlags(Flags);
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} else {
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SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Or);
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Slow = DAG.getNode(ISD::FADD, dl, DstVT, SignCvt, SignCvt);
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@ -58,8 +58,7 @@ enum NodeType : unsigned {
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ICMP,
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// Floating-point comparisons. The two operands are the values to compare.
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// Regular and strict (quiet and signaling) versions.
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FCMP, STRICT_FCMP, STRICT_FCMPS,
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FCMP,
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// Test under mask. The first operand is ANDed with the second operand
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// and the condition codes are set on the result. The third operand is
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@ -249,10 +248,9 @@ enum NodeType : unsigned {
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// Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
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// vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
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// greater than" and VFCMPHE for "ordered and greater than or equal to".
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// Regular and strict (quiet and signaling) versions.
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VFCMPE, STRICT_VFCMPE, STRICT_VFCMPES,
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VFCMPH, STRICT_VFCMPH, STRICT_VFCMPHS,
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VFCMPHE, STRICT_VFCMPHE, STRICT_VFCMPHES,
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VFCMPE,
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VFCMPH,
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VFCMPHE,
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// Likewise, but also set the condition codes on the result.
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VFCMPES,
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@ -263,12 +261,12 @@ enum NodeType : unsigned {
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VFTCI,
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// Extend the even f32 elements of vector operand 0 to produce a vector
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// of f64 elements. Regular and strict versions.
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VEXTEND, STRICT_VEXTEND,
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// of f64 elements.
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VEXTEND,
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// Round the f64 elements of vector operand 0 to f32s and store them in the
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// even elements of the result. Regular and strict versions.
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VROUND, STRICT_VROUND,
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// even elements of the result.
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VROUND,
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// AND the two vector operands together and set CC based on the result.
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VTM,
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@ -292,6 +290,24 @@ enum NodeType : unsigned {
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// Operand 1: the bit mask
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TDC,
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// Strict variants of scalar floating-point comparisons.
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// Quiet and signaling versions.
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STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
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STRICT_FCMPS,
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// Strict variants of vector floating-point comparisons.
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// Quiet and signaling versions.
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STRICT_VFCMPE,
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STRICT_VFCMPH,
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STRICT_VFCMPHE,
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STRICT_VFCMPES,
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STRICT_VFCMPHS,
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STRICT_VFCMPHES,
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// Strict variants of VEXTEND and VROUND.
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STRICT_VEXTEND,
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STRICT_VROUND,
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// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
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// ATOMIC_LOAD_<op>.
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//
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@ -79,9 +79,6 @@ namespace llvm {
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 strict FP compare instructions.
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STRICT_FCMP, STRICT_FCMPS,
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/// X86 bit-test instructions.
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BT,
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@ -325,7 +322,6 @@ namespace llvm {
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// Vector packed double/float comparison.
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CMPP,
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STRICT_CMPP,
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// Vector integer comparisons.
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PCMPEQ, PCMPGT,
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@ -338,7 +334,6 @@ namespace llvm {
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/// Vector comparison generating mask bits for fp and
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/// integer signed and unsigned data types.
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CMPM,
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STRICT_CMPM,
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// Vector comparison with SAE for FP values
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CMPM_SAE,
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@ -506,7 +501,6 @@ namespace llvm {
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// Vector float/double to signed/unsigned integer with truncation.
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CVTTP2SI, CVTTP2UI, CVTTP2SI_SAE, CVTTP2UI_SAE,
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STRICT_CVTTP2SI, STRICT_CVTTP2UI,
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// Scalar float/double to signed/unsigned integer with truncation.
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CVTTS2SI, CVTTS2UI, CVTTS2SI_SAE, CVTTS2UI_SAE,
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@ -605,6 +599,20 @@ namespace llvm {
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// For avx512-vp2intersect
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VP2INTERSECT,
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/// X86 strict FP compare instructions.
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STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
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STRICT_FCMPS,
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// Vector packed double/float comparison.
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STRICT_CMPP,
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/// Vector comparison generating mask bits for fp and
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/// integer signed and unsigned data types.
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STRICT_CMPM,
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// Vector float/double to signed/unsigned integer with truncation.
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STRICT_CVTTP2SI, STRICT_CVTTP2UI,
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// Compare and swap.
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LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LCMPXCHG8_DAG,
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@ -4,7 +4,7 @@ define i32 @f20u(double %x) #0 {
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; CHECK-LABEL: name: f20u
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
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; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY]], implicit $mxcsr
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; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = fpexcept CVTTSD2SI64rr [[COPY]], implicit $mxcsr
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[CVTTSD2SI64rr]].sub_32bit
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; CHECK: $eax = COPY [[COPY1]]
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; CHECK: RET 0, $eax
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@ -29,14 +29,14 @@ entry:
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; CHECK-LABEL: name: f20u64
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; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
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; CHECK: [[MOVSDrm_alt1:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
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; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
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; CHECK: fpexcept COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
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; CHECK: [[FsFLD0SD:%[0-9]+]]:fr64 = FsFLD0SD
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; CHECK: JCC_1
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; CHECK: [[PHI:%[0-9]+]]:fr64 = PHI [[MOVSDrm_alt1]], {{.*}}, [[FsFLD0SD]], {{.*}}
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; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
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; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = fpexcept SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
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; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[SUBSDrr]] :: (store 8 into %stack.0)
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
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; CHECK: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0)
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; CHECK: [[LD_Fp64m:%[0-9]+]]:rfp64 = fpexcept LD_Fp64m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0)
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; CHECK: FNSTCW16m %stack.1, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (store 2 into %stack.1)
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; CHECK: [[MOVZX32rm16_:%[0-9]+]]:gr32 = MOVZX32rm16 %stack.1, 1, $noreg, 0, $noreg :: (load 2 from %stack.1)
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; CHECK: [[OR32ri:%[0-9]+]]:gr32 = OR32ri killed [[MOVZX32rm16_]], 3072, implicit-def $eflags
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@ -59,7 +59,7 @@ entry:
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define i8 @f20s8(double %x) #0 {
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entry:
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; CHECK-LABEL: name: f20s8
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; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
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; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
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; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY [[CVTTSD2SIrm]]
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; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; CHECK: $al = COPY [[COPY1]]
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@ -71,7 +71,7 @@ entry:
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define i16 @f20s16(double %x) #0 {
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entry:
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; CHECK-LABEL: name: f20s16
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; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
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; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
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; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrm]].sub_16bit
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; CHECK: $ax = COPY [[COPY]]
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; CHECK: RET 0, $ax
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@ -84,15 +84,15 @@ entry:
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; CHECK-LABEL: name: f20u
|
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; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[MOVSDrm_alt1:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
|
||||
; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
|
||||
; CHECK: fpexcept COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
|
||||
; CHECK: [[FsFLD0SD:%[0-9]+]]:fr64 = FsFLD0SD
|
||||
; CHECK: JCC_1
|
||||
; CHECK: [[PHI:%[0-9]+]]:fr64 = PHI [[MOVSDrm_alt1]], {{.*}}, [[FsFLD0SD]], {{.*}}
|
||||
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
|
||||
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
|
||||
; CHECK: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[MOVZX32rr8_]], 31, implicit-def dead $eflags
|
||||
; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
|
||||
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
|
||||
; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = fpexcept SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
|
||||
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
|
||||
; CHECK: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[CVTTSD2SIrr]], killed [[SHL32ri]], implicit-def dead $eflags
|
||||
; CHECK: $eax = COPY [[XOR32rr]]
|
||||
; CHECK: RET 0, $eax
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
define <1 x float> @constrained_vector_fadd_v1f32() #0 {
|
||||
; CHECK-LABEL: name: constrained_vector_fadd_v1f32
|
||||
; CHECK: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: $xmm0 = COPY [[ADDSSrm]]
|
||||
; CHECK: RET 0, $xmm0
|
||||
entry:
|
||||
@ -15,9 +15,9 @@ define <3 x float> @constrained_vector_fadd_v3f32() #0 {
|
||||
; CHECK-LABEL: name: constrained_vector_fadd_v3f32
|
||||
; CHECK: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
|
||||
; CHECK: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = fpexcept ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY [[ADDSSrm1]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[ADDSSrm]]
|
||||
; CHECK: [[UNPCKLPSrr:%[0-9]+]]:vr128 = UNPCKLPSrr [[COPY1]], killed [[COPY]]
|
||||
@ -38,8 +38,8 @@ entry:
|
||||
define <4 x double> @constrained_vector_fadd_v4f64() #0 {
|
||||
; CHECK-LABEL: name: constrained_vector_fadd_v4f64
|
||||
; CHECK: [[MOVAPDrm:%[0-9]+]]:vr128 = MOVAPDrm $rip, 1, $noreg, %const.0, $noreg :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: $xmm0 = COPY [[ADDPDrm]]
|
||||
; CHECK: $xmm1 = COPY [[ADDPDrm1]]
|
||||
; CHECK: RET 0, $xmm0, $xmm1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user