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[AArch64][SVE] Asm: Support for predicated unary operations.
This patch adds support for the following instructions: CLS (Count Leading Sign bits) CLZ (Count Leading Zeros) CNT (Count non-zero bits) CNOT (Logically invert boolean condition in vector) NOT (Bitwise invert vector) FABS (Floating-point absolute value) FNEG (Floating-point negate) All operations are predicated and unary, e.g. clz z0.s, p0/m, z1.s - CLS, CLZ, CNT, CNOT and NOT have variants for 8, 16, 32 and 64 bit elements. - FABS and FNEG have variants for 16, 32 and 64 bit elements. llvm-svn: 336677
This commit is contained in:
Sander de Smalen
parent
1d7c3b6f9e
commit
d48e3148d9
@ -66,6 +66,14 @@ let Predicates = [HasSVE] in {
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defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs">;
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defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg">;
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defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls">;
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defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz">;
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defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt">;
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defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot">;
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defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not">;
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defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">;
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defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">;
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defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">;
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defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">;
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defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">;
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@ -1159,8 +1159,8 @@ multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> {
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// SVE Integer Arithmetic - Unary Predicated Group
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//===----------------------------------------------------------------------===//
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class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
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ZPRRegOp zprty>
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class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
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string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
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asm, "\t$Zd, $Pg/m, $Zn",
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"",
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@ -1170,8 +1170,9 @@ class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
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bits<5> Zn;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21-19} = 0b010;
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let Inst{18-16} = opc;
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let Inst{21-20} = 0b01;
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let Inst{19} = opc{0};
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let Inst{18-16} = opc{3-1};
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let Inst{15-13} = 0b101;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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@ -1181,27 +1182,39 @@ class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
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}
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multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> {
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def _B : sve_int_un_pred_arit_0<0b00, opc, asm, ZPR8>;
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def _H : sve_int_un_pred_arit_0<0b01, opc, asm, ZPR16>;
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def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
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def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
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def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>;
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def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
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def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
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def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
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}
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multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> {
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def _H : sve_int_un_pred_arit_0<0b01, opc, asm, ZPR16>;
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def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
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def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
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def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
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def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
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def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
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}
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multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> {
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def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
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def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
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def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
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def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
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}
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multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> {
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def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
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def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
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}
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multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm> {
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def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>;
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def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
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def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
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def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
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}
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multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm> {
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def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
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def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
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def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Integer Wide Immediate - Unpredicated Group
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18
test/MC/AArch64/SVE/cls-diagnostics.s
Normal file
18
test/MC/AArch64/SVE/cls-diagnostics.s
Normal file
@ -0,0 +1,18 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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cls z31.b, p8/m, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: cls z31.b, p8/m, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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cls z31.b, p7/m, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: cls z31.b, p7/m, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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32
test/MC/AArch64/SVE/cls.s
Normal file
32
test/MC/AArch64/SVE/cls.s
Normal file
@ -0,0 +1,32 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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cls z31.b, p7/m, z31.b
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// CHECK-INST: cls z31.b, p7/m, z31.b
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// CHECK-ENCODING: [0xff,0xbf,0x18,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 18 04 <unknown>
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cls z31.h, p7/m, z31.h
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// CHECK-INST: cls z31.h, p7/m, z31.h
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// CHECK-ENCODING: [0xff,0xbf,0x58,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 58 04 <unknown>
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cls z31.s, p7/m, z31.s
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// CHECK-INST: cls z31.s, p7/m, z31.s
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// CHECK-ENCODING: [0xff,0xbf,0x98,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 98 04 <unknown>
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cls z31.d, p7/m, z31.d
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// CHECK-INST: cls z31.d, p7/m, z31.d
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// CHECK-ENCODING: [0xff,0xbf,0xd8,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf d8 04 <unknown>
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18
test/MC/AArch64/SVE/clz-diagnostics.s
Normal file
18
test/MC/AArch64/SVE/clz-diagnostics.s
Normal file
@ -0,0 +1,18 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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clz z31.b, p8/m, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: clz z31.b, p8/m, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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clz z31.b, p7/m, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: clz z31.b, p7/m, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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32
test/MC/AArch64/SVE/clz.s
Normal file
32
test/MC/AArch64/SVE/clz.s
Normal file
@ -0,0 +1,32 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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clz z31.b, p7/m, z31.b
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// CHECK-INST: clz z31.b, p7/m, z31.b
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// CHECK-ENCODING: [0xff,0xbf,0x19,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 19 04 <unknown>
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clz z31.h, p7/m, z31.h
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// CHECK-INST: clz z31.h, p7/m, z31.h
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// CHECK-ENCODING: [0xff,0xbf,0x59,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 59 04 <unknown>
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clz z31.s, p7/m, z31.s
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// CHECK-INST: clz z31.s, p7/m, z31.s
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// CHECK-ENCODING: [0xff,0xbf,0x99,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 99 04 <unknown>
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clz z31.d, p7/m, z31.d
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// CHECK-INST: clz z31.d, p7/m, z31.d
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// CHECK-ENCODING: [0xff,0xbf,0xd9,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf d9 04 <unknown>
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18
test/MC/AArch64/SVE/cnot-diagnostics.s
Normal file
18
test/MC/AArch64/SVE/cnot-diagnostics.s
Normal file
@ -0,0 +1,18 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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cnot z31.b, p8/m, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: cnot z31.b, p8/m, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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cnot z31.b, p7/m, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: cnot z31.b, p7/m, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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32
test/MC/AArch64/SVE/cnot.s
Normal file
32
test/MC/AArch64/SVE/cnot.s
Normal file
@ -0,0 +1,32 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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cnot z31.b, p7/m, z31.b
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// CHECK-INST: cnot z31.b, p7/m, z31.b
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// CHECK-ENCODING: [0xff,0xbf,0x1b,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 1b 04 <unknown>
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cnot z31.h, p7/m, z31.h
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// CHECK-INST: cnot z31.h, p7/m, z31.h
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// CHECK-ENCODING: [0xff,0xbf,0x5b,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 5b 04 <unknown>
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cnot z31.s, p7/m, z31.s
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// CHECK-INST: cnot z31.s, p7/m, z31.s
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// CHECK-ENCODING: [0xff,0xbf,0x9b,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 9b 04 <unknown>
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cnot z31.d, p7/m, z31.d
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// CHECK-INST: cnot z31.d, p7/m, z31.d
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// CHECK-ENCODING: [0xff,0xbf,0xdb,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf db 04 <unknown>
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18
test/MC/AArch64/SVE/cnt-diagnostics.s
Normal file
18
test/MC/AArch64/SVE/cnt-diagnostics.s
Normal file
@ -0,0 +1,18 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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cnt z31.b, p8/m, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: cnt z31.b, p8/m, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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cnt z31.b, p7/m, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: cnt z31.b, p7/m, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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32
test/MC/AArch64/SVE/cnt.s
Normal file
32
test/MC/AArch64/SVE/cnt.s
Normal file
@ -0,0 +1,32 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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cnt z31.b, p7/m, z31.b
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// CHECK-INST: cnt z31.b, p7/m, z31.b
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// CHECK-ENCODING: [0xff,0xbf,0x1a,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 1a 04 <unknown>
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cnt z31.h, p7/m, z31.h
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// CHECK-INST: cnt z31.h, p7/m, z31.h
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// CHECK-ENCODING: [0xff,0xbf,0x5a,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 5a 04 <unknown>
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cnt z31.s, p7/m, z31.s
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// CHECK-INST: cnt z31.s, p7/m, z31.s
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// CHECK-ENCODING: [0xff,0xbf,0x9a,0x04]
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// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 9a 04 <unknown>
|
||||
|
||||
cnt z31.d, p7/m, z31.d
|
||||
// CHECK-INST: cnt z31.d, p7/m, z31.d
|
||||
// CHECK-ENCODING: [0xff,0xbf,0xda,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf da 04 <unknown>
|
||||
23
test/MC/AArch64/SVE/fabs-diagnostics.s
Normal file
23
test/MC/AArch64/SVE/fabs-diagnostics.s
Normal file
@ -0,0 +1,23 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid predicate
|
||||
|
||||
fabs z31.h, p8/m, z31.h
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: fabs z31.h, p8/m, z31.h
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid element width
|
||||
|
||||
fabs z31.b, p7/m, z31.b
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fabs z31.b, p7/m, z31.b
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fabs z31.h, p7/m, z31.s
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fabs z31.h, p7/m, z31.s
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
26
test/MC/AArch64/SVE/fabs.s
Normal file
26
test/MC/AArch64/SVE/fabs.s
Normal file
@ -0,0 +1,26 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
fabs z31.h, p7/m, z31.h
|
||||
// CHECK-INST: fabs z31.h, p7/m, z31.h
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x5c,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 5c 04 <unknown>
|
||||
|
||||
fabs z31.s, p7/m, z31.s
|
||||
// CHECK-INST: fabs z31.s, p7/m, z31.s
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x9c,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 9c 04 <unknown>
|
||||
|
||||
fabs z31.d, p7/m, z31.d
|
||||
// CHECK-INST: fabs z31.d, p7/m, z31.d
|
||||
// CHECK-ENCODING: [0xff,0xbf,0xdc,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf dc 04 <unknown>
|
||||
23
test/MC/AArch64/SVE/fneg-diagnostics.s
Normal file
23
test/MC/AArch64/SVE/fneg-diagnostics.s
Normal file
@ -0,0 +1,23 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid predicate
|
||||
|
||||
fneg z31.h, p8/m, z31.h
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: fneg z31.h, p8/m, z31.h
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid element width
|
||||
|
||||
fneg z31.b, p7/m, z31.b
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fneg z31.b, p7/m, z31.b
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fneg z31.h, p7/m, z31.s
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fneg z31.h, p7/m, z31.s
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
26
test/MC/AArch64/SVE/fneg.s
Normal file
26
test/MC/AArch64/SVE/fneg.s
Normal file
@ -0,0 +1,26 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
fneg z31.h, p7/m, z31.h
|
||||
// CHECK-INST: fneg z31.h, p7/m, z31.h
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x5d,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 5d 04 <unknown>
|
||||
|
||||
fneg z31.s, p7/m, z31.s
|
||||
// CHECK-INST: fneg z31.s, p7/m, z31.s
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x9d,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 9d 04 <unknown>
|
||||
|
||||
fneg z31.d, p7/m, z31.d
|
||||
// CHECK-INST: fneg z31.d, p7/m, z31.d
|
||||
// CHECK-ENCODING: [0xff,0xbf,0xdd,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf dd 04 <unknown>
|
||||
18
test/MC/AArch64/SVE/not-diagnostics.s
Normal file
18
test/MC/AArch64/SVE/not-diagnostics.s
Normal file
@ -0,0 +1,18 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid predicate
|
||||
|
||||
not z31.b, p8/m, z31.b
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: not z31.b, p8/m, z31.b
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid element width
|
||||
|
||||
not z31.b, p7/m, z31.h
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: not z31.b, p7/m, z31.h
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
@ -7,6 +7,30 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
not z31.b, p7/m, z31.b
|
||||
// CHECK-INST: not z31.b, p7/m, z31.b
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x1e,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 1e 04 <unknown>
|
||||
|
||||
not z31.h, p7/m, z31.h
|
||||
// CHECK-INST: not z31.h, p7/m, z31.h
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x5e,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 5e 04 <unknown>
|
||||
|
||||
not z31.s, p7/m, z31.s
|
||||
// CHECK-INST: not z31.s, p7/m, z31.s
|
||||
// CHECK-ENCODING: [0xff,0xbf,0x9e,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf 9e 04 <unknown>
|
||||
|
||||
not z31.d, p7/m, z31.d
|
||||
// CHECK-INST: not z31.d, p7/m, z31.d
|
||||
// CHECK-ENCODING: [0xff,0xbf,0xde,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff bf de 04 <unknown>
|
||||
|
||||
not p0.b, p0/z, p0.b
|
||||
// CHECK-INST: not p0.b, p0/z, p0.b
|
||||
// CHECK-ENCODING: [0x00,0x42,0x00,0x25]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user