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GlobalISel: support translation of extractvalue instructions.

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llvm-svn: 279285
This commit is contained in:
Tim Northover 2016-08-19 17:47:05 +00:00
parent e189b72731
commit d497ada993
6 changed files with 37 additions and 4 deletions
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3
include/llvm/CodeGen/GlobalISel/IRTranslator.h
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@ -149,6 +149,8 @@ private:
/// \pre \p U is a branch instruction.
bool translateBr(const User &U);
bool translateExtractValue(const User &U);
/// Translate return (ret) instruction.
/// The target needs to implement CallLowering::lowerReturn for
/// this to succeed.
@ -266,7 +268,6 @@ private:
bool translateExtractElement(const User &U) { return false; }
bool translateInsertElement(const User &U) { return false; }
bool translateShuffleVector(const User &U) { return false; }
bool translateExtractValue(const User &U) { return false; }
bool translateInsertValue(const User &U) { return false; }
bool translateLandingPad(const User &U) { return false; }

2
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
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@ -225,7 +225,7 @@ public:
///
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildExtract(LLT Ty, ArrayRef<unsigned> Results,
unsigned Src, ArrayRef<unsigned> Indexes);
unsigned Src, ArrayRef<uint64_t> Indexes);
/// Build and insert \p Res<def> = G_SEQUENCE \p Ty \p Op0, \p Idx0...
///

21
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -182,6 +182,27 @@ bool IRTranslator::translateStore(const User &U) {
return true;
}
bool IRTranslator::translateExtractValue(const User &U) {
const ExtractValueInst &EVI = cast<ExtractValueInst>(U);
const Value *Src = EVI.getAggregateOperand();
Type *Int32Ty = Type::getInt32Ty(EVI.getContext());
SmallVector<Value *, 1> Indices;
// getIndexedOffsetInType is designed for GEPs, so the first index is the
// usual array element rather than looking into the actual aggregate.
Indices.push_back(ConstantInt::get(Int32Ty, 0));
for (auto Idx : EVI.indices())
Indices.push_back(ConstantInt::get(Int32Ty, Idx));
uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
unsigned Res = getOrCreateVReg(EVI);
MIRBuilder.buildExtract(LLT{*EVI.getType()}, Res, getOrCreateVReg(*Src),
Offset);
return true;
}
bool IRTranslator::translateBitCast(const User &U) {
if (LLT{*U.getOperand(0)->getType()} == LLT{*U.getType()}) {
unsigned &Reg = ValToVReg[&U];

2
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
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@ -143,7 +143,7 @@ MachineInstrBuilder MachineIRBuilder::buildAnyExtend(LLT Ty, unsigned Res,
MachineInstrBuilder
MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results, unsigned Src,
ArrayRef<unsigned> Indexes) {
ArrayRef<uint64_t> Indexes) {
assert(Results.size() == Indexes.size() && "inconsistent number of regs");
MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_EXTRACT, Ty);

2
lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
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@ -51,7 +51,7 @@ MachineLegalizeHelper::LegalizeResult MachineLegalizeHelper::legalizeInstr(
void MachineLegalizeHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
SmallVectorImpl<unsigned> &VRegs) {
unsigned Size = Ty.getSizeInBits();
SmallVector<unsigned, 4> Indexes;
SmallVector<uint64_t, 4> Indexes;
for (int i = 0; i < NumParts; ++i) {
VRegs.push_back(MRI.createGenericVirtualRegister(Size));
Indexes.push_back(i * Size);

11
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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@ -682,3 +682,14 @@ define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
store { i32, i1 } %res, { i32, i1 }* %addr
ret void
}
; CHECK-LABEL: name: test_extractvalue
; CHECK: [[STRUCT:%[0-9]+]](128) = G_LOAD { s128, p0 }
; CHECK: [[RES:%[0-9]+]](32) = G_EXTRACT s32 [[STRUCT]], 64
; CHECK: %w0 = COPY [[RES]]
%struct.nested = type {i8, { i8, i32 }, i32}
define i32 @test_extractvalue(%struct.nested* %addr) {
%struct = load %struct.nested, %struct.nested* %addr
%res = extractvalue %struct.nested %struct, 1, 1
ret i32 %res
}