[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing

Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608

include/llvm/CodeGen/MachineFunction.h

@@ -277,7 +277,7 @@ class MachineFunction {
   unsigned FunctionNumber;
 
   /// Alignment - The alignment of the function.
-  unsigned LogAlignment;
+  llvm::Align Alignment;
 
   /// ExposesReturnsTwice - True if the function calls setjmp or related
   /// functions with attribute "returns twice", but doesn't have
@@ -508,16 +508,16 @@ public:
   const WinEHFuncInfo *getWinEHFuncInfo() const { return WinEHInfo; }
   WinEHFuncInfo *getWinEHFuncInfo() { return WinEHInfo; }
 
-  /// getLogAlignment - Return the alignment of the function.
+  /// getAlignment - Return the alignment of the function.
-  unsigned getLogAlignment() const { return LogAlignment; }
+  llvm::Align getAlignment() const { return Alignment; }
 
-  /// setLogAlignment - Set the alignment of the function.
+  /// setAlignment - Set the alignment of the function.
-  void setLogAlignment(unsigned A) { LogAlignment = A; }
+  void setAlignment(llvm::Align A) { Alignment = A; }
 
-  /// ensureAlignment - Make sure the function is at least 1 << A bytes aligned.
+  /// ensureAlignment - Make sure the function is at least A bytes aligned.
-  void ensureLogAlignment(unsigned A) {
+  void ensureAlignment(llvm::Align A) {
-    if (LogAlignment < A)
+    if (Alignment < A)
-      LogAlignment = A;
+      Alignment = A;
   }
 
   /// exposesReturnsTwice - Returns true if the function calls setjmp or

include/llvm/CodeGen/TargetLowering.h

@@ -1583,14 +1583,10 @@ public:
   }
 
   /// Return the minimum function alignment.
-  unsigned getMinFunctionLogAlignment() const {
+  llvm::Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
-    return Log2(MinFunctionAlignment);
-  }
 
   /// Return the preferred function alignment.
-  unsigned getPrefFunctionLogAlignment() const {
+  llvm::Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
-    return Log2(PrefFunctionAlignment);
-  }
 
   /// Return the preferred loop alignment.
   virtual llvm::Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

@@ -667,7 +667,7 @@ void AsmPrinter::EmitFunctionHeader() {
 
   EmitLinkage(&F, CurrentFnSym);
   if (MAI->hasFunctionAlignment())
-    EmitAlignment(MF->getLogAlignment(), &F);
+    EmitAlignment(Log2(MF->getAlignment()), &F);
 
   if (MAI->hasDotTypeDotSizeDirective())
     OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction);

lib/CodeGen/AsmPrinter/WinException.cpp

@@ -204,7 +204,7 @@ void WinException::beginFunclet(const MachineBasicBlock &MBB,
     // We want our funclet's entry point to be aligned such that no nops will be
     // present after the label.
     Asm->EmitAlignment(
-        std::max(Asm->MF->getLogAlignment(), MBB.getLogAlignment()), &F);
+        Log2(std::max(Asm->MF->getAlignment(), MBB.getAlignment())), &F);
 
     // Now that we've emitted the alignment directive, point at our funclet.
     Asm->OutStreamer->EmitLabel(Sym);

lib/CodeGen/BranchRelaxation.cpp

@@ -64,19 +64,18 @@ class BranchRelaxation : public MachineFunctionPass {
     /// Compute the offset immediately following this block. \p MBB is the next
     /// block.
     unsigned postOffset(const MachineBasicBlock &MBB) const {
-      unsigned PO = Offset + Size;
+      const unsigned PO = Offset + Size;
-      unsigned LogAlign = MBB.getLogAlignment();
+      const llvm::Align Align = MBB.getAlignment();
-      if (LogAlign == 0)
+      if (Align == 1)
         return PO;
 
-      unsigned AlignAmt = 1 << LogAlign;
+      const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
-      unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
+      if (Align <= ParentAlign)
-      if (LogAlign <= ParentLogAlign)
+        return PO + OffsetToAlignment(PO, Align.value());
-        return PO + OffsetToAlignment(PO, AlignAmt);
 
       // The alignment of this MBB is larger than the function's alignment, so we
       // can't tell whether or not it will insert nops. Assume that it will.
-      return PO + AlignAmt + OffsetToAlignment(PO, AlignAmt);
+      return PO + Align.value() + OffsetToAlignment(PO, Align.value());
     }
   };
 

lib/CodeGen/MIRParser/MIRParser.cpp

@@ -393,7 +393,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
   }
 
   if (YamlMF.Alignment)
-    MF.setLogAlignment(Log2_32(YamlMF.Alignment));
+    MF.setAlignment(llvm::Align(YamlMF.Alignment));
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasWinCFI(YamlMF.HasWinCFI);
 

lib/CodeGen/MIRPrinter.cpp

@@ -197,7 +197,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
 
   yaml::MachineFunction YamlMF;
   YamlMF.Name = MF.getName();
-  YamlMF.Alignment = 1UL << MF.getLogAlignment();
+  YamlMF.Alignment = MF.getAlignment().value();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasWinCFI = MF.hasWinCFI();
 

lib/CodeGen/MachineFunction.cpp

@@ -173,16 +173,16 @@ void MachineFunction::init() {
     FrameInfo->ensureMaxAlignment(F.getFnStackAlignment());
 
   ConstantPool = new (Allocator) MachineConstantPool(getDataLayout());
-  LogAlignment = STI->getTargetLowering()->getMinFunctionLogAlignment();
+  Alignment = STI->getTargetLowering()->getMinFunctionAlignment();
 
   // FIXME: Shouldn't use pref alignment if explicit alignment is set on F.
   // FIXME: Use Function::hasOptSize().
   if (!F.hasFnAttribute(Attribute::OptimizeForSize))
-    LogAlignment = std::max(
+    Alignment = std::max(Alignment,
-        LogAlignment, STI->getTargetLowering()->getPrefFunctionLogAlignment());
+                         STI->getTargetLowering()->getPrefFunctionAlignment());
 
   if (AlignAllFunctions)
-    LogAlignment = AlignAllFunctions;
+    Alignment = llvm::Align(1ULL << AlignAllFunctions);
 
   JumpTableInfo = nullptr;
 

lib/CodeGen/PatchableFunction.cpp

@@ -78,7 +78,7 @@ bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
     MIB.add(MO);
 
   FirstActualI->eraseFromParent();
-  MF.ensureLogAlignment(4);
+  MF.ensureAlignment(llvm::Align(16));
   return true;
 }
 

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

@@ -417,7 +417,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
   // The starting address of all shader programs must be 256 bytes aligned.
   // Regular functions just need the basic required instruction alignment.
-  MF.setLogAlignment(MFI->isEntryFunction() ? 8 : 2);
+  MF.setAlignment(MFI->isEntryFunction() ? llvm::Align(256) : llvm::Align(4));
 
   SetupMachineFunction(MF);
 

lib/Target/AMDGPU/R600AsmPrinter.cpp

@@ -104,7 +104,7 @@ bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
 
   // Functions needs to be cacheline (256B) aligned.
-  MF.ensureLogAlignment(8);
+  MF.ensureAlignment(llvm::Align(256));
 
   SetupMachineFunction(MF);
 

lib/Target/ARC/ARCMachineFunctionInfo.h

@@ -34,8 +34,8 @@ public:
   explicit ARCFunctionInfo(MachineFunction &MF)
       : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
         ReturnStackOffset(-1U), MaxCallStackReq(0) {
-    // Functions are 4-byte (2**2) aligned.
+    // Functions are 4-byte aligned.
-    MF.setLogAlignment(2);
+    MF.setAlignment(llvm::Align(4));
   }
 
   ~ARCFunctionInfo() {}

lib/Target/ARM/ARMBasicBlockInfo.cpp

@@ -63,7 +63,7 @@ void ARMBasicBlockUtils::computeBlockSize(MachineBasicBlock *MBB) {
   // tBR_JTr contains a .align 2 directive.
   if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
     BBI.PostAlign = 2;
-    MBB->getParent()->ensureLogAlignment(2);
+    MBB->getParent()->ensureAlignment(llvm::Align(4));
   }
 }
 

lib/Target/ARM/ARMConstantIslandPass.cpp

@@ -396,7 +396,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   // Functions with jump tables need an alignment of 4 because they use the ADR
   // instruction, which aligns the PC to 4 bytes before adding an offset.
   if (!T2JumpTables.empty())
-    MF->ensureLogAlignment(2);
+    MF->ensureAlignment(llvm::Align(4));
 
   /// Remove dead constant pool entries.
   MadeChange |= removeUnusedCPEntries();
@@ -493,7 +493,7 @@ ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs)
 
   // The function needs to be as aligned as the basic blocks. The linker may
   // move functions around based on their alignment.
-  MF->ensureLogAlignment(BB->getLogAlignment());
+  MF->ensureAlignment(BB->getAlignment());
 
   // Order the entries in BB by descending alignment.  That ensures correct
   // alignment of all entries as long as BB is sufficiently aligned.  Keep
@@ -686,7 +686,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
   // The known bits of the entry block offset are determined by the function
   // alignment.
-  BBInfo.front().KnownBits = MF->getLogAlignment();
+  BBInfo.front().KnownBits = Log2(MF->getAlignment());
 
   // Compute block offsets and known bits.
   BBUtils->adjustBBOffsetsAfter(&MF->front());
@@ -1041,7 +1041,8 @@ bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
     // the offset of the instruction. Also account for unknown alignment padding
     // in blocks between CPE and the user.
     if (CPEOffset < UserOffset)
-      UserOffset += Growth + UnknownPadding(MF->getLogAlignment(), CPELogAlign);
+      UserOffset +=
+          Growth + UnknownPadding(Log2(MF->getAlignment()), CPELogAlign);
   } else
     // CPE fits in existing padding.
     Growth = 0;
@@ -1316,7 +1317,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
   // Try to split the block so it's fully aligned.  Compute the latest split
   // point where we can add a 4-byte branch instruction, and then align to
   // LogAlign which is the largest possible alignment in the function.
-  unsigned LogAlign = MF->getLogAlignment();
+  unsigned LogAlign = Log2(MF->getAlignment());
   assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
   unsigned KnownBits = UserBBI.internalKnownBits();
   unsigned UPad = UnknownPadding(LogAlign, KnownBits);

lib/Target/Mips/MipsAsmPrinter.cpp

@@ -400,7 +400,8 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() {
   // NaCl sandboxing requires that indirect call instructions are masked.
   // This means that function entry points should be bundle-aligned.
   if (Subtarget->isTargetNaCl())
-    EmitAlignment(std::max(MF->getLogAlignment(), MIPS_NACL_BUNDLE_LOG_ALIGN));
+    EmitAlignment(
+        std::max(Log2(MF->getAlignment()), MIPS_NACL_BUNDLE_LOG_ALIGN));
 
   if (Subtarget->inMicroMipsMode()) {
     TS.emitDirectiveSetMicroMips();

lib/Target/Mips/MipsConstantIslandPass.cpp

@@ -542,7 +542,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) {
 
   // The function needs to be as aligned as the basic blocks. The linker may
   // move functions around based on their alignment.
-  MF->ensureLogAlignment(BB->getLogAlignment());
+  MF->ensureAlignment(BB->getAlignment());
 
   // Order the entries in BB by descending alignment.  That ensures correct
   // alignment of all entries as long as BB is sufficiently aligned.  Keep
@@ -1259,7 +1259,7 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex,
   // Try to split the block so it's fully aligned.  Compute the latest split
   // point where we can add a 4-byte branch instruction, and then align to
   // LogAlign which is the largest possible alignment in the function.
-  unsigned LogAlign = MF->getLogAlignment();
+  unsigned LogAlign = Log2(MF->getAlignment());
   assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
   unsigned BaseInsertOffset = UserOffset + U.getMaxDisp();
   LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",

lib/Target/PowerPC/PPCBranchSelector.cpp

@@ -81,21 +81,20 @@ FunctionPass *llvm::createPPCBranchSelectionPass() {
 /// original Offset.
 unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB,
                                          unsigned Offset) {
-  unsigned LogAlign = MBB.getLogAlignment();
+  const llvm::Align Align = MBB.getAlignment();
-  if (!LogAlign)
+  if (Align == 1)
     return 0;
 
-  unsigned AlignAmt = 1 << LogAlign;
+  const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
-  unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
 
-  if (LogAlign <= ParentLogAlign)
+  if (Align <= ParentAlign)
-    return OffsetToAlignment(Offset, AlignAmt);
+    return OffsetToAlignment(Offset, Align.value());
 
   // The alignment of this MBB is larger than the function's alignment, so we
   // can't tell whether or not it will insert nops. Assume that it will.
   if (FirstImpreciseBlock < 0)
     FirstImpreciseBlock = MBB.getNumber();
-  return AlignAmt + OffsetToAlignment(Offset, AlignAmt);
+  return Align.value() + OffsetToAlignment(Offset, Align.value());
 }
 
 /// We need to be careful about the offset of the first block in the function

lib/Target/SystemZ/SystemZLongBranch.cpp

@@ -276,7 +276,7 @@ uint64_t SystemZLongBranch::initMBBInfo() {
   Terminators.clear();
   Terminators.reserve(NumBlocks);
 
-  BlockPosition Position(MF->getLogAlignment());
+  BlockPosition Position(Log2(MF->getAlignment()));
   for (unsigned I = 0; I < NumBlocks; ++I) {
     MachineBasicBlock *MBB = MF->getBlockNumbered(I);
     MBBInfo &Block = MBBs[I];
@@ -340,7 +340,7 @@ bool SystemZLongBranch::mustRelaxABranch() {
 // must be long.
 void SystemZLongBranch::setWorstCaseAddresses() {
   SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
-  BlockPosition Position(MF->getLogAlignment());
+  BlockPosition Position(Log2(MF->getAlignment()));
   for (auto &Block : MBBs) {
     skipNonTerminators(Position, Block);
     for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
@@ -441,7 +441,7 @@ void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
 // Run a shortening pass and relax any branches that need to be relaxed.
 void SystemZLongBranch::relaxBranches() {
   SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
-  BlockPosition Position(MF->getLogAlignment());
+  BlockPosition Position(Log2(MF->getAlignment()));
   for (auto &Block : MBBs) {
     skipNonTerminators(Position, Block);
     for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {

test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

@@ -793,7 +793,7 @@ body:             |
 # Make sure we map FPEXT on FPR register bank.
 # CHECK-LABEL: name: fp16Ext32
 name:            fp16Ext32
-alignment:       2
+alignment:       4
 legalized:       true
 # CHECK: registers:
 # CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
@@ -828,7 +828,7 @@ body:             |
 # Make sure we map FPEXT on FPR register bank.
 # CHECK-LABEL: name: fp16Ext64
 name:            fp16Ext64
-alignment:       2
+alignment:       4
 legalized:       true
 # CHECK: registers:
 # CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
@@ -863,7 +863,7 @@ body:             |
 # Make sure we map FPEXT on FPR register bank.
 # CHECK-LABEL: name: fp32Ext64
 name:            fp32Ext64
-alignment:       2
+alignment:       4
 legalized:       true
 # CHECK: registers:
 # CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
@@ -897,7 +897,7 @@ body:             |
 # CHECK:  %0:fpr(s16) = COPY $h0
 # CHECK-NEXT: $h0 = COPY %0(s16)
 name:            passFp16
-alignment:       2
+alignment:       4
 legalized:       true
 registers:
   - { id: 0, class: _ }
@@ -931,7 +931,7 @@ body:             |
 # CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
 # CHECK-NEXT: $h0 = COPY %2(s16)
 name:            passFp16ViaAllocas
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 registers:

test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir

@@ -17,7 +17,7 @@
 ...
 ---
 name:            test_anyext_crash
-alignment:       2
+alignment:       4
 legalized:       false
 registers:       
   - { id: 0, class: _, preferred-register: '' }

test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir

@@ -14,7 +14,7 @@
 ...
 ---
 name:            fcmp_more_than_one_user_no_fold
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -50,7 +50,7 @@ body:             |
 ...
 ---
 name:            using_icmp
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -81,7 +81,7 @@ body:             |
 ...
 ---
 name:            foeq
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -111,7 +111,7 @@ body:             |
 ...
 ---
 name:            fueq
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -147,7 +147,7 @@ body:             |
 ...
 ---
 name:            fone
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -183,7 +183,7 @@ body:             |
 ...
 ---
 name:            fune
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -213,7 +213,7 @@ body:             |
 ...
 ---
 name:            doeq
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -243,7 +243,7 @@ body:             |
 ...
 ---
 name:            dueq
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -279,7 +279,7 @@ body:             |
 ...
 ---
 name:            done
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -315,7 +315,7 @@ body:             |
 ...
 ---
 name:            dune
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -345,7 +345,7 @@ body:             |
 ...
 ---
 name:            copy_from_physreg
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/fold-select.mir

@@ -9,7 +9,7 @@
 ...
 ---
 name:            eq
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -38,7 +38,7 @@ body:             |
 ...
 ---
 name:            using_fcmp
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir

@@ -15,7 +15,7 @@
 ...
 ---
 name:            x
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false

test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir

@@ -21,7 +21,7 @@
 ...
 ---
 name:            fp16_to_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -73,7 +73,7 @@ body:             |
 
 ---
 name:            gpr_to_fp16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -101,7 +101,7 @@ body:             |
 ...
 ---
 name:            gpr_to_fp16_physreg
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir

@@ -36,7 +36,7 @@
 ...
 ---
 name:            test_memcpy1
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -63,7 +63,7 @@ body:             |
 ...
 ---
 name:            test_memcpy2_const
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -110,7 +110,7 @@ body:             |
 ...
 ---
 name:            test_memcpy3_const_arrays_unaligned
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/inline-memmove.mir

@@ -44,7 +44,7 @@
 ...
 ---
 name:            test_memmove1
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
@@ -66,7 +66,7 @@ body:             |
 ...
 ---
 name:            test_memmove2_const
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
@@ -100,7 +100,7 @@ body:             |
 ...
 ---
 name:            test_memmove3_const_toolarge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
@@ -122,7 +122,7 @@ body:             |
 ...
 ---
 name:            test_memmove4_const_unaligned
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:

test/CodeGen/AArch64/GlobalISel/inline-memset.mir

@@ -41,7 +41,7 @@
 ...
 ---
 name:            test_ms1
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
@@ -67,7 +67,7 @@ body:             |
 ...
 ---
 name:            test_ms2_const
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
@@ -96,7 +96,7 @@ body:             |
 ...
 ---
 name:            test_ms3_const_both
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
@@ -120,7 +120,7 @@ body:             |
 ...
 ---
 name:            test_ms4_const_both_unaligned
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1.entry:

test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir

@@ -27,7 +27,7 @@
 ...
 ---
 name:            test_small_memcpy
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -59,7 +59,7 @@ body:             |
 ...
 ---
 name:            test_large_memcpy
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-add.mir

@@ -128,7 +128,7 @@ body:             |
 ...
 ---
 name:            add_v8i16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -151,7 +151,7 @@ body:             |
 ...
 ---
 name:            add_v16i8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir

@@ -17,7 +17,7 @@
 ...
 ---
 name:            test_blockaddress
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir

@@ -12,7 +12,7 @@
 ...
 ---
 name:            test_v8f16.ceil
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -55,7 +55,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.ceil
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

@@ -40,7 +40,7 @@ body:             |
 ...
 ---
 name:            test_s128
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: test_s128

test/CodeGen/AArch64/GlobalISel/legalize-cos.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.cos
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.cos
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -91,7 +91,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.cos
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.cos
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -170,7 +170,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.cos
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            test_cos_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-div.mir

@@ -41,7 +41,7 @@ body:             |
 ...
 ---
 name:            sdiv_v4s32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir

@@ -22,7 +22,7 @@
 ...
 ---
 name:            test_simple_alloca
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$w0' }
@@ -68,7 +68,7 @@ body:             |
 ...
 ---
 name:            test_aligned_alloca
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$w0' }
@@ -116,7 +116,7 @@ body:             |
 ...
 ---
 name:            test_natural_alloca
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$w0' }

test/CodeGen/AArch64/GlobalISel/legalize-exp.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.exp
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.exp
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -91,7 +91,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.exp
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.exp
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -170,7 +170,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.exp
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            test_exp_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-ext.mir

@@ -176,7 +176,7 @@ body:             |
 ...
 ---
 name:            test_zext_v8s16_from_v8s8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -196,7 +196,7 @@ body:             |
 ...
 ---
 name:            test_sext_v8s16_from_v8s8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -216,7 +216,7 @@ body:             |
 ...
 ---
 name:            test_anyext_v8s16_from_v8s8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -236,7 +236,7 @@ body:             |
 ...
 ---
 name:            test_zext_v4s32_from_v4s16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -257,7 +257,7 @@ body:             |
 ...
 ---
 name:            test_sext_v4s32_from_v4s16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -278,7 +278,7 @@ body:             |
 ...
 ---
 name:            test_anyext_v4s32_from_v4s16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -299,7 +299,7 @@ body:             |
 ...
 ---
 name:            test_zext_v2s64_from_v2s32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -323,7 +323,7 @@ body:             |
 ...
 ---
 name:            test_sext_v2s64_from_v2s32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -347,7 +347,7 @@ body:             |
 ...
 ---
 name:            test_anyext_v2s64_from_v2s32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir

@@ -5,7 +5,7 @@
 ...
 ---
 name:            test_v4f16.exp2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -53,7 +53,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.exp2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -129,7 +129,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.exp2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -159,7 +159,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.exp2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -199,7 +199,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.exp2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -229,7 +229,7 @@ body:             |
 ...
 ---
 name:            test_exp2_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:

test/CodeGen/AArch64/GlobalISel/legalize-fma.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.fma
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -60,7 +60,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.fma
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -136,7 +136,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.fma
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -169,7 +169,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.fma
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -202,7 +202,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.fma
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-frint.mir

@@ -3,7 +3,7 @@
 # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s --check-prefix=FP16
 
 name:            test_f16.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -18,7 +18,7 @@ body:             |
 ...
 ---
 name:            test_f32.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -45,7 +45,7 @@ body:             |
 ...
 ---
 name:            test_f64.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -72,7 +72,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -99,7 +99,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -126,7 +126,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -166,7 +166,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -218,7 +218,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.rint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir

@@ -6,7 +6,7 @@
 ...
 ---
 name:            test_f16.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -35,7 +35,7 @@ body:             |
 ...
 ---
 name:            test_f32.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -62,7 +62,7 @@ body:             |
 ...
 ---
 name:            test_f64.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -89,7 +89,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -141,7 +141,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -184,7 +184,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -214,7 +214,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -244,7 +244,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.round
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-trunc.mir

@@ -5,7 +5,7 @@
 ...
 ---
 name:            test_f16.intrinsic_trunc
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -32,7 +32,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.intrinsic_trunc
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -72,7 +72,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.intrinsic_trunc
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -124,7 +124,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.intrinsic_trunc
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -151,7 +151,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.intrinsic_trunc
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -178,7 +178,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.intrinsic_trunc
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir

@@ -21,7 +21,7 @@
 
 ---
 name:            broken
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir

@@ -24,7 +24,7 @@
 
 ---
 name:            broken
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir

@@ -19,7 +19,7 @@
 ...
 ---
 name:            store_v2p0
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -41,7 +41,7 @@ body:             |
 ...
 ---
 name:            load_v2p0
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -63,7 +63,7 @@ body:             |
 ...
 ---
 name:            load_v2p1
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

@@ -151,7 +151,7 @@ body: |
 ...
 ---
 name:            store_4xi16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -172,7 +172,7 @@ body:             |
 ...
 ---
 name:            store_4xi32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -193,7 +193,7 @@ body:             |
 ...
 ---
 name:            store_8xi16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -214,7 +214,7 @@ body:             |
 ...
 ---
 name:            store_16xi8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -235,7 +235,7 @@ body:             |
 ...
 ---
 name:            load_4xi16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -256,7 +256,7 @@ body:             |
 ...
 ---
 name:            load_4xi32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -277,7 +277,7 @@ body:             |
 ...
 ---
 name:            load_8xi16
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -298,7 +298,7 @@ body:             |
 ...
 ---
 name:            load_16xi8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -319,7 +319,7 @@ body:             |
 ...
 ---
 name:            load_8xi8
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-log.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.log
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.log
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -91,7 +91,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.log
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.log
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -170,7 +170,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.log
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            test_log_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-log10.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.log10
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.log10
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -91,7 +91,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.log10
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.log10
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -170,7 +170,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.log10
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            test_log10_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-log2.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.log2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.log2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -91,7 +91,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.log2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.log2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -170,7 +170,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.log2
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            test_log2_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir

@@ -5,7 +5,7 @@
 ...
 ---
 name:            test_v4f16.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -45,7 +45,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -97,7 +97,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -124,7 +124,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -151,7 +151,7 @@ body:             |
 ...
 ---
 name:            test_f32.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -178,7 +178,7 @@ body:             |
 ...
 ---
 name:            test_f64.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
@@ -205,7 +205,7 @@ body:             |
 ...
 ---
 name:            test_f16.nearbyint
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir

@@ -13,7 +13,7 @@
 ...
 ---
 name:            load_store_test
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1 (%ir-block.0):

test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

@@ -43,7 +43,7 @@
 ...
 ---
 name:            legalize_phi
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
@@ -130,7 +130,7 @@ body:             |
 ...
 ---
 name:            legalize_phi_ptr
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
@@ -184,7 +184,7 @@ body:             |
 ...
 ---
 name:            legalize_phi_empty
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
@@ -270,7 +270,7 @@ body:             |
 ...
 ---
 name:            legalize_phi_loop
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
@@ -338,7 +338,7 @@ body:             |
 ...
 ---
 name:            legalize_phi_cycle
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
@@ -395,7 +395,7 @@ body:             |
 ...
 ---
 name:            legalize_phi_same_bb
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
@@ -496,7 +496,7 @@ body:             |
 ...
 ---
 name:            legalize_phi_diff_bb
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false

test/CodeGen/AArch64/GlobalISel/legalize-pow.mir

@@ -35,7 +35,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.pow
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -95,7 +95,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.pow
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -191,7 +191,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.pow
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -227,7 +227,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.pow
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -275,7 +275,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.pow
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:

test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir

@@ -11,7 +11,7 @@
 ...
 ---
 name:            udiv_test
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
@@ -52,7 +52,7 @@ body:             |
 ...
 ---
 name:            sdiv_test
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }

test/CodeGen/AArch64/GlobalISel/legalize-select.mir

@@ -3,7 +3,7 @@
 ...
 ---
 name:            v2s64
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
@@ -37,7 +37,7 @@ body:             |
 ...
 ---
 name:            v2s32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:

test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir

@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=aarch64 -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
 ---
 name:            shuffle_v4i32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1:
@@ -24,7 +24,7 @@ body:             |
 ...
 ---
 name:            shuffle_v2i64
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1:
@@ -46,7 +46,7 @@ body:             |
 ...
 ---
 name:            shuffle_1elt_mask
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.1:

test/CodeGen/AArch64/GlobalISel/legalize-sin.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.sin
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.sin
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -91,7 +91,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.sin
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.sin
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -170,7 +170,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.sin
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            test_sin_half
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir

@@ -12,7 +12,7 @@
 ...
 ---
 name:            test_v8f16.sqrt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -55,7 +55,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.sqrt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir

@@ -2,7 +2,7 @@
 # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
 ---
 name:            test_v2i64_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -32,7 +32,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -62,7 +62,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -92,7 +92,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -122,7 +122,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -152,7 +152,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -182,7 +182,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -212,7 +212,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -242,7 +242,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -272,7 +272,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -302,7 +302,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -332,7 +332,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -362,7 +362,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -392,7 +392,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_ugt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -422,7 +422,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -452,7 +452,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -482,7 +482,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -512,7 +512,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -542,7 +542,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -572,7 +572,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -602,7 +602,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_uge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -632,7 +632,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -662,7 +662,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -692,7 +692,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -722,7 +722,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -752,7 +752,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -782,7 +782,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -812,7 +812,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_ult
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -842,7 +842,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -872,7 +872,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -902,7 +902,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -932,7 +932,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -962,7 +962,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -992,7 +992,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1022,7 +1022,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_ule
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1052,7 +1052,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1082,7 +1082,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1112,7 +1112,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1142,7 +1142,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1172,7 +1172,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1202,7 +1202,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1232,7 +1232,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_sgt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1262,7 +1262,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1292,7 +1292,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1322,7 +1322,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1352,7 +1352,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1382,7 +1382,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1412,7 +1412,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1442,7 +1442,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_sge
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1472,7 +1472,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1502,7 +1502,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1532,7 +1532,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1562,7 +1562,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1592,7 +1592,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1622,7 +1622,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1652,7 +1652,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_slt
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1682,7 +1682,7 @@ body:             |
 ...
 ---
 name:            test_v2i64_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1712,7 +1712,7 @@ body:             |
 ...
 ---
 name:            test_v4i32_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1742,7 +1742,7 @@ body:             |
 ...
 ---
 name:            test_v2i32_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1772,7 +1772,7 @@ body:             |
 ...
 ---
 name:            test_v8i16_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1802,7 +1802,7 @@ body:             |
 ...
 ---
 name:            test_v4i16_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1832,7 +1832,7 @@ body:             |
 ...
 ---
 name:            test_v16i8_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1862,7 +1862,7 @@ body:             |
 ...
 ---
 name:            test_v8i8_sle
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
@@ -1892,7 +1892,7 @@ body:             |
 ...
 ---
 name:            test_v2p0_eq
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir

@@ -4,7 +4,7 @@
 # This test checks we don't crash when doing zext(trunc) legalizer combines.
 ---
 name:            zext_trunc_dead_inst_crash
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: zext_trunc_dead_inst_crash

test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

@@ -29,7 +29,7 @@
 
 ---
 name:            ldrxrox_breg_oreg
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -55,7 +55,7 @@ body:             |
 
 ---
 name:            ldrdrox_breg_oreg
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -79,7 +79,7 @@ body:             |
 ...
 ---
 name:            more_than_one_use
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -111,7 +111,7 @@ body:             |
 ...
 ---
 name:            ldrxrox_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -138,7 +138,7 @@ body:             |
 ...
 ---
 name:            ldrdrox_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -165,7 +165,7 @@ body:             |
 ...
 ---
 name:            ldrxrox_mul_rhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -192,7 +192,7 @@ body:             |
 ...
 ---
 name:            ldrdrox_mul_rhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -219,7 +219,7 @@ body:             |
 ...
 ---
 name:            ldrxrox_mul_lhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -246,7 +246,7 @@ body:             |
 ...
 ---
 name:            ldrdrox_mul_lhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -273,7 +273,7 @@ body:             |
 ...
 ---
 name:            mul_not_pow_2
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -305,7 +305,7 @@ body:             |
 ...
 ---
 name:            mul_wrong_pow_2
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -337,7 +337,7 @@ body:             |
 ...
 ---
 name:            more_than_one_use_shl_1
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -371,7 +371,7 @@ body:             |
 ...
 ---
 name:            more_than_one_use_shl_2
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -410,7 +410,7 @@ body:             |
 ...
 ---
 name:            more_than_one_use_shl_lsl_fast
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -443,7 +443,7 @@ body:             |
 ...
 ---
 name:            more_than_one_use_shl_lsl_slow
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -478,7 +478,7 @@ body:             |
 ...
 ---
 name:            more_than_one_use_shl_minsize
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -515,7 +515,7 @@ body:             |
 ...
 ---
 name:            ldrwrox
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -539,7 +539,7 @@ body:             |
 ...
 ---
 name:            ldrsrox
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -563,7 +563,7 @@ body:             |
 ...
 ---
 name:            ldrhrox
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -587,7 +587,7 @@ body:             |
 ...
 ---
 name:            ldbbrox
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -611,7 +611,7 @@ body:             |
 ...
 ---
 name:            ldrqrox
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir

@@ -29,7 +29,7 @@
 ---
 # CHECK-LABEL: name: foo
 name:            foo
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/localizer.mir

@@ -392,7 +392,7 @@ body:             |
 ...
 ---
 name:            test_inttoptr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir

@@ -81,7 +81,7 @@ body:             |
 ...
 ---
 name:            int_extensions
-alignment:       2
+alignment:       4
 legalized:       false
 regBankSelected: false
 selected:        false

test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir

@@ -13,7 +13,7 @@
 ...
 ---
 name:            ld_zext_i24
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |

test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir

@@ -11,7 +11,7 @@
 ...
 ---
 name:            test
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

@@ -32,7 +32,7 @@
 ...
 ---
 name:            cmn_s32_rhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -64,7 +64,7 @@ body:             |
 ...
 ---
 name:            cmn_s32_lhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -96,7 +96,7 @@ body:             |
 ...
 ---
 name:            no_cmn_s32_rhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -129,7 +129,7 @@ body:             |
 ...
 ---
 name:            no_cmn_s32_lhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -162,7 +162,7 @@ body:             |
 ...
 ---
 name:            cmn_s64_rhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -195,7 +195,7 @@ body:             |
 ...
 ---
 name:            cmn_s64_lhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -228,7 +228,7 @@ body:             |
 ...
 ---
 name:            no_cmn_s64_rhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -262,7 +262,7 @@ body:             |
 ...
 ---
 name:            no_cmn_s64_lhs
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -296,7 +296,7 @@ body:             |
 ...
 ---
 name:            tst_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -327,7 +327,7 @@ body:             |
 ...
 ---
 name:            tst_s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -359,7 +359,7 @@ body:             |
 ...
 ---
 name:            no_tst_unsigned_compare
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -391,7 +391,7 @@ body:             |
 ...
 ---
 name:            no_tst_nonzero
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -423,7 +423,7 @@ body:             |
 ...
 ---
 name:            imm_tst
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -455,7 +455,7 @@ body:             |
 ...
 ---
 name:            no_imm_tst_not_logical_imm
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -487,7 +487,7 @@ body:             |
 ...
 ---
 name:            test_physreg_copy
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir

@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -O1 -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            splat_4xi32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -27,7 +27,7 @@ body:             |
 ...
 ---
 name:            splat_2xi64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -52,7 +52,7 @@ body:             |
 ...
 ---
 name:            splat_4xf32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -79,7 +79,7 @@ body:             |
 ...
 ---
 name:            splat_2xf64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -106,7 +106,7 @@ body:             |
 ...
 ---
 name:            splat_2xf64_copies
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -137,7 +137,7 @@ body:             |
 ...
 ---
 name:            not_all_zeros
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir

@@ -10,7 +10,7 @@
 ...
 ---
 name:            test
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }

test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir

@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
 
 name:            v2s32_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 registers:
@@ -22,7 +22,7 @@ body:             |
 ...
 ---
 name:            v4s32_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 registers:
@@ -49,7 +49,7 @@ body:             |
 ...
 ---
 name:            v2s64_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 registers:
@@ -76,7 +76,7 @@ body:             |
 ...
 ---
 name:            v4s16_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 registers:

test/CodeGen/AArch64/GlobalISel/regbank-extract.mir

@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
 ---
 name:            extract_s64_s128
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |

test/CodeGen/AArch64/GlobalISel/regbank-fma.mir

@@ -5,7 +5,7 @@
 ---
 
 name:            fma_f32
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -31,7 +31,7 @@ body:             |
 ...
 ---
 name:            fma_f64
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}

test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir

@@ -13,7 +13,7 @@
 # 3) The fourth operand should be a GPR, since it's a constant.
 
 name:            v4s32_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
@@ -38,7 +38,7 @@ body:             |
 ...
 ---
 name:            v4s32_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
@@ -63,7 +63,7 @@ body:             |
 ...
 ---
 name:            v2s64_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
@@ -88,7 +88,7 @@ body:             |
 ...
 ---
 name:            v2s64_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
@@ -113,7 +113,7 @@ body:             |
 ...
 ---
 name:            v2s32_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
@@ -138,7 +138,7 @@ body:             |
 ...
 ---
 name:            v2s32_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |

test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir

@@ -6,7 +6,7 @@
 ...
 ---
 name:            test_f16.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -30,7 +30,7 @@ body:             |
 ...
 ---
 name:            test_f32.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -54,7 +54,7 @@ body:             |
 ...
 ---
 name:            test_f64.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -78,7 +78,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -102,7 +102,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -126,7 +126,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -150,7 +150,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -174,7 +174,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.round
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:

test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_f32.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -28,7 +28,7 @@ body:             |
 ...
 ---
 name:            test_f64.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:

test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_v4f16.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -26,7 +26,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -48,7 +48,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -70,7 +70,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -92,7 +92,7 @@ body:             |
 ...
 ---
 name:            test_f32.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -114,7 +114,7 @@ body:             |
 ...
 ---
 name:            test_f64.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -136,7 +136,7 @@ body:             |
 ...
 ---
 name:            test_f16.nearbyint
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}

test/CodeGen/AArch64/GlobalISel/regbank-select.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            select_f32
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -32,7 +32,7 @@ body:             |
 ...
 ---
 name:            select_f64
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -60,7 +60,7 @@ body:             |
 ...
 ---
 name:            two_fpr_inputs_gpr_output
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -94,7 +94,7 @@ body:             |
 ...
 ---
 name:            one_fpr_input_fpr_output
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -126,7 +126,7 @@ body:             |
 ...
 ---
 name:            one_fpr_input_gpr_output
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
@@ -158,7 +158,7 @@ body:             |
 ...
 ---
 name:            two_gpr_input_fpr_output
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}

test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir

@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
 ---
 name:            trunc_s64_s128
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |

test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir

@@ -2,7 +2,7 @@
 # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            build_vec_f16
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |

test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir

@@ -2,7 +2,7 @@
 # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            unmerge
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:
@@ -26,7 +26,7 @@ body:             |
 ...
 ---
 name:            unmerge_s128
-alignment:       2
+alignment:       4
 legalized:       true
 tracksRegLiveness: true
 frameInfo:

test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir

@@ -3,7 +3,7 @@
 
 ---
 name:            add_sext_s32_to_s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -27,7 +27,7 @@ body:             |
 ...
 ---
 name:            add_and_s32_to_s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -54,7 +54,7 @@ body:             |
 ...
 ---
 name:            add_sext_s16_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -79,7 +79,7 @@ body:             |
 ...
 ---
 name:            add_zext_s16_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -104,7 +104,7 @@ body:             |
 ...
 ---
 name:            add_anyext_s16_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -129,7 +129,7 @@ body:             |
 ...
 ---
 name:            add_and_s16_to_s32_uxtb
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -154,7 +154,7 @@ body:             |
 ...
 ---
 name:            add_and_s16_to_s32_uxth
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -179,7 +179,7 @@ body:             |
 ...
 ---
 name:            add_sext_s8_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -204,7 +204,7 @@ body:             |
 ...
 ---
 name:            add_zext_s8_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -229,7 +229,7 @@ body:             |
 ...
 ---
 name:            add_anyext_s8_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -254,7 +254,7 @@ body:             |
 ...
 ---
 name:            add_sext_with_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -281,7 +281,7 @@ body:             |
 ...
 ---
 name:            add_and_with_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -308,7 +308,7 @@ body:             |
 ...
 ---
 name:            dont_fold_invalid_mask
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -336,7 +336,7 @@ body:             |
 ...
 ---
 name:            dont_fold_invalid_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -364,7 +364,7 @@ body:             |
 ...
 ---
 name:            sub_sext_s32_to_s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -388,7 +388,7 @@ body:             |
 ...
 ---
 name:            sub_sext_s16_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -413,7 +413,7 @@ body:             |
 ...
 ---
 name:            sub_zext_s16_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -438,7 +438,7 @@ body:             |
 ...
 ---
 name:            sub_anyext_s16_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -463,7 +463,7 @@ body:             |
 ...
 ---
 name:            sub_and_s16_to_s32_uxtb
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -488,7 +488,7 @@ body:             |
 ...
 ---
 name:            sub_and_s16_to_s32_uxth
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -512,7 +512,7 @@ body:             |
     RET_ReallyLR implicit $w3
 ---
 name:            sub_sext_s8_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -530,7 +530,7 @@ body:             |
 ...
 ---
 name:            sub_zext_s8_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -555,7 +555,7 @@ body:             |
 ...
 ---
 name:            sub_anyext_s8_to_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -581,7 +581,7 @@ body:             |
 ...
 ---
 name:            sub_sext_with_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -608,7 +608,7 @@ body:             |
 ...
 ---
 name:            sub_and_with_shl
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir

@@ -12,7 +12,7 @@
 ...
 ---
 name:            load_acq_i8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-binop.mir

@@ -1072,7 +1072,7 @@ body:             |
 ...
 ---
 name:            add_v8i16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -1101,7 +1101,7 @@ body:             |
 ...
 ---
 name:            add_v16i8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir

@@ -20,7 +20,7 @@
 ...
 ---
 name:            test_blockaddress
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-bswap.mir

@@ -48,7 +48,7 @@ body:             |
 ...
 ---
 name:            bswap_v4s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -71,7 +71,7 @@ body:             |
 ...
 ---
 name:            bswap_v2s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -94,7 +94,7 @@ body:             |
 ...
 ---
 name:            bswap_v2s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-build-vector.mir

@@ -25,7 +25,7 @@
 ...
 ---
 name:            test_f32
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
@@ -66,7 +66,7 @@ body:             |
 ...
 ---
 name:            test_f64
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
@@ -97,7 +97,7 @@ body:             |
 ...
 ---
 name:            test_i32
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
@@ -132,7 +132,7 @@ body:             |
 ...
 ---
 name:            test_i64
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
@@ -161,7 +161,7 @@ body:             |
 ...
 ---
 name:            test_p0
-alignment:       2
+alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true

test/CodeGen/AArch64/GlobalISel/select-cbz.mir

@@ -119,7 +119,7 @@ body:             |
 ...
 ---
 name:            test_rhs_inttoptr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -156,7 +156,7 @@ body:             |
 ...
 ---
 name:            test_rhs_unknown
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir

@@ -3,7 +3,7 @@
 ...
 ---
 name:            legal_v4s32_v2s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -36,7 +36,7 @@ body:             |
 ...
 ---
 name:            legal_v8s16_v4s16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-ctlz.mir

@@ -2,7 +2,7 @@
 # RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
 
 name:            test_v8s8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -24,7 +24,7 @@ body:             |
 ...
 ---
 name:            test_v4s16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -46,7 +46,7 @@ body:             |
 ...
 ---
 name:            test_v2s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -68,7 +68,7 @@ body:             |
 ...
 ---
 name:            test_s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -92,7 +92,7 @@ body:             |
 ...
 ---
 name:            test_s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -115,7 +115,7 @@ body:             |
 ...
 ---
 name:            test_v16s8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -137,7 +137,7 @@ body:             |
 ...
 ---
 name:            test_v8s16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -159,7 +159,7 @@ body:             |
 ...
 ---
 name:            test_v4s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -181,7 +181,7 @@ body:             |
 ...
 ---
 name:            test_v2s64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir

@@ -3,7 +3,7 @@
 ...
 ---
 name:            v2s32_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -34,7 +34,7 @@ body:             |
 ...
 ---
 name:            v2s32_fpr_idx0
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -57,7 +57,7 @@ body:             |
 ...
 ---
 name:            v2s64_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -86,7 +86,7 @@ body:             |
 ...
 ---
 name:            v4s16_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -117,7 +117,7 @@ body:             |
 ...
 ---
 name:            v8s16_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -140,7 +140,7 @@ body:             |
 ...
 ---
 name:            v8s16_fpr_zext
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -164,7 +164,7 @@ body:             |
 ...
 ---
 name:            v8s16_fpr_sext
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -188,7 +188,7 @@ body:             |
 ...
 ---
 name:            v8s16_fpr_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-fcmp.mir

@@ -6,7 +6,7 @@
 ...
 ---
 name:            zero
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -31,7 +31,7 @@ body:             |
 ...
 ---
 name:            notzero
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_f16.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -31,7 +31,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -100,7 +100,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-frint.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_f16.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -27,7 +27,7 @@ body:             |
 ...
 ---
 name:            test_f32.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -50,7 +50,7 @@ body:             |
 ...
 ---
 name:            test_f64.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -73,7 +73,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -96,7 +96,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -119,7 +119,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -142,7 +142,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -165,7 +165,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.rint
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir

@@ -2,7 +2,7 @@
 # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
 
 name:            v4s32_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -29,7 +29,7 @@ body:             |
 ...
 ---
 name:            v4s32_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -54,7 +54,7 @@ body:             |
 ...
 ---
 name:            v2s64_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -81,7 +81,7 @@ body:             |
 ...
 ---
 name:            v2s64_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -106,7 +106,7 @@ body:             |
 ...
 ---
 name:            v2s32_fpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -136,7 +136,7 @@ body:             |
 ...
 ---
 name:            v2s32_gpr
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-int-ext.mir

@@ -75,7 +75,7 @@ body:             |
 
 ---
 name:            anyext_v8s16_from_v8s8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -101,7 +101,7 @@ body:             |
 
 ---
 name:            anyext_v4s32_from_v4s16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -127,7 +127,7 @@ body:             |
 
 ---
 name:            anyext_v2s64_from_v2s32
-alignment:       2
+alignment:       4
 tracksRegLiveness: true
 legalized:       true
 regBankSelected: true
@@ -248,7 +248,7 @@ body:             |
 
 ---
 name:            zext_v8s16_from_v8s8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -275,7 +275,7 @@ body:             |
 
 ---
 name:            zext_v4s32_from_v4s16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -301,7 +301,7 @@ body:             |
 
 ---
 name:            zext_v2s64_from_v2s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -422,7 +422,7 @@ body:             |
 
 ---
 name:            sext_v8s16_from_v8s8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -449,7 +449,7 @@ body:             |
 
 ---
 name:            sext_v4s32_from_v4s16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -475,7 +475,7 @@ body:             |
 
 ---
 name:            sext_v2s64_from_v2s32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_f64.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -27,7 +27,7 @@ body:             |
 ...
 ---
 name:            test_f32.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -50,7 +50,7 @@ body:             |
 ...
 ---
 name:            test_f16.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -75,7 +75,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -100,7 +100,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -150,7 +150,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -175,7 +175,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.intrinsic_round
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir

@@ -4,7 +4,7 @@
 ...
 ---
 name:            test_f64.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -27,7 +27,7 @@ body:             |
 ...
 ---
 name:            test_f32.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -50,7 +50,7 @@ body:             |
 ...
 ---
 name:            test_f16.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -75,7 +75,7 @@ body:             |
 ...
 ---
 name:            test_v4f16.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -100,7 +100,7 @@ body:             |
 ...
 ---
 name:            test_v8f16.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -125,7 +125,7 @@ body:             |
 ...
 ---
 name:            test_v2f32.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -150,7 +150,7 @@ body:             |
 ...
 ---
 name:            test_v4f32.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -175,7 +175,7 @@ body:             |
 ...
 ---
 name:            test_v2f64.intrinsic_trunc
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir

@@ -30,7 +30,7 @@
 ...
 ---
 name:            jt_test
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir

@@ -10,7 +10,7 @@
 ---
 
 name:            test_load_acquire_i8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -32,7 +32,7 @@ body:             |
 ...
 ---
 name:            test_load_acquire_i16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -54,7 +54,7 @@ body:             |
 ...
 ---
 name:            test_load_acquire_i32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -76,7 +76,7 @@ body:             |
 ...
 ---
 name:            test_load_acquire_i64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true

test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir

@@ -9,7 +9,7 @@
 ...
 ---
 name:            test_load_i8
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -31,7 +31,7 @@ body:             |
 ...
 ---
 name:            test_load_i16
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -53,7 +53,7 @@ body:             |
 ...
 ---
 name:            test_load_i32
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -76,7 +76,7 @@ body:             |
 ...
 ---
 name:            test_load_i64
-alignment:       2
+alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true