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Followup on Proposal to move MIR physical register namespace to '$' sigil.

Browse Source 
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
This commit is contained in:
Puyan Lotfi 2018-01-31 22:04:26 +00:00
parent ec143adab5
commit d4c615be8c
970 changed files with 29286 additions and 29277 deletions
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23
lib/CodeGen/MIRParser/MILexer.cpp
View File

@ -410,17 +410,26 @@ static bool isRegisterChar(char C) {
return isIdentifierChar(C) && C != '.';
}
static Cursor maybeLexRegister(Cursor C, MIToken &Token) {
if (C.peek() != '%')
static Cursor maybeLexRegister(Cursor C, MIToken &Token,
ErrorCallbackType ErrorCallback) {
if (C.peek() != '%' && C.peek() != '$')
return None;
if (isdigit(C.peek(1)))
return lexVirtualRegister(C, Token);
if (C.peek() == '%') {
if (isdigit(C.peek(1)))
return lexVirtualRegister(C, Token);
// ErrorCallback(Token.location(), "Named vregs are not yet supported.");
return None;
}
assert(C.peek() == '$');
auto Range = C;
C.advance(); // Skip '%'
C.advance(); // Skip '$'
while (isRegisterChar(C.peek()))
C.advance();
Token.reset(MIToken::NamedRegister, Range.upto(C))
.setStringValue(Range.upto(C).drop_front(1)); // Drop the '%'
.setStringValue(Range.upto(C).drop_front(1)); // Drop the '$'
return C;
}
@ -642,7 +651,7 @@ StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
return R.remaining();
if (Cursor R = maybeLexIRValue(C, Token, ErrorCallback))
return R.remaining();
if (Cursor R = maybeLexRegister(C, Token))
if (Cursor R = maybeLexRegister(C, Token, ErrorCallback))
return R.remaining();
if (Cursor R = maybeLexGlobalValue(C, Token, ErrorCallback))
return R.remaining();

6
lib/CodeGen/TargetRegisterInfo.cpp
View File

@ -89,15 +89,15 @@ Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
unsigned SubIdx) {
return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
if (!Reg)
OS << "%noreg";
OS << "$noreg";
else if (TargetRegisterInfo::isStackSlot(Reg))
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
else if (!TRI)
OS << '%' << "physreg" << Reg;
OS << '$' << "physreg" << Reg;
else if (Reg < TRI->getNumRegs()) {
OS << '%';
OS << '$';
printLowerCase(TRI->getName(Reg), OS);
} else
llvm_unreachable("Register kind is unsupported.");

6
test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
View File

@ -13,9 +13,9 @@ target triple = "aarch64-apple-ios9.0"
; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK: %w0 = COPY [[ANSWER]]
; CHECK: %d0 = COPY [[D_ONE]]
; CHECK: %x1 = COPY [[TWELVE]]
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $d0 = COPY [[D_ONE]]
; CHECK: $x1 = COPY [[TWELVE]]
; CHECK: G_STORE [[THREE]](s8), {{%[0-9]+}}(p0) :: (store 1 into stack, align 0)
; CHECK: G_STORE [[ONE]](s16), {{%[0-9]+}}(p0) :: (store 2 into stack + 8, align 0)
; CHECK: G_STORE [[FOUR]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 16, align 0)

74
test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
View File

@ -4,15 +4,15 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu"
; CHECK-LABEL: name: args_i32
; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY %w0
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w1
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w2
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w3
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w4
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w5
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w6
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w7
; CHECK: %w0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY $w0
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w1
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w2
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w3
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w4
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w5
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w6
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w7
; CHECK: $w0 = COPY %[[ARG0]]
define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
i32 %w4, i32 %w5, i32 %w6, i32 %w7) {
@ -20,15 +20,15 @@ define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
}
; CHECK-LABEL: name: args_i64
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %x0
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x1
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x2
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x3
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x4
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x5
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x6
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x7
; CHECK: %x0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY $x0
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x1
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x2
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x3
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x4
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x5
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x6
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x7
; CHECK: $x0 = COPY %[[ARG0]]
define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
ret i64 %x0
@ -36,23 +36,23 @@ define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
; CHECK-LABEL: name: args_ptrs
; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY %x0
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x1
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x2
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x3
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x4
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x5
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x6
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x7
; CHECK: %x0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY $x0
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x1
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x2
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x3
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x4
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x5
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x6
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x7
; CHECK: $x0 = COPY %[[ARG0]]
define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
[3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) {
ret i8* %x0
}
; CHECK-LABEL: name: args_arr
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %d0
; CHECK: %d0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY $d0
; CHECK: $d0 = COPY %[[ARG0]]
define [1 x double] @args_arr([1 x double] %d0) {
ret [1 x double] %d0
}
@ -67,16 +67,16 @@ define [1 x double] @args_arr([1 x double] %d0) {
; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK: %w0 = COPY [[ANSWER]]
; CHECK: %d0 = COPY [[D_ONE]]
; CHECK: %x1 = COPY [[TWELVE]]
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $d0 = COPY [[D_ONE]]
; CHECK: $x1 = COPY [[TWELVE]]
; CHECK: [[THREE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[THREE]]
; CHECK: %w2 = COPY [[THREE_TMP]](s32)
; CHECK: $w2 = COPY [[THREE_TMP]](s32)
; CHECK: [[ONE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[ONE]]
; CHECK: %w3 = COPY [[ONE_TMP]](s32)
; CHECK: %w4 = COPY [[FOUR]](s32)
; CHECK: %s1 = COPY [[F_ONE]](s32)
; CHECK: %d2 = COPY [[TWO]](s64)
; CHECK: $w3 = COPY [[ONE_TMP]](s32)
; CHECK: $w4 = COPY [[FOUR]](s32)
; CHECK: $s1 = COPY [[F_ONE]](s32)
; CHECK: $d2 = COPY [[TWO]](s64)
declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0)

554
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

File diff suppressed because it is too large Load Diff

286
test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
View File

@ -122,10 +122,10 @@ registers:
- { id: 1, class: _ }
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: defaultMapping
; CHECK: %1:gpr(s32) = G_ADD %0
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_ADD %0, %0
...
@ -140,11 +140,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0.entry:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: defaultMappingVector
; CHECK: %0:fpr(<2 x s32>) = COPY %d0
; CHECK: %0:fpr(<2 x s32>) = COPY $d0
; CHECK: %1:fpr(<2 x s32>) = G_ADD %0
%0(<2 x s32>) = COPY %d0
%0(<2 x s32>) = COPY $d0
%1(<2 x s32>) = G_ADD %0, %0
...
@ -160,14 +160,14 @@ registers:
- { id: 2, class: _ }
body: |
bb.0.entry:
liveins: %s0, %x0
liveins: $s0, $x0
; CHECK-LABEL: name: defaultMapping1Repair
; CHECK: %0:fpr(s32) = COPY %s0
; CHECK-NEXT: %1:gpr(s32) = COPY %w0
; CHECK: %0:fpr(s32) = COPY $s0
; CHECK-NEXT: %1:gpr(s32) = COPY $w0
; CHECK-NEXT: %3:gpr(s32) = COPY %0
; CHECK-NEXT: %2:gpr(s32) = G_ADD %3, %1
%0(s32) = COPY %s0
%1(s32) = COPY %w0
%0(s32) = COPY $s0
%1(s32) = COPY $w0
%2(s32) = G_ADD %0, %1
...
@ -179,13 +179,13 @@ registers:
- { id: 1, class: _ }
body: |
bb.0.entry:
liveins: %s0, %x0
liveins: $s0, $x0
; CHECK-LABEL: name: defaultMapping2Repairs
; CHECK: %0:fpr(s32) = COPY %s0
; CHECK: %0:fpr(s32) = COPY $s0
; CHECK-NEXT: %2:gpr(s32) = COPY %0
; CHECK-NEXT: %3:gpr(s32) = COPY %0
; CHECK-NEXT: %1:gpr(s32) = G_ADD %2, %3
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_ADD %0, %0
...
@ -201,12 +201,12 @@ registers:
- { id: 1, class: fpr }
body: |
bb.0.entry:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: defaultMappingDefRepair
; CHECK: %0:gpr(s32) = COPY %w0
; CHECK: %0:gpr(s32) = COPY $w0
; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %0
; CHECK-NEXT: %1:fpr(s32) = COPY %2
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_ADD %0, %0
...
@ -231,12 +231,12 @@ registers:
body: |
bb.0.entry:
successors: %bb.2.end, %bb.1.then
liveins: %x0, %x1, %w2
liveins: $x0, $x1, $w2
%0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src)
%0 = LDRWui killed $x0, 0 :: (load 4 from %ir.src)
%5(s32) = COPY %0
%1(p0) = COPY %x1
%2 = COPY %w2
%1(p0) = COPY $x1
%2 = COPY $w2
TBNZW killed %2, 0, %bb.2.end
bb.1.then:
@ -259,14 +259,14 @@ registers:
- { id: 2, class: _ }
body: |
bb.0.entry:
liveins: %w0, %s0
liveins: $w0, $s0
; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
; CHECK: %0:gpr(s32) = COPY %w0
; CHECK-NEXT: %1:fpr(s32) = COPY %s0
; CHECK: %0:gpr(s32) = COPY $w0
; CHECK-NEXT: %1:fpr(s32) = COPY $s0
; CHECK-NEXT: %3:gpr(s32) = COPY %1
; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %3
%0(s32) = COPY %w0
%1(s32) = COPY %s0
%0(s32) = COPY $w0
%1(s32) = COPY $s0
%2(s32) = G_ADD %0, %1
...
@ -279,14 +279,14 @@ registers:
- { id: 1, class: _ }
body: |
bb.0.entry:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: defaultMappingDefRepairPhysReg
; CHECK: %0:gpr(s32) = COPY %w0
; CHECK: %0:gpr(s32) = COPY $w0
; CHECK-NEXT: %1:gpr(s32) = G_ADD %0, %0
; CHECK-NEXT: %s0 = COPY %1
%0(s32) = COPY %w0
; CHECK-NEXT: $s0 = COPY %1
%0(s32) = COPY $w0
%1(s32) = G_ADD %0, %0
%s0 = COPY %1
$s0 = COPY %1
...
---
@ -300,9 +300,9 @@ registers:
- { id: 2, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1
; CHECK: %0:gpr(<2 x s32>) = COPY %x0
; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
liveins: $x0, $x1
; CHECK: %0:gpr(<2 x s32>) = COPY $x0
; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1
; Fast mode tries to reuse the source of the copy for the destination.
; Now, the default mapping says that %0 and %1 need to be in FPR.
@ -314,8 +314,8 @@ body: |
; Greedy mode remapped the instruction on the GPR bank.
; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1
%0(<2 x s32>) = COPY %x0
%1(<2 x s32>) = COPY %x1
%0(<2 x s32>) = COPY $x0
%1(<2 x s32>) = COPY $x1
%2(<2 x s32>) = G_OR %0, %1
...
@ -331,11 +331,11 @@ registers:
- { id: 2, class: fpr }
body: |
bb.0.entry:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: greedyMappingOrWithConstraints
; CHECK: %0:gpr(<2 x s32>) = COPY %x0
; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
; CHECK: %0:gpr(<2 x s32>) = COPY $x0
; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1
; Fast mode tries to reuse the source of the copy for the destination.
; Now, the default mapping says that %0 and %1 need to be in FPR.
@ -349,8 +349,8 @@ body: |
; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1
; We need to keep %2 into FPR because we do not know anything about it.
; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3
%0(<2 x s32>) = COPY %x0
%1(<2 x s32>) = COPY %x1
%0(<2 x s32>) = COPY $x0
%1(<2 x s32>) = COPY $x1
%2(<2 x s32>) = G_OR %0, %1
...
@ -366,17 +366,17 @@ registers:
- { id: 1, class: gpr64 }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK: %0:gpr64 = COPY %x0
; CHECK: %0:gpr64 = COPY $x0
; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0
; CHECK-NEXT: %x0 = COPY %1
; CHECK-NEXT: RET_ReallyLR implicit %x0
; CHECK-NEXT: $x0 = COPY %1
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0 = COPY %x0
%0 = COPY $x0
%1 = ADDXrr %0, %0
%x0 = COPY %1
RET_ReallyLR implicit %x0
$x0 = COPY %1
RET_ReallyLR implicit $x0
...
---
@ -404,13 +404,13 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s32) = COPY %w0
# CHECK: %0:gpr(s32) = COPY $w0
# CHECK: %1:gpr(s32) = G_BITCAST %0
body: |
bb.0:
liveins: %w0
liveins: $w0
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_BITCAST %0
...
@ -427,13 +427,13 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s16>) = COPY %s0
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
# CHECK: %1:fpr(<2 x s16>) = G_BITCAST %0
body: |
bb.0:
liveins: %s0
liveins: $s0
%0(<2 x s16>) = COPY %s0
%0(<2 x s16>) = COPY $s0
%1(<2 x s16>) = G_BITCAST %0
...
@ -451,14 +451,14 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s32) = COPY %w0
# CHECK: %0:gpr(s32) = COPY $w0
# FAST: %1:fpr(<2 x s16>) = G_BITCAST %0
# GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0
body: |
bb.0:
liveins: %w0
liveins: $w0
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(<2 x s16>) = G_BITCAST %0
...
@ -470,14 +470,14 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s16>) = COPY %s0
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
# FAST: %1:gpr(s32) = G_BITCAST %0
# GREEDY: %1:fpr(s32) = G_BITCAST %0
body: |
bb.0:
liveins: %s0
liveins: $s0
%0(<2 x s16>) = COPY %s0
%0(<2 x s16>) = COPY $s0
%1(s32) = G_BITCAST %0
...
@ -489,13 +489,13 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s64) = COPY %x0
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK: %1:gpr(s64) = G_BITCAST %0
body: |
bb.0:
liveins: %x0
liveins: $x0
%0(s64) = COPY %x0
%0(s64) = COPY $x0
%1(s64) = G_BITCAST %0
...
@ -507,13 +507,13 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s32>) = COPY %d0
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
# CHECK: %1:fpr(<2 x s32>) = G_BITCAST %0
body: |
bb.0:
liveins: %d0
liveins: $d0
%0(<2 x s32>) = COPY %d0
%0(<2 x s32>) = COPY $d0
%1(<2 x s32>) = G_BITCAST %0
...
@ -525,14 +525,14 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s64) = COPY %x0
# CHECK: %0:gpr(s64) = COPY $x0
# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
body: |
bb.0:
liveins: %x0
liveins: $x0
%0(s64) = COPY %x0
%0(s64) = COPY $x0
%1(<2 x s32>) = G_BITCAST %0
...
@ -544,14 +544,14 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s32>) = COPY %d0
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
# FAST: %1:gpr(s64) = G_BITCAST %0
# GREEDY: %1:fpr(s64) = G_BITCAST %0
body: |
bb.0:
liveins: %d0
liveins: $d0
%0(<2 x s32>) = COPY %d0
%0(<2 x s32>) = COPY $d0
%1(s64) = G_BITCAST %0
...
@ -569,13 +569,13 @@ registers:
# CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)
body: |
bb.1:
liveins: %x0, %x1
%0(s64) = COPY %x0
%1(s64) = COPY %x1
liveins: $x0, $x1
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
%2(<2 x s64>) = G_BITCAST %3(s128)
%q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit %q0
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
@ -598,14 +598,14 @@ registers:
# CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)
body: |
bb.1:
liveins: %x0, %x1
%0(s64) = COPY %x0
%1(s64) = COPY %x1
liveins: $x0, $x1
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
%4(s128) = COPY %3(s128)
%2(<2 x s64>) = G_BITCAST %4(s128)
%q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit %q0
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
@ -630,11 +630,11 @@ registers:
# CHECK: %1:fpr(s128) = COPY %0
body: |
bb.1:
liveins: %x0
%0 = LDRQui killed %x0, 0
liveins: $x0
%0 = LDRQui killed $x0, 0
%1(s128) = COPY %0
%q0 = COPY %1(s128)
RET_ReallyLR implicit %q0
$q0 = COPY %1(s128)
RET_ReallyLR implicit $q0
...
@ -654,15 +654,15 @@ registers:
# CHECK: registers:
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: %0:gpr(s32) = COPY %w0
# CHECK: %0:gpr(s32) = COPY $w0
# CHECK-NEXT: %1:gpr(s16) = G_TRUNC %0(s32)
body: |
bb.1:
liveins: %w0
%0(s32) = COPY %w0
liveins: $w0
%0(s32) = COPY $w0
%1(s16) = G_TRUNC %0(s32)
%h0 = COPY %1(s16)
RET_ReallyLR implicit %h0
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
@ -682,8 +682,8 @@ registers:
- { id: 4, class: _ }
- { id: 5, class: _ }
# No repairing should be necessary for both modes.
# CHECK: %0:gpr(s64) = COPY %x0
# CHECK-NEXT: %1:gpr(p0) = COPY %x1
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
# FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
# FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
# FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3
@ -691,20 +691,20 @@ registers:
# GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
# GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3
# CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
# CHECK-NEXT: %x0 = COPY %5(s64)
# CHECK-NEXT: RET_ReallyLR implicit %x0
# CHECK-NEXT: $x0 = COPY %5(s64)
# CHECK-NEXT: RET_ReallyLR implicit $x0
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
%0(s64) = COPY %x0
%1(p0) = COPY %x1
%0(s64) = COPY $x0
%1(p0) = COPY $x1
%2(<2 x s32>) = G_BITCAST %0(s64)
%3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
%4(<2 x s32>) = G_OR %2, %3
%5(s64) = G_BITCAST %4(<2 x s32>)
%x0 = COPY %5(s64)
RET_ReallyLR implicit %x0
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
@ -728,25 +728,25 @@ registers:
- { id: 3, class: _ }
# No repairing should be necessary for both modes.
# CHECK: %0:gpr(s64) = COPY %x0
# CHECK-NEXT: %1:gpr(p0) = COPY %x1
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
# CHECK-NEXT: %2:fpr(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
# %0 has been mapped to GPR, we need to repair to match FPR.
# CHECK-NEXT: %4:fpr(s64) = COPY %0
# CHECK-NEXT: %3:fpr(s64) = G_FADD %4, %2
# CHECK-NEXT: %x0 = COPY %3(s64)
# CHECK-NEXT: RET_ReallyLR implicit %x0
# CHECK-NEXT: $x0 = COPY %3(s64)
# CHECK-NEXT: RET_ReallyLR implicit $x0
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
%0(s64) = COPY %x0
%1(p0) = COPY %x1
%0(s64) = COPY $x0
%1(p0) = COPY $x1
%2(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
%3(s64) = G_FADD %0, %2
%x0 = COPY %3(s64)
RET_ReallyLR implicit %x0
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
@ -768,8 +768,8 @@ registers:
- { id: 1, class: _ }
- { id: 2, class: _ }
# CHECK: %0:gpr(s64) = COPY %x0
# CHECK-NEXT: %1:gpr(p0) = COPY %x1
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
# %0 has been mapped to GPR, we need to repair to match FPR.
# CHECK-NEXT: %3:fpr(s64) = COPY %0
# CHECK-NEXT: %4:fpr(s64) = COPY %0
@ -779,10 +779,10 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
%0(s64) = COPY %x0
%1(p0) = COPY %x1
%0(s64) = COPY $x0
%1(p0) = COPY $x1
%2(s64) = G_FADD %0, %0
G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
RET_ReallyLR
@ -804,23 +804,23 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# CHECK: %1:gpr(s32) = COPY %w0
# CHECK: %1:gpr(s32) = COPY $w0
# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
# %0 has been mapped to GPR, we need to repair to match FPR.
# CHECK-NEXT: %3:fpr(s16) = COPY %0
# CHECK-NEXT: %2:fpr(s32) = G_FPEXT %3
# CHECK-NEXT: %s0 = COPY %2
# CHECK-NEXT: $s0 = COPY %2
# CHECK-NEXT: RET_ReallyLR
body: |
bb.1:
liveins: %w0
liveins: $w0
%1(s32) = COPY %w0
%1(s32) = COPY $w0
%0(s16) = G_TRUNC %1(s32)
%2(s32) = G_FPEXT %0(s16)
%s0 = COPY %2(s32)
RET_ReallyLR implicit %s0
$s0 = COPY %2(s32)
RET_ReallyLR implicit $s0
...
@ -839,23 +839,23 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# CHECK: %1:gpr(s32) = COPY %w0
# CHECK: %1:gpr(s32) = COPY $w0
# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
# %0 has been mapped to GPR, we need to repair to match FPR.
# CHECK-NEXT: %3:fpr(s16) = COPY %0
# CHECK-NEXT: %2:fpr(s64) = G_FPEXT %3
# CHECK-NEXT: %d0 = COPY %2
# CHECK-NEXT: $d0 = COPY %2
# CHECK-NEXT: RET_ReallyLR
body: |
bb.1:
liveins: %w0
liveins: $w0
%1(s32) = COPY %w0
%1(s32) = COPY $w0
%0(s16) = G_TRUNC %1(s32)
%2(s64) = G_FPEXT %0(s16)
%d0 = COPY %2(s64)
RET_ReallyLR implicit %d0
$d0 = COPY %2(s64)
RET_ReallyLR implicit $d0
...
@ -872,20 +872,20 @@ legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0:gpr(s32) = COPY %w0
# CHECK: %0:gpr(s32) = COPY $w0
# %0 has been mapped to GPR, we need to repair to match FPR.
# CHECK-NEXT: %2:fpr(s32) = COPY %0
# CHECK-NEXT: %1:fpr(s64) = G_FPEXT %2
# CHECK-NEXT: %d0 = COPY %1
# CHECK-NEXT: $d0 = COPY %1
# CHECK-NEXT: RET_ReallyLR
body: |
bb.1:
liveins: %w0
liveins: $w0
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s64) = G_FPEXT %0(s32)
%d0 = COPY %1(s64)
RET_ReallyLR implicit %d0
$d0 = COPY %1(s64)
RET_ReallyLR implicit $d0
...
@ -894,8 +894,8 @@ body: |
# CHECK-LABEL: name: passFp16
# CHECK: registers:
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: %0:fpr(s16) = COPY %h0
# CHECK-NEXT: %h0 = COPY %0(s16)
# CHECK: %0:fpr(s16) = COPY $h0
# CHECK-NEXT: $h0 = COPY %0(s16)
name: passFp16
alignment: 2
legalized: true
@ -903,11 +903,11 @@ registers:
- { id: 0, class: _ }
body: |
bb.1.entry:
liveins: %h0
liveins: $h0
%0(s16) = COPY %h0
%h0 = COPY %0(s16)
RET_ReallyLR implicit %h0
%0(s16) = COPY $h0
$h0 = COPY %0(s16)
RET_ReallyLR implicit $h0
...
---
@ -919,7 +919,7 @@ body: |
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: - { id: 2, class: fpr, preferred-register: '' }
#
# CHECK: %0:fpr(s16) = COPY %h0
# CHECK: %0:fpr(s16) = COPY $h0
# CHECK-NEXT: %1:gpr(p0) = G_FRAME_INDEX %stack.0.p.addr
# If we didn't look through the copy for %0, the default mapping
# would have been on GPR and we would have to insert a copy to move
@ -929,7 +929,7 @@ body: |
# would have been on GPR and we would have to insert a copy to move
# the value to FPR (h0).
# CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
# CHECK-NEXT: %h0 = COPY %2(s16)
# CHECK-NEXT: $h0 = COPY %2(s16)
name: passFp16ViaAllocas
alignment: 2
legalized: true
@ -944,13 +944,13 @@ stack:
- { id: 0, name: p.addr, size: 2, alignment: 2, stack-id: 0 }
body: |
bb.1.entry:
liveins: %h0
liveins: $h0
%0(s16) = COPY %h0
%0(s16) = COPY $h0
%1(p0) = G_FRAME_INDEX %stack.0.p.addr
G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr)
%2(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
%h0 = COPY %2(s16)
RET_ReallyLR implicit %h0
$h0 = COPY %2(s16)
RET_ReallyLR implicit $h0
...

22
test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
View File

@ -11,7 +11,7 @@
; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]]
; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8)
; CHECK: %w0 = COPY [[SUM32]](s32)
; CHECK: $w0 = COPY [[SUM32]](s32)
define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
%sum = add i8 %lhs, %rhs
ret i8 %sum
@ -20,11 +20,11 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
; CHECK-LABEL: name: test_call_stack
; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0)
@ -35,9 +35,9 @@ define void @test_call_stack() {
}
; CHECK-LABEL: name: test_128bit_struct
; CHECK: %x0 = COPY
; CHECK: %x1 = COPY
; CHECK: %x2 = COPY
; CHECK: $x0 = COPY
; CHECK: $x1 = COPY
; CHECK: $x2 = COPY
; CHECK: BL @take_128bit_struct
define void @test_128bit_struct([2 x i64]* %ptr) {
%struct = load [2 x i64], [2 x i64]* %ptr
@ -46,9 +46,9 @@ define void @test_128bit_struct([2 x i64]* %ptr) {
}
; CHECK-LABEL: name: take_128bit_struct
; CHECK: {{%.*}}:_(p0) = COPY %x0
; CHECK: {{%.*}}:_(s64) = COPY %x1
; CHECK: {{%.*}}:_(s64) = COPY %x2
; CHECK: {{%.*}}:_(p0) = COPY $x0
; CHECK: {{%.*}}:_(s64) = COPY $x1
; CHECK: {{%.*}}:_(s64) = COPY $x2
define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
store [2 x i64] %in, [2 x i64]* %ptr
ret void
@ -59,12 +59,12 @@ define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)

114
test/CodeGen/AArch64/GlobalISel/call-translator.ll
View File

@ -1,9 +1,9 @@
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_trivial_call
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def %lr
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def $lr
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
declare void @trivial_callee()
define void @test_trivial_call() {
call void @trivial_callee()
@ -11,10 +11,10 @@ define void @test_trivial_call() {
}
; CHECK-LABEL: name: test_simple_return
; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit-def %x0
; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: %x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit %x0
; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
declare i64 @simple_return_callee()
define i64 @test_simple_return() {
%res = call i64 @simple_return_callee()
@ -22,9 +22,9 @@ define i64 @test_simple_return() {
}
; CHECK-LABEL: name: test_simple_arg
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: %w0 = COPY [[IN]]
; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: $w0 = COPY [[IN]]
; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: RET_ReallyLR
declare void @simple_arg_callee(i32 %in)
define void @test_simple_arg(i32 %in) {
@ -36,8 +36,8 @@ define void @test_simple_arg(i32 %in) {
; CHECK: registers:
; Make sure the register feeding the indirect call is properly constrained.
; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
; CHECK: %[[FUNC]]:gpr64(p0) = COPY %x0
; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
; CHECK: %[[FUNC]]:gpr64(p0) = COPY $x0
; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK: RET_ReallyLR
define void @test_indirect_call(void()* %func) {
call void %func()
@ -45,11 +45,11 @@ define void @test_indirect_call(void()* %func) {
}
; CHECK-LABEL: name: test_multiple_args
; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: %w0 = COPY [[ANSWER]]
; CHECK: %x1 = COPY [[IN]]
; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit %x1
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $x1 = COPY [[IN]]
; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
; CHECK: RET_ReallyLR
declare void @multiple_args_callee(i32, i64)
define void @test_multiple_args(i64 %in) {
@ -59,11 +59,11 @@ define void @test_multiple_args(i64 %in) {
; CHECK-LABEL: name: test_struct_formal
; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY %d0
; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY %w1
; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
; CHECK: [[UNDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
; CHECK: [[ARG0:%[0-9]+]]:_(s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
@ -80,17 +80,17 @@ define void @test_struct_formal({double, i64, i8} %in, {double, i64, i8}* %addr)
; CHECK-LABEL: name: test_struct_return
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[VAL:%[0-9]+]]:_(s192) = G_LOAD [[ADDR]](p0)
; CHECK: [[DBL:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 0
; CHECK: [[I64:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 64
; CHECK: [[I32:%[0-9]+]]:_(s32) = G_EXTRACT [[VAL]](s192), 128
; CHECK: %d0 = COPY [[DBL]](s64)
; CHECK: %x0 = COPY [[I64]](s64)
; CHECK: %w1 = COPY [[I32]](s32)
; CHECK: RET_ReallyLR implicit %d0, implicit %x0, implicit %w1
; CHECK: $d0 = COPY [[DBL]](s64)
; CHECK: $x0 = COPY [[I64]](s64)
; CHECK: $w1 = COPY [[I32]](s32)
; CHECK: RET_ReallyLR implicit $d0, implicit $x0, implicit $w1
define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) {
%val = load {double, i64, i32}, {double, i64, i32}* %addr
ret {double, i64, i32} %val
@ -105,15 +105,15 @@ define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) {
; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128
; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192
; CHECK: %x0 = COPY [[E0]](s64)
; CHECK: %x1 = COPY [[E1]](s64)
; CHECK: %x2 = COPY [[E2]](s64)
; CHECK: %x3 = COPY [[E3]](s64)
; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2, implicit %x3, implicit-def %x0, implicit-def %x1, implicit-def %x2, implicit-def %x3
; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY %x2
; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY %x3
; CHECK: $x0 = COPY [[E0]](s64)
; CHECK: $x1 = COPY [[E1]](s64)
; CHECK: $x2 = COPY [[E2]](s64)
; CHECK: $x3 = COPY [[E3]](s64)
; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3
; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[RES:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
; CHECK: G_EXTRACT [[RES]](s256), 64
declare [4 x i64] @arr_callee([4 x i64])
@ -128,14 +128,14 @@ define i64 @test_arr_call([4 x i64]* %addr) {
; CHECK-LABEL: name: test_abi_exts_call
; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
; CHECK: %w0 = COPY [[VAL_TMP]]
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
; CHECK: $w0 = COPY [[VAL_TMP]]
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
; CHECK: %w0 = COPY [[SVAL]](s32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
; CHECK: $w0 = COPY [[SVAL]](s32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
; CHECK: %w0 = COPY [[ZVAL]](s32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
; CHECK: $w0 = COPY [[ZVAL]](s32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
declare void @take_char(i8)
define void @test_abi_exts_call(i8* %addr) {
%val = load i8, i8* %addr
@ -148,8 +148,8 @@ define void @test_abi_exts_call(i8* %addr) {
; CHECK-LABEL: name: test_abi_sext_ret
; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
; CHECK: %w0 = COPY [[SVAL]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[SVAL]](s32)
; CHECK: RET_ReallyLR implicit $w0
define signext i8 @test_abi_sext_ret(i8* %addr) {
%val = load i8, i8* %addr
ret i8 %val
@ -158,8 +158,8 @@ define signext i8 @test_abi_sext_ret(i8* %addr) {
; CHECK-LABEL: name: test_abi_zext_ret
; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
; CHECK: %w0 = COPY [[SVAL]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[SVAL]](s32)
; CHECK: RET_ReallyLR implicit $w0
define zeroext i8 @test_abi_zext_ret(i8* %addr) {
%val = load i8, i8* %addr
ret i8 %val
@ -188,21 +188,21 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0)
; CHECK: BL @test_stack_slots
; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp
; CHECK: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
define void @test_call_stack() {
call void @test_stack_slots([8 x i64] undef, i64 42, i64 12, i64* null)
ret void
@ -219,9 +219,9 @@ define void @test_mem_i1([8 x i64], i1 %in) {
}
; CHECK-LABEL: name: test_128bit_struct
; CHECK: %x0 = COPY
; CHECK: %x1 = COPY
; CHECK: %x2 = COPY
; CHECK: $x0 = COPY
; CHECK: $x1 = COPY
; CHECK: $x2 = COPY
; CHECK: BL @take_128bit_struct
define void @test_128bit_struct([2 x i64]* %ptr) {
%struct = load [2 x i64], [2 x i64]* %ptr
@ -230,9 +230,9 @@ define void @test_128bit_struct([2 x i64]* %ptr) {
}
; CHECK-LABEL: name: take_128bit_struct
; CHECK: {{%.*}}:_(p0) = COPY %x0
; CHECK: {{%.*}}:_(s64) = COPY %x1
; CHECK: {{%.*}}:_(s64) = COPY %x2
; CHECK: {{%.*}}:_(p0) = COPY $x0
; CHECK: {{%.*}}:_(s64) = COPY $x1
; CHECK: {{%.*}}:_(s64) = COPY $x2
define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
store [2 x i64] %in, [2 x i64]* %ptr
ret void
@ -243,12 +243,12 @@ define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)

12
test/CodeGen/AArch64/GlobalISel/debug-insts.ll
View File

@ -6,7 +6,7 @@
; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12
; CHECK: DBG_VALUE debug-use %0(s32), debug-use $noreg, !11, !DIExpression(), debug-location !12
define void @debug_declare(i32 %in) #0 !dbg !7 {
entry:
%in.addr = alloca i32, align 4
@ -17,7 +17,7 @@ entry:
}
; CHECK-LABEL: name: debug_declare_vla
; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15
; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use $noreg, !14, !DIExpression(), debug-location !15
define void @debug_declare_vla(i32 %in) #0 !dbg !13 {
entry:
%vla.addr = alloca i32, i32 %in
@ -26,19 +26,19 @@ entry:
}
; CHECK-LABEL: name: debug_value
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
define void @debug_value(i32 %in) #0 !dbg !16 {
%addr = alloca i32
; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18
; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use $noreg, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
store i32 %in, i32* %addr
; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
; CHECK: DBG_VALUE debug-use %1(p0), debug-use $noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18
; CHECK: DBG_VALUE $noreg, 0, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
ret void
}

24
test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
View File

@ -1,47 +1,47 @@
; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
; CHECK-LABEL: name: test_simple_alloca
; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 4
; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
; CHECK: $sp = COPY [[ALIGNED_ALLOC]]
; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
; CHECK: %x0 = COPY [[ALLOC]]
; CHECK: $x0 = COPY [[ALLOC]]
define i8* @test_simple_alloca(i32 %numelts) {
%addr = alloca i8, i32 %numelts
ret i8* %addr
}
; CHECK-LABEL: name: test_aligned_alloca
; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 5
; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
; CHECK: $sp = COPY [[ALIGNED_ALLOC]]
; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
; CHECK: %x0 = COPY [[ALLOC]]
; CHECK: $x0 = COPY [[ALLOC]]
define i8* @test_aligned_alloca(i32 %numelts) {
%addr = alloca i8, i32 %numelts, align 32
ret i8* %addr
}
; CHECK-LABEL: name: test_natural_alloca
; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
; CHECK: %sp = COPY [[ALLOC]]
; CHECK: $sp = COPY [[ALLOC]]
; CHECK: [[ALLOC_TMP:%[0-9]+]]:_(p0) = COPY [[ALLOC]]
; CHECK: %x0 = COPY [[ALLOC_TMP]]
; CHECK: $x0 = COPY [[ALLOC_TMP]]
define i128* @test_natural_alloca(i32 %numelts) {
%addr = alloca i128, i32 %numelts
ret i128* %addr

8
test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
View File

@ -28,17 +28,17 @@ stack:
di-variable: '', di-expression: '', di-location: '' }
body: |
bb.1.entry:
liveins: %q0
liveins: $q0
; This test just checks we don't crash on G_FNEG of FP128 types. Expect to fall
; back until support is added for fp128.
; CHECK: ret
%0:_(s128) = COPY %q0
%0:_(s128) = COPY $q0
%1:_(p0) = G_FRAME_INDEX %stack.0.a.addr
G_STORE %0(s128), %1(p0) :: (store 16 into %ir.a.addr)
%2:_(s128) = G_LOAD %1(p0) :: (load 16 from %ir.a.addr)
%3:_(s128) = G_FNEG %2
%q0 = COPY %3(s128)
RET_ReallyLR implicit %q0
$q0 = COPY %3(s128)
RET_ReallyLR implicit $q0
...

2
test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
View File

@ -24,7 +24,7 @@ define i32 @test_bitcast_invalid_vreg() {
; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
; CHECK: %46:_(s32) = G_CONSTANT i32 100
; CHECK: %w0 = COPY %46(s32)
; CHECK: $w0 = COPY %46(s32)
%res = bitcast i32 100 to i32
ret i32 %res
}

22
test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
View File

@ -11,24 +11,24 @@ declare i32 @llvm.eh.typeid.for(i8*)
; CHECK-NEXT: bb.1 (%ir-block.0):
; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
; CHECK: EH_LABEL
; CHECK: %w0 = COPY
; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
; CHECK: {{%[0-9]+}}:_(s32) = COPY %w0
; CHECK: $w0 = COPY
; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK: {{%[0-9]+}}:_(s32) = COPY $w0
; CHECK: EH_LABEL
; CHECK: G_BR %[[GOOD]]
; CHECK: [[BAD]].{{[a-z]+}} (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[VAL_WITH_PTR:%[0-9]+]]:_(s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
; CHECK: [[PTR_SEL:%[0-9]+]]:_(s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
; CHECK: [[PTR_RET:%[0-9]+]]:_(s64) = G_EXTRACT [[PTR_SEL]](s128), 0
; CHECK: [[SEL_RET:%[0-9]+]]:_(s32) = G_EXTRACT [[PTR_SEL]](s128), 64
; CHECK: %x0 = COPY [[PTR_RET]]
; CHECK: %w1 = COPY [[SEL_RET]]
; CHECK: $x0 = COPY [[PTR_RET]]
; CHECK: $w1 = COPY [[SEL_RET]]
; CHECK: [[GOOD]].{{[a-z]+}}:
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@ -49,7 +49,7 @@ continue:
}
; CHECK-LABEL: name: test_invoke_indirect
; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY %x0
; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY $x0
; CHECK: BLR [[CALLEE]]
define void @test_invoke_indirect(void()* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
invoke void %callee() to label %continue unwind label %broken
@ -68,14 +68,14 @@ continue:
; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.0
; CHECK: %x0 = COPY [[NULL]]
; CHECK: $x0 = COPY [[NULL]]
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
; CHECK: G_STORE [[ANSWER]](s32), [[SLOT]]
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
; CHECK: G_STORE [[ONE]](s32), [[SLOT]]

110
test/CodeGen/AArch64/GlobalISel/legalize-add.mir
View File

@ -30,29 +30,29 @@
name: test_scalar_add_big
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_add_big
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
; CHECK: %x0 = COPY [[UADDE]](s64)
; CHECK: %x1 = COPY [[UADDE2]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s64) = COPY %x2
%3:_(s64) = COPY %x3
; CHECK: $x0 = COPY [[UADDE]](s64)
; CHECK: $x1 = COPY [[UADDE2]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = COPY $x3
%4:_(s128) = G_MERGE_VALUES %0, %1
%5:_(s128) = G_MERGE_VALUES %2, %3
%6:_(s128) = G_ADD %4, %5
%7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
%x0 = COPY %7
%x1 = COPY %8
$x0 = COPY %7
$x1 = COPY %8
...
---
@ -70,7 +70,7 @@ registers:
- { id: 9, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_add_big_nonpow2
; CHECK-NOT: G_MERGE_VALUES
; CHECK-NOT: G_UNMERGE_VALUES
@ -81,71 +81,71 @@ body: |
; CHECK: [[RES_HI:%[0-9]+]]:_(s64), {{%.*}}(s1) = G_UADDE %2, %3, [[CARRY2]]
; CHECK-NOT: G_MERGE_VALUES
; CHECK-NOT: G_UNMERGE_VALUES
; CHECK: %x0 = COPY [[RES_LO]]
; CHECK: %x1 = COPY [[RES_MI]]
; CHECK: %x2 = COPY [[RES_HI]]
; CHECK: $x0 = COPY [[RES_LO]]
; CHECK: $x1 = COPY [[RES_MI]]
; CHECK: $x2 = COPY [[RES_HI]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s64) = COPY %x2
%3(s64) = COPY %x3
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = COPY $x2
%3(s64) = COPY $x3
%4(s192) = G_MERGE_VALUES %0, %1, %2
%5(s192) = G_MERGE_VALUES %1, %2, %3
%6(s192) = G_ADD %4, %5
%7(s64), %8(s64), %9(s64) = G_UNMERGE_VALUES %6
%x0 = COPY %7
%x1 = COPY %8
%x2 = COPY %9
$x0 = COPY %7
$x1 = COPY %8
$x2 = COPY %9
...
---
name: test_scalar_add_small
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_add_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1
%4:_(s8) = G_ADD %2, %3
%5:_(s64) = G_ANYEXT %4
%x0 = COPY %5
$x0 = COPY %5
...
---
name: test_vector_add
body: |
bb.0.entry:
liveins: %q0, %q1, %q2, %q3
liveins: $q0, $q1, $q2, $q3
; CHECK-LABEL: name: test_vector_add
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY %q0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY %q1
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY %q2
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY %q3
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
%0:_(<2 x s64>) = COPY %q0
%1:_(<2 x s64>) = COPY %q1
%2:_(<2 x s64>) = COPY %q2
%3:_(<2 x s64>) = COPY %q3
; CHECK: $q0 = COPY [[ADD]](<2 x s64>)
; CHECK: $q1 = COPY [[ADD1]](<2 x s64>)
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
%3:_(<2 x s64>) = COPY $q3
%4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
%5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
%6:_(<4 x s64>) = G_ADD %4, %5
%7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
%q0 = COPY %7
%q1 = COPY %8
$q0 = COPY %7
$q1 = COPY %8
...
---
name: test_vector_add_nonpow2
@ -162,7 +162,7 @@ registers:
- { id: 9, class: _ }
body: |
bb.0.entry:
liveins: %q0, %q1, %q2, %q3
liveins: $q0, $q1, $q2, $q3
; CHECK-LABEL: name: test_vector_add_nonpow2
; CHECK-NOT: G_EXTRACT
; CHECK-NOT: G_SEQUENCE
@ -171,19 +171,19 @@ body: |
; CHECK: [[RES_HI:%[0-9]+]]:_(<2 x s64>) = G_ADD %2, %3
; CHECK-NOT: G_EXTRACT
; CHECK-NOT: G_SEQUENCE
; CHECK: %q0 = COPY [[RES_LO]]
; CHECK: %q1 = COPY [[RES_MI]]
; CHECK: %q2 = COPY [[RES_HI]]
; CHECK: $q0 = COPY [[RES_LO]]
; CHECK: $q1 = COPY [[RES_MI]]
; CHECK: $q2 = COPY [[RES_HI]]
%0(<2 x s64>) = COPY %q0
%1(<2 x s64>) = COPY %q1
%2(<2 x s64>) = COPY %q2
%3(<2 x s64>) = COPY %q3
%0(<2 x s64>) = COPY $q0
%1(<2 x s64>) = COPY $q1
%2(<2 x s64>) = COPY $q2
%3(<2 x s64>) = COPY $q3
%4(<6 x s64>) = G_MERGE_VALUES %0, %1, %2
%5(<6 x s64>) = G_MERGE_VALUES %1, %2, %3
%6(<6 x s64>) = G_ADD %4, %5
%7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>) = G_UNMERGE_VALUES %6
%q0 = COPY %7
%q1 = COPY %8
%q2 = COPY %9
$q0 = COPY %7
$q1 = COPY %8
$q2 = COPY %9
...

18
test/CodeGen/AArch64/GlobalISel/legalize-and.mir
View File

@ -22,25 +22,25 @@ registers:
- { id: 6, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_and_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: %x0 = COPY [[COPY3]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[COPY3]](s64)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_AND %2, %3
%6(s32) = G_ANYEXT %4
%w0 = COPY %6
$w0 = COPY %6
%5(s64) = G_ANYEXT %2
%x0 = COPY %5
$x0 = COPY %5
...

40
test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
View File

@ -14,72 +14,72 @@
name: cmpxchg_i8
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i8
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[CST2:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 1 on %ir.addr)
; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
; CHECK: %w0 = COPY [[RES2]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES2]]
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 1 on %ir.addr)
%3:_(s32) = G_ANYEXT %2
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
...
---
name: cmpxchg_i16
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i16
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 2 on %ir.addr)
; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
; CHECK: %w0 = COPY [[RES2]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES2]]
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 1
%2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 2 on %ir.addr)
%3:_(s32) = G_ANYEXT %2
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
...
---
name: cmpxchg_i32
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 4 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 4 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
name: cmpxchg_i64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 8 on %ir.addr)
; CHECK: %x0 = COPY [[RES]]
%0:_(p0) = COPY %x0
; CHECK: $x0 = COPY [[RES]]
%0:_(p0) = COPY $x0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...

22
test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
View File

@ -30,13 +30,13 @@ registers:
- { id: 14, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
@ -45,27 +45,27 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; CHECK: %w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; CHECK: %w0 = COPY [[COPY4]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x0
; CHECK: $w0 = COPY [[COPY4]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x0
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s1) = G_ICMP intpred(sge), %0, %1
%11(s32) = G_ANYEXT %4
%w0 = COPY %11
$w0 = COPY %11
%8(s1) = G_ICMP intpred(ult), %2, %3
%12(s32) = G_ANYEXT %8
%w0 = COPY %12
$w0 = COPY %12
%9(p0) = G_INTTOPTR %0(s64)
%10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
%14(s32) = G_ANYEXT %10
%w0 = COPY %14
$w0 = COPY %14
...

20
test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
View File

@ -13,24 +13,24 @@ name: cmpxchg_i32
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s32), [[CMP]]
; CHECK: [[SRES32:%[0-9]+]]:_(s32) = COPY [[SRES]]
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[RES]], [[SRES32]]
; CHECK: %w0 = COPY [[MUL]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[MUL]]
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_CONSTANT i32 1
%3:_(s32), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
%5:_(s32) = G_ANYEXT %4
%6:_(s32) = G_MUL %3, %5
%w0 = COPY %6(s32)
$w0 = COPY %6(s32)
...
---
@ -38,22 +38,22 @@ name: cmpxchg_i64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s64), [[CMP]]
; CHECK: [[SRES64:%[0-9]+]]:_(s64) = G_ANYEXT [[SRES]]
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[RES]], [[SRES64]]
; CHECK: %x0 = COPY [[MUL]]
%0:_(p0) = COPY %x0
; CHECK: $x0 = COPY [[MUL]]
%0:_(p0) = COPY $x0
%1:_(s64) = G_CONSTANT i64 0
%2:_(s64) = G_CONSTANT i64 1
%3:_(s64), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
%5:_(s64) = G_ANYEXT %4
%6:_(s64) = G_MUL %3, %5
%x0 = COPY %6(s64)
$x0 = COPY %6(s64)
...

40
test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
View File

@ -14,82 +14,82 @@
name: cmpxchg_i8
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i8
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[CMPT:%[0-9]+]]:_(s8) = G_TRUNC [[CMP]]
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[CSTT:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 1 on %ir.addr)
; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s8)
; CHECK: %w0 = COPY [[RES2]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES2]]
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 0
%2:_(s8) = G_CONSTANT i8 1
%3:_(s8) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 1 on %ir.addr)
%4:_(s32) = G_ANYEXT %3
%w0 = COPY %4(s32)
$w0 = COPY %4(s32)
...
---
name: cmpxchg_i16
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i16
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[CMPT:%[0-9]+]]:_(s16) = G_TRUNC [[CMP]]
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[CSTT:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 2 on %ir.addr)
; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s16)
; CHECK: %w0 = COPY [[RES2]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES2]]
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 0
%2:_(s16) = G_CONSTANT i16 1
%3:_(s16) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 2 on %ir.addr)
%4:_(s32) = G_ANYEXT %3
%w0 = COPY %4(s32)
$w0 = COPY %4(s32)
...
---
name: cmpxchg_i32
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 4 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:_(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_CONSTANT i32 1
%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 4 on %ir.addr)
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
...
---
name: cmpxchg_i64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
; CHECK: %x0 = COPY [[RES]]
%0:_(p0) = COPY %x0
; CHECK: $x0 = COPY [[RES]]
%0:_(p0) = COPY $x0
%1:_(s64) = G_CONSTANT i64 0
%2:_(s64) = G_CONSTANT i64 1
%3:_(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
%x0 = COPY %3(s64)
$x0 = COPY %3(s64)
...

34
test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
View File

@ -14,78 +14,78 @@
name: test_combines_2
body: |
bb.0:
liveins: %w0
liveins: $w0
; Here the types don't match.
; CHECK-LABEL: name: test_combines_2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[MV]](s64), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s64), 0
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s1) = G_EXTRACT %2, 0
%5:_(s32) = G_ANYEXT %3
%w0 = COPY %5
$w0 = COPY %5
%4:_(s64) = G_EXTRACT %2, 0
%x0 = COPY %4
$x0 = COPY %4
...
---
name: test_combines_3
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_combines_3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ADD %3, %4
%w0 = COPY %5
$w0 = COPY %5
...
---
name: test_combines_4
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_combines_4
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
%0:_(s64) = COPY %x0
%0:_(s64) = COPY $x0
%1:_(s128) = G_MERGE_VALUES %0, %0
%2:_(s64) = G_EXTRACT %1, 0
%3:_(s64) = G_ADD %2, %2
%w0 = COPY %3
$w0 = COPY %3
...
---
name: test_combines_5
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_combines_5
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ADD %3, %4
%w0 = COPY %5
$w0 = COPY %5
...

40
test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
View File

@ -31,34 +31,34 @@ body: |
; CHECK-LABEL: name: test_constant
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: %w0 = COPY [[COPY]](s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: %w0 = COPY [[C3]](s32)
; CHECK: $w0 = COPY [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: %x0 = COPY [[C4]](s64)
; CHECK: $x0 = COPY [[C4]](s64)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: %x0 = COPY [[C5]](s64)
; CHECK: $x0 = COPY [[C5]](s64)
%0(s1) = G_CONSTANT i1 0
%6:_(s32) = G_ANYEXT %0
%w0 = COPY %6
$w0 = COPY %6
%1(s8) = G_CONSTANT i8 42
%7:_(s32) = G_ANYEXT %1
%w0 = COPY %7
$w0 = COPY %7
%2(s16) = G_CONSTANT i16 65535
%8:_(s32) = G_ANYEXT %2
%w0 = COPY %8
$w0 = COPY %8
%3(s32) = G_CONSTANT i32 -1
%w0 = COPY %3
$w0 = COPY %3
%4(s64) = G_CONSTANT i64 1
%x0 = COPY %4
$x0 = COPY %4
%5(s64) = G_CONSTANT i64 0
%x0 = COPY %5
$x0 = COPY %5
...
---
@ -72,20 +72,20 @@ body: |
; CHECK-LABEL: name: test_fconstant
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: %w0 = COPY [[C]](s32)
; CHECK: $w0 = COPY [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK: %x0 = COPY [[C1]](s64)
; CHECK: $x0 = COPY [[C1]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; CHECK: %w0 = COPY [[ANYEXT]](s32)
; CHECK: $w0 = COPY [[ANYEXT]](s32)
%0(s32) = G_FCONSTANT float 1.0
%w0 = COPY %0
$w0 = COPY %0
%1(s64) = G_FCONSTANT double 2.0
%x0 = COPY %1
$x0 = COPY %1
%2(s16) = G_FCONSTANT half 0.0
%3:_(s32) = G_ANYEXT %2
%w0 = COPY %3
$w0 = COPY %3
...
---
@ -98,8 +98,8 @@ body: |
; CHECK-LABEL: name: test_global
; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[GV]](p0)
; CHECK: %x0 = COPY [[PTRTOINT]](s64)
; CHECK: $x0 = COPY [[PTRTOINT]](s64)
%0(p0) = G_GLOBAL_VALUE @var
%1:_(s64) = G_PTRTOINT %0
%x0 = COPY %1
$x0 = COPY %1
...

18
test/CodeGen/AArch64/GlobalISel/legalize-div.mir
View File

@ -21,10 +21,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_div
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
@ -35,7 +35,7 @@ body: |
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
@ -44,20 +44,20 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; CHECK: %w0 = COPY [[COPY3]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $w0 = COPY [[COPY3]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_SDIV %2, %3
%6:_(s32) = G_ANYEXT %4
%w0 = COPY %6
$w0 = COPY %6
%5(s8) = G_UDIV %2, %3
%7:_(s32) = G_ANYEXT %5
%w0 = COPY %7
$w0 = COPY %7
...

4
test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
View File

@ -15,10 +15,10 @@ declare void @_Unwind_Resume(i8*)
; CHECK: [[LP]].{{[a-z]+}} (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[STRUCT_PTR:%[0-9]+]]:_(s64) = G_PTRTOINT [[PTR]](p0)
; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
; CHECK: [[STRUCT_SEL:%[0-9]+]]:_(s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0

78
test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
View File

@ -34,110 +34,110 @@ registers:
- { id: 18, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_ext
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC]](s32)
; CHECK: $w0 = COPY [[TRUNC]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC1]](s32)
; CHECK: $w0 = COPY [[TRUNC1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC2]](s32)
; CHECK: $w0 = COPY [[TRUNC2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC3]](s32)
; CHECK: $w0 = COPY [[TRUNC3]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: %x0 = COPY [[COPY1]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
; CHECK: %x0 = COPY [[AND]](s64)
; CHECK: $x0 = COPY [[AND]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: %x0 = COPY [[COPY3]](s64)
; CHECK: $x0 = COPY [[COPY3]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY4]], [[C1]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]]
; CHECK: %x0 = COPY [[ASHR]](s64)
; CHECK: $x0 = COPY [[ASHR]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[C2]]
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C2]]
; CHECK: %w0 = COPY [[ASHR1]](s32)
; CHECK: $w0 = COPY [[ASHR1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C3]]
; CHECK: %w0 = COPY [[AND1]](s32)
; CHECK: $w0 = COPY [[AND1]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC6]](s32)
; CHECK: $w0 = COPY [[TRUNC6]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C4]]
; CHECK: %w0 = COPY [[AND2]](s32)
; CHECK: $w0 = COPY [[AND2]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC8]](s32)
; CHECK: $w0 = COPY [[TRUNC8]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC9]], [[C5]]
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C5]]
; CHECK: %w0 = COPY [[ASHR2]](s32)
; CHECK: $w0 = COPY [[ASHR2]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[TRUNC3]]4(s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]]1, [[TRUNC3]]2
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[TRUNC3]]3(s32)
; CHECK: %w0 = COPY [[COPY6]](s32)
; CHECK: $w0 = COPY [[COPY6]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC11]](s32)
; CHECK: $w0 = COPY [[TRUNC11]](s32)
; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: %w0 = COPY [[TRUNC12]](s32)
; CHECK: $w0 = COPY [[TRUNC12]](s32)
; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
; CHECK: %x0 = COPY [[FPEXT]](s64)
%0(s64) = COPY %x0
; CHECK: $x0 = COPY [[FPEXT]](s64)
%0(s64) = COPY $x0
%1(s1) = G_TRUNC %0
%19:_(s32) = G_ANYEXT %1
%w0 = COPY %19
$w0 = COPY %19
%2(s8) = G_TRUNC %0
%20:_(s32) = G_ANYEXT %2
%w0 = COPY %20
$w0 = COPY %20
%3(s16) = G_TRUNC %0
%21:_(s32) = G_ANYEXT %3
%w0 = COPY %21
$w0 = COPY %21
%4(s32) = G_TRUNC %0
%w0 = COPY %4
$w0 = COPY %4
%5(s64) = G_ANYEXT %1
%x0 = COPY %5
$x0 = COPY %5
%6(s64) = G_ZEXT %2
%x0 = COPY %6
$x0 = COPY %6
%7(s64) = G_ANYEXT %3
%x0 = COPY %7
$x0 = COPY %7
%8(s64) = G_SEXT %4
%x0 = COPY %8
$x0 = COPY %8
%9(s32) = G_SEXT %1
%w0 = COPY %9
$w0 = COPY %9
%10(s32) = G_ZEXT %2
%w0 = COPY %10
$w0 = COPY %10
%11(s32) = G_ANYEXT %3
%w0 = COPY %11
$w0 = COPY %11
%12(s32) = G_ZEXT %1
%w0 = COPY %12
$w0 = COPY %12
%13(s32) = G_ANYEXT %2
%w0 = COPY %13
$w0 = COPY %13
%14(s32) = G_SEXT %3
%w0 = COPY %14
$w0 = COPY %14
%15(s8) = G_ZEXT %1
%22:_(s32) = G_ANYEXT %15
%w0 = COPY %22
$w0 = COPY %22
%16(s16) = G_ANYEXT %2
%23:_(s32) = G_ANYEXT %16
%w0 = COPY %23
$w0 = COPY %23
%17(s32) = G_TRUNC %0
%w0 = COPY %17
$w0 = COPY %17
%18(s64) = G_FPEXT %17
%x0 = COPY %18
$x0 = COPY %18
...

46
test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
View File

@ -5,13 +5,13 @@
name: test_extracts_1
body: |
bb.0:
liveins: %w0
liveins: $w0
; Low part of extraction takes entirity of the low register entirely, so
; value stored is forwarded directly from first load.
; CHECK-LABEL: name: test_extracts_1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x2
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
@ -19,9 +19,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store 8)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
%0:_(s64) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(p0) = COPY $x2
%3:_(s128) = G_LOAD %2(p0) :: (load 16)
%4:_(s64) = G_EXTRACT %3(s128), 0
G_STORE %4(s64), %2(p0) :: (store 8)
@ -32,11 +32,11 @@ body: |
name: test_extracts_2
body: |
bb.0:
liveins: %w0
liveins: $w0
; Low extraction wipes takes whole low register. High extraction is real.
; CHECK-LABEL: name: test_extracts_2
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x2
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
@ -47,9 +47,9 @@ body: |
; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store 8)
; CHECK: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 4)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
%0:_(s64) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(p0) = COPY $x2
%3:_(s128) = G_LOAD %2(p0) :: (load 16)
%4:_(s64) = G_EXTRACT %3(s128), 0
%5:_(s32) = G_EXTRACT %3(s128), 64
@ -62,22 +62,22 @@ body: |
name: test_extracts_3
body: |
bb.0:
liveins: %x0, %x1, %x2
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_extracts_3
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
; CHECK: %x0 = COPY [[MV]](s64)
; CHECK: $x0 = COPY [[MV]](s64)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s128) = G_MERGE_VALUES %0, %1
%3:_(s64) = G_EXTRACT %2, 32
%x0 = COPY %3
$x0 = COPY %3
RET_ReallyLR
...
@ -85,19 +85,19 @@ body: |
name: test_extracts_4
body: |
bb.0:
liveins: %x0, %x1, %x2
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_extracts_4
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s128) = G_MERGE_VALUES %0, %1
%3:_(s32) = G_EXTRACT %2, 32
%w0 = COPY %3
$w0 = COPY %3
RET_ReallyLR
...

18
test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
View File

@ -23,25 +23,25 @@ registers:
- { id: 7, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]]
; CHECK: %w0 = COPY [[FCMP]](s32)
; CHECK: $w0 = COPY [[FCMP]](s32)
; CHECK: [[FCMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[TRUNC]](s32), [[TRUNC1]]
; CHECK: %w0 = COPY [[FCMP1]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x0
; CHECK: $w0 = COPY [[FCMP1]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x0
%2(s32) = G_TRUNC %0
%3(s32) = G_TRUNC %1
%4(s32) = G_FCMP floatpred(oge), %0, %1
%w0 = COPY %4
$w0 = COPY %4
%5(s32) = G_FCMP floatpred(uno), %2, %3
%w0 = COPY %5
$w0 = COPY %5
...

20
test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
View File

@ -20,15 +20,15 @@ registers:
- { id: 1, class: _ }
body: |
bb.1:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fneg_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -0.000000e+00
; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[COPY]]
; CHECK: %s0 = COPY [[FSUB]](s32)
%0(s32) = COPY %s0
; CHECK: $s0 = COPY [[FSUB]](s32)
%0(s32) = COPY $s0
%1(s32) = G_FNEG %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
name: test_fneg_f64
@ -37,13 +37,13 @@ registers:
- { id: 1, class: _ }
body: |
bb.1:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: test_fneg_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -0.000000e+00
; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[COPY]]
; CHECK: %d0 = COPY [[FSUB]](s64)
%0(s64) = COPY %d0
; CHECK: $d0 = COPY [[FSUB]](s64)
%0(s64) = COPY $d0
%1(s64) = G_FNEG %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...

128
test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
View File

@ -29,112 +29,112 @@
name: test_fptosi_s32_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptosi_s32_s32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[DEF]](s32)
; CHECK: %w0 = COPY [[FPTOSI]](s32)
; CHECK: $w0 = COPY [[FPTOSI]](s32)
%0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_FPTOSI %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_fptoui_s32_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptoui_s32_s32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[DEF]](s32)
; CHECK: %w0 = COPY [[FPTOUI]](s32)
; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_FPTOUI %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_fptosi_s32_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_fptosi_s32_s64
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[DEF]](s32)
; CHECK: %w0 = COPY [[FPTOSI]](s32)
; CHECK: $w0 = COPY [[FPTOSI]](s32)
%0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_FPTOSI %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_fptoui_s32_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_fptoui_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
; CHECK: %w0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY %x0
; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY $x0
%1:_(s32) = G_FPTOUI %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_fptosi_s64_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptosi_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s32)
; CHECK: %x0 = COPY [[FPTOSI]](s64)
%0:_(s32) = COPY %w0
; CHECK: $x0 = COPY [[FPTOSI]](s64)
%0:_(s32) = COPY $w0
%1:_(s64) = G_FPTOSI %0
%x0 = COPY %1
$x0 = COPY %1
...
---
name: test_fptoui_s64_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptoui_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s32)
; CHECK: %x0 = COPY [[FPTOUI]](s64)
%0:_(s32) = COPY %w0
; CHECK: $x0 = COPY [[FPTOUI]](s64)
%0:_(s32) = COPY $w0
%1:_(s64) = G_FPTOUI %0
%x0 = COPY %1
$x0 = COPY %1
...
---
name: test_fptosi_s64_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_fptosi_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s64)
; CHECK: %x0 = COPY [[FPTOSI]](s64)
%0:_(s64) = COPY %x0
; CHECK: $x0 = COPY [[FPTOSI]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_FPTOSI %0
%x0 = COPY %1
$x0 = COPY %1
...
---
name: test_fptoui_s64_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_fptoui_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s64)
; CHECK: %x0 = COPY [[FPTOUI]](s64)
%0:_(s64) = COPY %x0
; CHECK: $x0 = COPY [[FPTOUI]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_FPTOUI %0
%x0 = COPY %1
$x0 = COPY %1
...
@ -143,93 +143,93 @@ body: |
name: test_fptosi_s1_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptosi_s1_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
; CHECK: %x0 = COPY [[TRUNC]](s1)
%0:_(s32) = COPY %w0
; CHECK: $x0 = COPY [[TRUNC]](s1)
%0:_(s32) = COPY $w0
%1:_(s1) = G_FPTOSI %0
%x0 = COPY %1
$x0 = COPY %1
...
---
name: test_fptoui_s1_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptoui_s1_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_fptosi_s8_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_fptosi_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY %x0
; CHECK: $w0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_fptoui_s8_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_fptoui_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY %x0
; CHECK: $w0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_fptosi_s16_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptosi_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_fptoui_s16_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_fptoui_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
%w0 = COPY %2
$w0 = COPY %2
...

14
test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
View File

@ -19,20 +19,20 @@ registers:
- { id: 3, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_gep_small
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[ASHR]](s64)
; CHECK: %x0 = COPY [[GEP]](p0)
%0(p0) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[GEP]](p0)
%0(p0) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %1
%3(p0) = G_GEP %0, %2(s8)
%x0 = COPY %3
$x0 = COPY %3
...

10
test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
View File

@ -14,13 +14,13 @@ registers:
- { id: 0, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_copy
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: %x0 = COPY [[COPY]](s64)
%0(s64) = COPY %x0
%x0 = COPY %0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: $x0 = COPY [[COPY]](s64)
%0(s64) = COPY $x0
$x0 = COPY %0
...
---

68
test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
View File

@ -16,7 +16,7 @@
name: test_inserts_1
body: |
bb.0:
liveins: %w0
liveins: $w0
; Low part of insertion wipes out the old register entirely, so %0 gets
; forwarded to the G_STORE. Hi part is unchanged so (split) G_LOAD gets
@ -26,9 +26,9 @@ body: |
; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
; CHECK: G_STORE %0(s64)
; CHECK: G_STORE [[HI]]
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
%0:_(s64) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(p0) = COPY $x2
%3:_(s128) = G_LOAD %2(p0) :: (load 16)
%4:_(s128) = G_INSERT %3(s128), %0(s64), 0
G_STORE %4(s128), %2(p0) :: (store 16)
@ -39,7 +39,7 @@ body: |
name: test_inserts_2
body: |
bb.0:
liveins: %w0
liveins: $w0
; Low insertion wipes out the old register entirely, so %0 gets forwarded
; to the G_STORE again. Second insertion is real.
@ -49,9 +49,9 @@ body: |
; CHECK: [[NEWHI:%[0-9]+]]:_(s64) = G_INSERT [[HI]], %1(s32), 0
; CHECK: G_STORE %0(s64)
; CHECK: G_STORE [[NEWHI]]
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
%0:_(s64) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(p0) = COPY $x2
%3:_(s128) = G_LOAD %2(p0) :: (load 16)
%4:_(s128) = G_INSERT %3(s128), %0(s64), 0
%5:_(s128) = G_INSERT %4(s128), %1(s32), 64
@ -63,7 +63,7 @@ body: |
name: test_inserts_3
body: |
bb.0:
liveins: %w0
liveins: $w0
; I'm not entirely convinced inserting a p0 into an s64 is valid, but it's
; certainly better than the alternative of directly forwarding the value
@ -74,9 +74,9 @@ body: |
; CHECK: [[NEWLO:%[0-9]+]]:_(s64) = G_PTRTOINT %0(p0)
; CHECK: G_STORE [[NEWLO]](s64)
; CHECK: G_STORE [[HI]]
%0:_(p0) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(p0) = COPY $x2
%3:_(s128) = G_LOAD %2(p0) :: (load 16)
%4:_(s128) = G_INSERT %3(s128), %0(p0), 0
G_STORE %4(s128), %2(p0) :: (store 16)
@ -87,18 +87,18 @@ body: |
name: test_inserts_4
body: |
bb.0:
liveins: %w0
liveins: $w0
; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair.
; CHECK-LABEL: name: test_inserts_4
; CHECK: [[VALEXT:%[0-9]+]]:_(s32) = COPY %2(s32)
; CHECK: [[VAL:%[0-9]+]]:_(s32) = G_INSERT [[VALEXT]], %1(s1), 0
; CHECK: %5:_(s8) = G_TRUNC [[VAL]](s32)
%4:_(s32) = COPY %w0
%4:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %4
%5:_(s32) = COPY %w1
%5:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %5
%2:_(p0) = COPY %x2
%2:_(p0) = COPY $x2
%3:_(s8) = G_INSERT %1(s8), %0(s1), 0
G_STORE %3(s8), %2(p0) :: (store 1)
RET_ReallyLR
@ -108,7 +108,7 @@ body: |
name: test_inserts_5
body: |
bb.0:
liveins: %x0, %x1, %x2
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_inserts_5
@ -117,13 +117,13 @@ body: |
; CHECK: [[INS_HI:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 32
; CHECK: [[VAL_HI:%[0-9]+]]:_(s64) = G_INSERT %1, [[INS_HI]](s32), 0
; CHECK: %4:_(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s64) = COPY %x2
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s128) = G_MERGE_VALUES %0, %1
%4:_(s128) = G_INSERT %3, %2, 32
%5:_(s64) = G_TRUNC %4
%x0 = COPY %5
$x0 = COPY %5
RET_ReallyLR
...
@ -131,19 +131,19 @@ body: |
name: test_inserts_6
body: |
bb.0:
liveins: %x0, %x1, %x2
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_inserts_6
; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, %2(s32), 32
; CHECK: %4:_(s128) = G_MERGE_VALUES [[VAL_LO]](s64), %1(s64)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s32) = COPY %w2
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s32) = COPY $w2
%3:_(s128) = G_MERGE_VALUES %0, %1
%4:_(s128) = G_INSERT %3, %2, 32
%5:_(s64) = G_TRUNC %4
%x0 = COPY %5
$x0 = COPY %5
RET_ReallyLR
...
@ -151,19 +151,19 @@ body: |
name: test_inserts_nonpow2
body: |
bb.0:
liveins: %x0, %x1, %x2
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_inserts_nonpow2
; CHECK: [[C:%[0-9]+]]:_(s64) = COPY %x3
; CHECK: %x0 = COPY [[C]]
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s64) = COPY %x2
%3:_(s64) = COPY %x3
; CHECK: [[C:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: $x0 = COPY [[C]]
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = COPY $x3
%4:_(s192) = G_MERGE_VALUES %0, %1, %2
%5:_(s192) = G_INSERT %4, %3, 0
%6:_(s64), %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %5
%x0 = COPY %6
$x0 = COPY %6
RET_ReallyLR
...

112
test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
View File

@ -29,104 +29,104 @@
name: test_sitofp_s32_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_SITOFP %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_uitofp_s32_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_uitofp_s32_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_UITOFP %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_sitofp_s32_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_sitofp_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%0:_(s64) = COPY $x0
%1:_(s32) = G_SITOFP %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_uitofp_s32_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_uitofp_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%0:_(s64) = COPY $x0
%1:_(s32) = G_UITOFP %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_sitofp_s64_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s64) = G_SITOFP %0
%w0 = COPY %1
$w0 = COPY %1
...
---
name: test_uitofp_s64_s32
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_uitofp_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s64) = G_UITOFP %0
%x0 = COPY %1
$x0 = COPY %1
...
---
name: test_sitofp_s64_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_sitofp_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%0:_(s64) = COPY $x0
%1:_(s64) = G_SITOFP %0
%x0 = COPY %1
$x0 = COPY %1
...
---
name: test_uitofp_s64_s64
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_uitofp_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%0:_(s64) = COPY $x0
%1:_(s64) = G_UITOFP %0
%x0 = COPY %1
$x0 = COPY %1
...
@ -134,103 +134,103 @@ body: |
name: test_sitofp_s32_s1
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_uitofp_s32_s1
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_uitofp_s32_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_UITOFP %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_sitofp_s64_s8
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s64_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %0
%2:_(s64) = G_SITOFP %1
%x0 = COPY %2
$x0 = COPY %2
...
---
name: test_uitofp_s64_s8
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_uitofp_s64_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %0
%2:_(s64) = G_UITOFP %1
%x0 = COPY %2
$x0 = COPY %2
...
---
name: test_sitofp_s32_s16
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1
%w0 = COPY %2
$w0 = COPY %2
...
---
name: test_uitofp_s32_s16
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_uitofp_s32_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
%0:_(s32) = COPY %w0
%0:_(s32) = COPY $w0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_UITOFP %1
%w0 = COPY %2
$w0 = COPY %2
...

26
test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
View File

@ -27,40 +27,40 @@ registers:
- { id: 8, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_load
%0(p0) = COPY %x0
%0(p0) = COPY $x0
%1(s1) = G_LOAD %0 :: (load 1 from %ir.addr)
%9:_(s32) = G_ANYEXT %1
%w0 = COPY %9
$w0 = COPY %9
; CHECK: %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
%2(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%10:_(s32) = G_ANYEXT %2
%w0 = COPY %10
$w0 = COPY %10
; CHECK: %3:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
%3(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%11:_(s32) = G_ANYEXT %3
%w0 = COPY %11
$w0 = COPY %11
; CHECK: %4:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
%4(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
%w0 = COPY %4
$w0 = COPY %4
; CHECK: %5:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
%x0 = COPY %5
$x0 = COPY %5
%6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%12:_(s64) = G_PTRTOINT %6
%x0 = COPY %12
$x0 = COPY %12
; CHECK: %7:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%13:_(s64) = G_BITCAST %7
%x0 = COPY %13
$x0 = COPY %13
; CHECK: [[LOAD0:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@ -69,7 +69,7 @@ body: |
; CHECK: %8:_(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
%8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
%14:_(s64) = G_TRUNC %8
%x0 = COPY %14
$x0 = COPY %14
...
---
@ -85,11 +85,11 @@ registers:
- { id: 7, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_store
%0(p0) = COPY %x0
%1(s32) = COPY %w1
%0(p0) = COPY $x0
%1(s32) = COPY $w1
; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[B:%.*]]:_(s32) = COPY %1(s32)

2
test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
View File

@ -26,5 +26,5 @@ body: |
%2(s8) = G_MERGE_VALUES %1(s4), %1(s4)
%3(s8) = COPY %2(s8)
%4(s64) = G_ANYEXT %3(s8)
%x0 = COPY %4(s64)
$x0 = COPY %4(s64)
...

50
test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
View File

@ -27,23 +27,23 @@ registers:
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_mul_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_MUL %2, %3
%5(s64) = G_ANYEXT %4
%x0 = COPY %5
$x0 = COPY %5
...
@ -51,25 +51,25 @@ body: |
name: test_smul_overflow
body: |
bb.0:
liveins: %x0, %x1, %w2, %w3
liveins: $x0, $x1, $w2, $w3
; CHECK-LABEL: name: test_smul_overflow
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
; CHECK: [[SMULH:%[0-9]+]]:_(s64) = G_SMULH [[COPY]], [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[ASHR]]
; CHECK: %x0 = COPY [[MUL]](s64)
; CHECK: $x0 = COPY [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
; CHECK: $w0 = COPY [[COPY2]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_SMULO %0, %1
%x0 = COPY %2
$x0 = COPY %2
%4:_(s32) = G_ANYEXT %3
%w0 = COPY %4
$w0 = COPY %4
...
@ -78,23 +78,23 @@ body: |
name: test_umul_overflow
body: |
bb.0:
liveins: %x0, %x1, %w2, %w3
liveins: $x0, $x1, $w2, $w3
; CHECK-LABEL: name: test_umul_overflow
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
; CHECK: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH [[COPY]], [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]]
; CHECK: %x0 = COPY [[MUL]](s64)
; CHECK: $x0 = COPY [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
; CHECK: $w0 = COPY [[COPY2]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_UMULO %0, %1
%x0 = COPY %2
$x0 = COPY %2
%4:_(s32) = G_ANYEXT %3
%w0 = COPY %4
$w0 = COPY %4
...

10
test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
View File

@ -19,16 +19,16 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_legalize_merge_v3s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[MV:%[0-9]+]]:_(<3 x s64>) = G_MERGE_VALUES [[COPY]](s64), [[COPY]](s64), [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s64>) = COPY [[MV]](<3 x s64>)
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<3 x s64>)
; CHECK: %x0 = COPY [[UV]](s64)
%0(s64) = COPY %x0
; CHECK: $x0 = COPY [[UV]](s64)
%0(s64) = COPY $x0
%1(<3 x s64>) = G_MERGE_VALUES %0(s64), %0(s64), %0(s64)
%2(<3 x s64>) = COPY %1(<3 x s64>)
%3(s64), %4(s64), %5(s64) = G_UNMERGE_VALUES %2(<3 x s64>)
%x0 = COPY %3(s64)
$x0 = COPY %3(s64)
...

44
test/CodeGen/AArch64/GlobalISel/legalize-or.mir
View File

@ -5,51 +5,51 @@
name: test_scalar_or_small
body: |
bb.0:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_or_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[TRUNC1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
; CHECK: %x0 = COPY [[TRUNC2]](s8)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
; CHECK: $x0 = COPY [[TRUNC2]](s8)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1
%4:_(s8) = G_OR %2, %3
%x0 = COPY %4
$x0 = COPY %4
...
---
name: test_big_scalar_power_of_2
body: |
bb.0:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; We have a temporary G_MERGE_VALUES in the legalizer that gets
; cleaned up with the G_UNMERGE_VALUES, so we end up directly
; copying the results of the G_OR ops.
; CHECK-LABEL: name: test_big_scalar_power_of_2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY2]]
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[COPY3]]
; CHECK: %x0 = COPY [[OR]](s64)
; CHECK: %x1 = COPY [[OR1]](s64)
; CHECK: RET_ReallyLR implicit %x0, implicit %x1
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s64) = COPY %x2
%3:_(s64) = COPY %x3
; CHECK: $x0 = COPY [[OR]](s64)
; CHECK: $x1 = COPY [[OR1]](s64)
; CHECK: RET_ReallyLR implicit $x0, implicit $x1
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = COPY $x3
%4:_(s128) = G_MERGE_VALUES %0, %1
%5:_(s128) = G_MERGE_VALUES %2, %3
%6:_(s128) = G_OR %4, %5
%7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
%x0 = COPY %7
%x1 = COPY %8
RET_ReallyLR implicit %x0, implicit %x1
$x0 = COPY %7
$x1 = COPY %8
RET_ReallyLR implicit $x0, implicit $x1
...

122
test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
View File

@ -66,8 +66,8 @@ body: |
; CHECK-LABEL: name: legalize_phi
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
@ -89,17 +89,17 @@ body: |
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; CHECK: %w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
; Test that we insert legalization artifacts(Truncs here) into the correct BBs
; while legalizing the G_PHI to s16.
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %w0
liveins: $w0
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 0
%3(s32) = G_CONSTANT i32 1
%6(s32) = G_CONSTANT i32 2
@ -123,8 +123,8 @@ body: |
bb.3:
%9(s1) = G_PHI %5(s1), %bb.1, %8(s1), %bb.2
%10(s32) = G_ZEXT %9(s1)
%w0 = COPY %10(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %10(s32)
RET_ReallyLR implicit $w0
...
---
@ -147,10 +147,10 @@ body: |
; CHECK-LABEL: name: legalize_phi_ptr
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: %w2, %x0, %x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY %x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %w2
; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: G_BR %bb.2
@ -158,16 +158,16 @@ body: |
; CHECK: successors: %bb.2(0x80000000)
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
; CHECK: %x0 = COPY [[PHI]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[PHI]](p0)
; CHECK: RET_ReallyLR implicit $x0
bb.1:
successors: %bb.2, %bb.3
liveins: %w2, %x0, %x1
liveins: $w2, $x0, $x1
%0(p0) = COPY %x0
%1(p0) = COPY %x1
%4(s32) = COPY %w2
%0(p0) = COPY $x0
%1(p0) = COPY $x1
%4(s32) = COPY $w2
%2(s1) = G_TRUNC %4(s32)
G_BRCOND %2(s1), %bb.2
G_BR %bb.3
@ -177,8 +177,8 @@ body: |
bb.3:
%3(p0) = G_PHI %0(p0), %bb.1, %1(p0), %bb.2
%x0 = COPY %3(p0)
RET_ReallyLR implicit %x0
$x0 = COPY %3(p0)
RET_ReallyLR implicit $x0
...
---
@ -206,8 +206,8 @@ body: |
; CHECK-LABEL: name: legalize_phi_empty
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@ -229,17 +229,17 @@ body: |
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; CHECK: %w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %w0
liveins: $w0
; Test that we properly legalize a phi with a predecessor that's empty
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 0
%3(s32) = G_CONSTANT i32 3
%6(s32) = G_CONSTANT i32 1
@ -263,8 +263,8 @@ body: |
bb.3:
%9(s1) = G_PHI %8(s1), %bb.1, %5(s1), %bb.2
%10(s32) = G_ZEXT %9(s1)
%w0 = COPY %10(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %10(s32)
RET_ReallyLR implicit $w0
...
---
@ -289,8 +289,8 @@ body: |
; CHECK-LABEL: name: legalize_phi_loop
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
@ -312,14 +312,14 @@ body: |
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: %w0 = COPY [[AND1]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[AND1]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x80000000)
liveins: %w0
liveins: $w0
; Test that we properly legalize a phi that uses a value from the same BB
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%2(s8) = G_CONSTANT i8 1
%7(s8) = G_CONSTANT i8 0
@ -334,8 +334,8 @@ body: |
bb.3:
%6(s32) = G_ZEXT %3(s8)
%w0 = COPY %6(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
@ -357,8 +357,8 @@ body: |
; CHECK-LABEL: name: legalize_phi_cycle
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: bb.1:
@ -373,15 +373,15 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
; CHECK: G_BRCOND [[TRUNC2]](s1), %bb.1
; CHECK: bb.2:
; CHECK: %w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x80000000)
liveins: %w0
liveins: $w0
; Test that we properly legalize a phi that uses itself
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%4(s8) = G_CONSTANT i8 0
bb.1:
@ -393,8 +393,8 @@ body: |
G_BRCOND %3(s1), %bb.1
bb.3:
%w0 = COPY %2(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
@ -426,8 +426,8 @@ body: |
; CHECK-LABEL: name: legalize_phi_same_bb
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: %w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@ -457,18 +457,18 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[C]]1, [[C]]2
; CHECK: %w0 = COPY [[C]]3(s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[C]]3(s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %w0
liveins: $w0
; Make sure that we correctly insert the new legalized G_PHI at the
; correct location (ie make sure G_PHIs are the first insts in the BB).
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 0
%3(s32) = G_CONSTANT i32 3
%6(s32) = G_CONSTANT i32 1
@ -496,8 +496,8 @@ body: |
%11(s32) = G_ZEXT %9(s8)
%12(s32) = G_ZEXT %10(s8)
%13(s32) = G_ADD %11, %12
%w0 = COPY %13(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %13(s32)
RET_ReallyLR implicit $w0
...
---
@ -530,8 +530,8 @@ body: |
; CHECK-LABEL: name: legalize_phi_diff_bb
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: %w0, %w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@ -563,18 +563,18 @@ body: |
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[C]]8, [[C]]7
; CHECK: %w0 = COPY [[AND1]](s32)
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[AND1]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: %w0, %w1
liveins: $w0, $w1
; Make sure that we correctly legalize PHIs sharing common defs
; in different BBs.
%0(s32) = COPY %w0
%1(s32) = COPY %w1
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_CONSTANT i32 0
%4(s32) = G_CONSTANT i32 3
%9(s32) = G_CONSTANT i32 1
@ -599,7 +599,7 @@ body: |
bb.3:
%13(s8) = G_PHI %7(s8), %bb.1, %6(s8), %bb.0
%14(s32) = G_ZEXT %13(s8)
%w0 = COPY %14(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %14(s32)
RET_ReallyLR implicit $w0
...

30
test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
View File

@ -13,28 +13,28 @@
name: test_pow
body: |
bb.0.entry:
liveins: %d0, %d1, %s2, %s3
liveins: $d0, $d1, $s2, $s3
; CHECK-LABEL: name: test_pow
; CHECK: hasCalls: true
%0:_(s64) = COPY %d0
%1:_(s64) = COPY %d1
%2:_(s32) = COPY %s2
%3:_(s32) = COPY %s3
%0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1
%2:_(s32) = COPY $s2
%3:_(s32) = COPY $s3
; CHECK: %d0 = COPY %0
; CHECK: %d1 = COPY %1
; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: %4:_(s64) = COPY %d0
; CHECK: $d0 = COPY %0
; CHECK: $d1 = COPY %1
; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: %4:_(s64) = COPY $d0
%4:_(s64) = G_FPOW %0, %1
%x0 = COPY %4
$x0 = COPY %4
; CHECK: %s0 = COPY %2
; CHECK: %s1 = COPY %3
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
; CHECK: %5:_(s32) = COPY %s0
; CHECK: $s0 = COPY %2
; CHECK: $s1 = COPY %3
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK: %5:_(s32) = COPY $s0
%5:_(s32) = G_FPOW %2, %3
%w0 = COPY %5
$w0 = COPY %5
...

84
test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
View File

@ -30,19 +30,19 @@ registers:
- { id: 2, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_urem_64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
; CHECK: %x0 = COPY [[SUB]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[SUB]](s64)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_UREM %0, %1
%x0 = COPY %2
$x0 = COPY %2
...
@ -56,23 +56,23 @@ registers:
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_srem_32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
; CHECK: %w0 = COPY [[SUB]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $w0 = COPY [[SUB]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%3(s32) = G_TRUNC %0
%4(s32) = G_TRUNC %1
%5(s32) = G_SREM %3, %4
%w0 = COPY %5
$w0 = COPY %5
...
---
@ -85,12 +85,12 @@ registers:
- { id: 8, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_srem_8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
@ -107,14 +107,14 @@ body: |
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: %w0 = COPY [[COPY4]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $w0 = COPY [[COPY4]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%6(s8) = G_TRUNC %0
%7(s8) = G_TRUNC %1
%8(s8) = G_SREM %6, %7
%9:_(s32) = G_ANYEXT %8
%w0 = COPY %9
$w0 = COPY %9
...
---
name: test_frem
@ -127,33 +127,33 @@ registers:
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_frem
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
; CHECK: %d0 = COPY [[COPY]](s64)
; CHECK: %d1 = COPY [[COPY1]](s64)
; CHECK: BL &fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
; CHECK: %x0 = COPY [[COPY2]](s64)
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[COPY]](s64)
; CHECK: $d1 = COPY [[COPY1]](s64)
; CHECK: BL &fmod, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY2]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
; CHECK: %s0 = COPY [[TRUNC]](s32)
; CHECK: %s1 = COPY [[TRUNC1]](s32)
; CHECK: BL &fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY %s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
; CHECK: %w0 = COPY [[COPY3]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[TRUNC]](s32)
; CHECK: $s1 = COPY [[TRUNC1]](s32)
; CHECK: BL &fmodf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: $w0 = COPY [[COPY3]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_FREM %0, %1
%x0 = COPY %2
$x0 = COPY %2
%3(s32) = G_TRUNC %0
%4(s32) = G_TRUNC %1
%5(s32) = G_FREM %3, %4
%w0 = COPY %5
$w0 = COPY %5

22
test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
View File

@ -22,10 +22,10 @@ registers:
- { id: 6, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_shift
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
@ -36,7 +36,7 @@ body: |
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[ASHR1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
@ -45,27 +45,27 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: %w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY1]]0, [[COPY1]]1
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]]2(s32)
; CHECK: %w0 = COPY [[COPY4]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $w0 = COPY [[COPY4]](s32)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_ASHR %2, %3
%7:_(s32) = G_ANYEXT %4
%w0 = COPY %7
$w0 = COPY %7
%5(s8) = G_LSHR %2, %3
%8:_(s32) = G_ANYEXT %5
%w0 = COPY %8
$w0 = COPY %8
%6(s8) = G_SHL %2, %3
%9:_(s32) = G_ANYEXT %6
%w0 = COPY %9
$w0 = COPY %9
...

94
test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
View File

@ -45,46 +45,46 @@ body: |
; CHECK-LABEL: name: test_simple
; CHECK: bb.0.{{[a-zA-Z0-9]+}}:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
; CHECK: %x0 = COPY [[PTRTOINT]](s64)
; CHECK: $x0 = COPY [[PTRTOINT]](s64)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: bb.1.{{[a-zA-Z0-9]+}}:
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: %w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
; CHECK: %w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
; CHECK: %x0 = COPY [[SELECT4]](s64)
; CHECK: $x0 = COPY [[SELECT4]](s64)
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
; CHECK: %x0 = COPY [[BITCAST1]](s64)
; CHECK: $x0 = COPY [[BITCAST1]](s64)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[SELECT3]](s32)
; CHECK: %w0 = COPY [[BITCAST2]](s32)
; CHECK: $w0 = COPY [[BITCAST2]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[COPY]](s64)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
; CHECK: %w0 = COPY [[BITCAST4]](s32)
; CHECK: $w0 = COPY [[BITCAST4]](s32)
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s64)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
; CHECK: %w0 = COPY [[BITCAST6]](s32)
; CHECK: $w0 = COPY [[BITCAST6]](s32)
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
%0(s64) = COPY %x0
liveins: $x0, $x1, $x2, $x3
%0(s64) = COPY $x0
%1(s1) = G_TRUNC %0
%2(s8) = G_TRUNC %0
@ -93,7 +93,7 @@ body: |
%5(p0) = G_INTTOPTR %0
%6(s64) = G_PTRTOINT %5
%x0 = COPY %6
$x0 = COPY %6
G_BRCOND %1, %bb.1
@ -101,31 +101,31 @@ body: |
%7(s1) = G_SELECT %1, %1, %1
%21:_(s32) = G_ANYEXT %7
%w0 = COPY %21
$w0 = COPY %21
%8(s8) = G_SELECT %1, %2, %2
%20:_(s32) = G_ANYEXT %8
%w0 = COPY %20
$w0 = COPY %20
%9(s16) = G_SELECT %1, %3, %3
%19:_(s32) = G_ANYEXT %9
%w0 = COPY %19
$w0 = COPY %19
%10(s32) = G_SELECT %1, %4, %4
%11(s64) = G_SELECT %1, %0, %0
%x0 = COPY %11
$x0 = COPY %11
%12(<2 x s32>) = G_BITCAST %0
%13(s64) = G_BITCAST %12
%x0 = COPY %13
$x0 = COPY %13
%14(s32) = G_BITCAST %10
%w0 = COPY %14
$w0 = COPY %14
%15(<4 x s8>) = G_BITCAST %0
%17:_(s32) = G_BITCAST %15
%w0 = COPY %17
$w0 = COPY %17
%16(<2 x s16>) = G_BITCAST %0
%18:_(s32) = G_BITCAST %16
%w0 = COPY %18
$w0 = COPY %18
...
---
@ -138,22 +138,22 @@ registers:
- { id: 3, class: _}
body: |
bb.1:
liveins: %x0, %x1
liveins: $x0, $x1
; This is legal and shouldn't be changed.
; CHECK-LABEL: name: bitcast128
; CHECK: liveins: %x0, %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
; CHECK: %q0 = COPY [[BITCAST]](<2 x s64>)
; CHECK: RET_ReallyLR implicit %q0
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $q0 = COPY [[BITCAST]](<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
%2(<2 x s64>) = G_BITCAST %3(s128)
%q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit %q0
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
@ -166,19 +166,19 @@ registers:
- { id: 3, class: _}
body: |
bb.1:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: testExtOfCopyOfTrunc
; CHECK: liveins: %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: %x0 = COPY [[COPY1]](s64)
; CHECK: RET_ReallyLR implicit %x0
%0(s64) = COPY %x0
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0(s64) = COPY $x0
%1(s1) = G_TRUNC %0
%2(s1) = COPY %1
%3(s64) = G_ANYEXT %2
%x0 = COPY %3
RET_ReallyLR implicit %x0
$x0 = COPY %3
RET_ReallyLR implicit $x0
...
---
@ -191,19 +191,19 @@ registers:
- { id: 3, class: _}
body: |
bb.1:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: testExtOf2CopyOfTrunc
; CHECK: liveins: %x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: %x0 = COPY [[COPY1]](s64)
; CHECK: RET_ReallyLR implicit %x0
%0(s64) = COPY %x0
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0(s64) = COPY $x0
%1(s1) = G_TRUNC %0
%2(s1) = COPY %1
%4:_(s1) = COPY %2
%3(s64) = G_ANYEXT %4
%x0 = COPY %3
RET_ReallyLR implicit %x0
$x0 = COPY %3
RET_ReallyLR implicit $x0
...

14
test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
View File

@ -21,21 +21,21 @@ registers:
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_sub_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_SUB %2, %3
%5(s64) = G_ANYEXT %4
%x0 = COPY %5
$x0 = COPY %5
...

2
test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
View File

@ -14,5 +14,5 @@ body: |
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
%0:_(s128) = G_IMPLICIT_DEF
%1:_(s64) = G_TRUNC %0
%x0 = COPY %1
$x0 = COPY %1
...

2
test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
View File

@ -23,6 +23,6 @@ body: |
; CHECK: unable to legalize instruction: {{.*}} G_UNMERGE_VALUES
%1(s4), %2(s4)= G_UNMERGE_VALUES %0(s8)
%3(s64) = G_ANYEXT %1(s4)
%x0 = COPY %3(s64)
$x0 = COPY %3(s64)
...

4
test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
View File

@ -12,7 +12,7 @@ name: test_vaarg
body: |
bb.0:
; CHECK-LABEL: name: test_vaarg
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s64)
@ -28,7 +28,7 @@ body: |
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[PTR_MASK]], [[C3]](s64)
; CHECK: G_STORE [[GEP3]](p0), [[COPY]](p0) :: (store 8)
%0:_(p0) = COPY %x0
%0:_(p0) = COPY $x0
%1:_(s8) = G_VAARG %0(p0), 1

14
test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
View File

@ -21,21 +21,21 @@ registers:
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_xor_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_XOR %2, %3
%5(s64) = G_ANYEXT %4
%x0 = COPY %5
$x0 = COPY %5
...

10
test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
View File

@ -75,10 +75,10 @@ registers:
# CHECK-NEXT: G_FADD %0, %2
body: |
bb.0 (%ir-block.0):
liveins: %s0, %w0
liveins: $s0, $w0
%0(s32) = COPY %s0
%6(s32) = COPY %w0
%0(s32) = COPY $s0
%6(s32) = COPY $w0
%1(s1) = G_TRUNC %6
%4(s32) = G_FCONSTANT float 1.000000e+00
%5(s32) = G_FCONSTANT float 2.000000e+00
@ -93,7 +93,7 @@ body: |
bb.3.end:
%2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
%3(s32) = G_FADD %0, %2
%s0 = COPY %3(s32)
RET_ReallyLR implicit %s0
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
...

8
test/CodeGen/AArch64/GlobalISel/localizer.mir
View File

@ -274,8 +274,8 @@ body: |
; CHECK-LABEL: name: non_local_label
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
@ -288,10 +288,10 @@ body: |
; The newly created reg should be on the same regbank/regclass as its origin.
bb.0:
liveins: %s0
liveins: $s0
successors: %bb.1
%0:fpr(s32) = COPY %s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FCONSTANT float 1.0
bb.1:

72
test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
View File

@ -9,15 +9,15 @@ body: |
; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %[[TWO:[0-9]+]]:_(s32) = G_ADD %[[ONE]], %[[ONE]]
; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]
; CHECK-NEXT: %[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit %[[RET]]
; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
bb.0:
%0:_(s32) = G_CONSTANT i32 1
%1:_(s32) = G_ADD %0, %0
%2:_(s32) = G_ADD %0, %0
%3:_(s32) = G_ADD %1, %2
%w0 = COPY %3(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: regbankselected
@ -29,15 +29,15 @@ body: |
; CHECK: %[[ONE:[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]
; CHECK-NEXT: %[[SUM:[0-9]+]]:gpr(s32) = G_ADD %[[TWO]], %[[TWO]]
; CHECK-NEXT: %[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit %[[RET]]
; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
bb.0:
%0:gpr(s32) = G_CONSTANT i32 1
%1:gpr(s32) = G_ADD %0, %0
%2:gpr(s32) = G_ADD %0, %0
%3:gpr(s32) = G_ADD %1, %2
%w0 = COPY %3(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: legalized
@ -49,15 +49,15 @@ body: |
; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]
; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]
; CHECK-NEXT: %[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit %[[RET]]
; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
bb.0:
%0:_(s32) = G_CONSTANT i32 1
%1:_(s32) = G_ADD %0, %0
%2:gpr(s32) = G_ADD %0, %0
%3:_(s32) = G_ADD %1, %2
%w0 = COPY %3(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: legalized_sym
@ -69,15 +69,15 @@ body: |
; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]
; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]
; CHECK-NEXT: %[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit %[[RET]]
; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
bb.0:
%0:_(s32) = G_CONSTANT i32 1
%1:gpr(s32) = G_ADD %0, %0
%2:_(s32) = G_ADD %0, %0
%3:_(s32) = G_ADD %1, %2
%w0 = COPY %3(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: int_extensions
@ -93,8 +93,8 @@ body: |
; CHECK-NEXT: %[[S16_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S16]](s16)
; CHECK-NEXT: %[[S32_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S32]](s32)
; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s64) = G_ADD %[[S16_Z64]], %[[S32_Z64]]
; CHECK-NEXT: %[[RET:[wx][0-9]+]] = COPY %[[SUM]](s64)
; CHECK-NEXT: RET_ReallyLR implicit %[[RET]]
; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
bb.0.entry:
%0:_(s8) = G_CONSTANT i8 1
%1:_(s16) = G_SEXT %0(s8)
@ -102,8 +102,8 @@ body: |
%3:_(s64) = G_ZEXT %1(s16)
%4:_(s64) = G_ZEXT %2(s32)
%5:_(s64) = G_ADD %3, %4
%x0 = COPY %5(s64)
RET_ReallyLR implicit %x0
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: generic
@ -115,13 +115,13 @@ body: |
; CHECK: %[[SG:[0-9]+]]:_(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}}
; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[SG]], %[[SG]]
bb.0:
%0:_(s32) = COPY %w0
%1:_(s32) = COPY %w1
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_ADD %0, %1
%3:_(s32) = COPY %2(s32)
%4:_(s32) = G_ADD %3, %3
%w0 = COPY %4(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %4(s32)
RET_ReallyLR implicit $w0
...
---
name: generic_to_concrete_copy
@ -134,13 +134,13 @@ body: |
; CHECK-NEXT: %[[S2:[0-9]+]]:gpr32 = COPY %[[S1]](s32)
; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[S2]], %[[S2]]
bb.0:
%0:_(s32) = COPY %w0
%1:_(s32) = COPY %w1
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_ADD %0, %1
%3:gpr32 = COPY %2(s32)
%4:gpr32 = ADDWrr %3, %3
%w0 = COPY %4
RET_ReallyLR implicit %w0
$w0 = COPY %4
RET_ReallyLR implicit $w0
...
---
name: concrete_to_generic_copy
@ -153,13 +153,13 @@ body: |
; CHECK-NEXT: %[[S2:[0-9]+]]:_(s32) = COPY %[[S1]]
; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[S2]], %[[S2]]
bb.0:
%0:gpr32 = COPY %w0
%1:gpr32 = COPY %w1
%0:gpr32 = COPY $w0
%1:gpr32 = COPY $w1
%2:gpr32 = ADDWrr %0, %1
%3:_(s32) = COPY %2
%4:_(s32) = G_ADD %3, %3
%w0 = COPY %4(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %4(s32)
RET_ReallyLR implicit $w0
...
---
name: concrete
@ -171,11 +171,11 @@ body: |
; CHECK: %[[SC:[0-9]+]]:gpr32 = ADDWrr %{{[0-9]+}}, %{{[0-9]+}}
; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[SC]], %[[SC]]
bb.0:
%0:gpr32 = COPY %w0
%1:gpr32 = COPY %w1
%0:gpr32 = COPY $w0
%1:gpr32 = COPY $w1
%2:gpr32 = ADDWrr %0, %1
%3:gpr32 = COPY %2
%4:gpr32 = ADDWrr %3, %3
%w0 = COPY %4
RET_ReallyLR implicit %w0
$w0 = COPY %4
RET_ReallyLR implicit $w0
...

12
test/CodeGen/AArch64/GlobalISel/no-regclass.mir
View File

@ -19,13 +19,13 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: unused_reg
; CHECK: liveins: %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
; CHECK: %w0 = COPY [[COPY]]
%0:gpr(s32) = COPY %w0
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
; CHECK: $w0 = COPY [[COPY]]
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_MERGE_VALUES %0(s32), %0(s32)
%2:gpr(s32), %3:gpr(s32) = G_UNMERGE_VALUES %1(s64)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

10
test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
View File

@ -5,7 +5,7 @@ legalized: true
registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_large_merge
; CHECK: registers:
@ -13,10 +13,10 @@ body: |
; CHECK: - { id: 1, class: gpr
; CHECK: - { id: 2, class: gpr
; CHECK: - { id: 3, class: fpr
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(p0) = COPY %x2
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(p0) = COPY $x2
%3:_(s128) = G_MERGE_VALUES %0, %1
%4:_(s64) = G_TRUNC %3
%d0 = COPY %4
$d0 = COPY %4
...

12
test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
View File

@ -34,11 +34,11 @@ legalized: true
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
body: |
bb.0:
liveins: %w0
%0:_(s32) = COPY %w0
; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
liveins: $w0
%0:_(s32) = COPY $w0
; CHECK: DBG_VALUE debug-use %0(s32), debug-use $noreg, !7, !DIExpression(), debug-location !9
DBG_VALUE debug-use %0(s32), debug-use $noreg, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
...

262
test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
View File

@ -80,11 +80,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_add_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_ADD %0, %0
...
@ -96,11 +96,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_add_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[ADD:%[0-9]+]]:fpr(<4 x s32>) = G_ADD [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_ADD %0, %0
...
@ -112,11 +112,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sub_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[SUB:%[0-9]+]]:gpr(s32) = G_SUB [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_SUB %0, %0
...
@ -128,11 +128,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_sub_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[SUB:%[0-9]+]]:fpr(<4 x s32>) = G_SUB [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_SUB %0, %0
...
@ -144,11 +144,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_mul_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[MUL:%[0-9]+]]:gpr(s32) = G_MUL [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_MUL %0, %0
...
@ -160,11 +160,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_mul_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[MUL:%[0-9]+]]:fpr(<4 x s32>) = G_MUL [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_MUL %0, %0
...
@ -176,11 +176,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_and_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_AND %0, %0
...
@ -192,11 +192,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_and_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[AND:%[0-9]+]]:fpr(<4 x s32>) = G_AND [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_AND %0, %0
...
@ -208,11 +208,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_or_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[OR:%[0-9]+]]:gpr(s32) = G_OR [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_OR %0, %0
...
@ -224,11 +224,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_or_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[OR:%[0-9]+]]:fpr(<4 x s32>) = G_OR [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_OR %0, %0
...
@ -240,11 +240,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_xor_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[XOR:%[0-9]+]]:gpr(s32) = G_XOR [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_XOR %0, %0
...
@ -256,11 +256,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_xor_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[XOR:%[0-9]+]]:fpr(<4 x s32>) = G_XOR [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_XOR %0, %0
...
@ -272,11 +272,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_shl_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[SHL:%[0-9]+]]:gpr(s32) = G_SHL [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_SHL %0, %0
...
@ -288,11 +288,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
liveins: $q0
; CHECK-LABEL: name: test_shl_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[SHL:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[COPY]], [[COPY]]
%0(<4 x s32>) = COPY %q0
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_SHL %0, %0
...
@ -304,11 +304,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_lshr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[LSHR:%[0-9]+]]:gpr(s32) = G_LSHR [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_LSHR %0, %0
...
@ -320,11 +320,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_ashr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[ASHR:%[0-9]+]]:gpr(s32) = G_ASHR [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_ASHR %0, %0
...
@ -336,11 +336,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sdiv_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[SDIV:%[0-9]+]]:gpr(s32) = G_SDIV [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_SDIV %0, %0
...
@ -352,11 +352,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_udiv_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[UDIV:%[0-9]+]]:gpr(s32) = G_UDIV [[COPY]], [[COPY]]
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_UDIV %0, %0
...
@ -368,11 +368,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_anyext_s64_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[ANYEXT:%[0-9]+]]:gpr(s64) = G_ANYEXT [[COPY]](s32)
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s64) = G_ANYEXT %0
...
@ -384,11 +384,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sext_s64_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[SEXT:%[0-9]+]]:gpr(s64) = G_SEXT [[COPY]](s32)
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s64) = G_SEXT %0
...
@ -400,11 +400,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_zext_s64_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[ZEXT:%[0-9]+]]:gpr(s64) = G_ZEXT [[COPY]](s32)
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s64) = G_ZEXT %0
...
@ -416,11 +416,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_trunc_s32_s64
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s32) = G_TRUNC [[COPY]](s64)
%0(s64) = COPY %x0
%0(s64) = COPY $x0
%1(s32) = G_TRUNC %0
...
@ -457,12 +457,12 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_icmp_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_ICMP intpred(ne), %0, %0
%2(s1) = G_TRUNC %1(s32)
...
@ -476,12 +476,12 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_icmp_p0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
%0(p0) = COPY %x0
%0(p0) = COPY $x0
%1(s32) = G_ICMP intpred(ne), %0, %0
%2(s1) = G_TRUNC %1(s32)
...
@ -508,11 +508,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_ptrtoint_s64_p0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
; CHECK: [[PTRTOINT:%[0-9]+]]:gpr(s64) = G_PTRTOINT [[COPY]](p0)
%0(p0) = COPY %x0
%0(p0) = COPY $x0
%1(s64) = G_PTRTOINT %0
...
@ -524,11 +524,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_inttoptr_p0_s64
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
; CHECK: [[INTTOPTR:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[COPY]](s64)
%0(s64) = COPY %x0
%0(s64) = COPY $x0
%1(p0) = G_INTTOPTR %0
...
@ -540,11 +540,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_load_s32_p0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4)
%0(p0) = COPY %x0
%0(p0) = COPY $x0
%1(s32) = G_LOAD %0 :: (load 4)
...
@ -556,13 +556,13 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: test_store_s32_p0
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store 4)
%0(p0) = COPY %x0
%1(s32) = COPY %w1
%0(p0) = COPY $x0
%1(s32) = COPY $w1
G_STORE %1, %0 :: (store 4)
...
@ -574,11 +574,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fadd_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[COPY]]
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_FADD %0, %0
...
@ -590,11 +590,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fsub_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FSUB:%[0-9]+]]:fpr(s32) = G_FSUB [[COPY]], [[COPY]]
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_FSUB %0, %0
...
@ -606,11 +606,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fmul_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FMUL:%[0-9]+]]:fpr(s32) = G_FMUL [[COPY]], [[COPY]]
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_FMUL %0, %0
...
@ -622,11 +622,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fdiv_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FDIV:%[0-9]+]]:fpr(s32) = G_FDIV [[COPY]], [[COPY]]
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_FDIV %0, %0
...
@ -638,11 +638,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fpext_s64_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FPEXT:%[0-9]+]]:fpr(s64) = G_FPEXT [[COPY]](s32)
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s64) = G_FPEXT %0
...
@ -654,11 +654,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: test_fptrunc_s32_s64
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[FPTRUNC:%[0-9]+]]:fpr(s32) = G_FPTRUNC [[COPY]](s64)
%0(s64) = COPY %d0
%0(s64) = COPY $d0
%1(s32) = G_FPTRUNC %0
...
@ -683,12 +683,12 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fcmp_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[FCMP]](s32)
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_FCMP floatpred(olt), %0, %0
%2(s1) = G_TRUNC %1(s32)
...
@ -701,11 +701,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s64_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[SITOFP:%[0-9]+]]:fpr(s64) = G_SITOFP [[COPY]](s32)
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s64) = G_SITOFP %0
...
@ -717,11 +717,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: test_uitofp_s32_s64
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
; CHECK: [[UITOFP:%[0-9]+]]:fpr(s32) = G_UITOFP [[COPY]](s64)
%0(s64) = COPY %x0
%0(s64) = COPY $x0
%1(s32) = G_UITOFP %0
...
@ -733,11 +733,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: test_fptosi_s64_s32
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[COPY]](s32)
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s64) = G_FPTOSI %0
...
@ -749,11 +749,11 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: test_fptoui_s32_s64
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[FPTOUI:%[0-9]+]]:gpr(s32) = G_FPTOUI [[COPY]](s64)
%0(s64) = COPY %d0
%0(s64) = COPY $d0
%1(s32) = G_FPTOUI %0
...
@ -772,10 +772,10 @@ body: |
; CHECK-LABEL: name: test_gphi_ptr
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: %w2, %x0, %x1
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %x1
; CHECK: [[COPY2:%[0-9]+]]:gpr(s32) = COPY %w2
; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY2]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: G_BR %bb.2
@ -783,15 +783,15 @@ body: |
; CHECK: successors: %bb.2(0x80000000)
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:gpr(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
; CHECK: %x0 = COPY [[PHI]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[PHI]](p0)
; CHECK: RET_ReallyLR implicit $x0
bb.0:
successors: %bb.1, %bb.2
liveins: %w2, %x0, %x1
liveins: $w2, $x0, $x1
%0(p0) = COPY %x0
%1(p0) = COPY %x1
%4(s32) = COPY %w2
%0(p0) = COPY $x0
%1(p0) = COPY $x1
%4(s32) = COPY $w2
%2(s1) = G_TRUNC %4(s32)
G_BRCOND %2(s1), %bb.1
G_BR %bb.2
@ -802,7 +802,7 @@ body: |
bb.2:
%3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
%x0 = COPY %3(p0)
RET_ReallyLR implicit %x0
$x0 = COPY %3(p0)
RET_ReallyLR implicit $x0
...

4
test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
View File

@ -18,8 +18,8 @@ registers:
- { id: 0, class: dd }
body: |
bb.0:
liveins: %d0, %d1
liveins: $d0, $d1
%0 = REG_SEQUENCE %d0, %subreg.dsub0, %d1, %subreg.dsub1
%0 = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1
...

112
test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
View File

@ -25,17 +25,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_xchg_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: %x0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $x0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
name: atomicrmw_add_i64
@ -44,17 +44,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_add_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: %x0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $x0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
name: atomicrmw_add_i32
@ -63,17 +63,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_add_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -83,17 +83,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_sub_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -103,18 +103,18 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_and_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[CST]]
; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[CST]]
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -124,17 +124,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_or_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSETLW [[CST]], [[COPY]] :: (load store release 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -144,17 +144,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_xor_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDEORALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -164,17 +164,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_min_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMINALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -184,17 +184,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_max_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMAXALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -204,17 +204,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_umin_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMINALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -224,15 +224,15 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: atomicrmw_umax_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMAXALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 8 on %ir.addr)
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

462
test/CodeGen/AArch64/GlobalISel/select-binop.mir
View File

@ -70,17 +70,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: add_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[ADDWrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[ADDWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_ADD %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -96,17 +96,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: add_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[ADDXrr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ADDXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_ADD %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -121,16 +121,16 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: add_imm_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
; CHECK: %w0 = COPY [[ADDWri]]
%0(s32) = COPY %w0
; CHECK: $w0 = COPY [[ADDWri]]
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 1
%2(s32) = G_ADD %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -145,16 +145,16 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: add_imm_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
; CHECK: %x0 = COPY [[ADDXri]]
%0(s64) = COPY %x0
; CHECK: $x0 = COPY [[ADDXri]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i32 1
%2(s64) = G_ADD %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -171,22 +171,22 @@ body: |
; CHECK-LABEL: name: add_imm_s32_gpr_bb
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
; CHECK: %w0 = COPY [[ADDWri]]
; CHECK: $w0 = COPY [[ADDWri]]
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
successors: %bb.1
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 1
G_BR %bb.1
bb.1:
%2(s32) = G_ADD %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -202,17 +202,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: sub_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv
; CHECK: %w0 = COPY [[SUBSWrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: $w0 = COPY [[SUBSWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_SUB %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -228,17 +228,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: sub_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv
; CHECK: %x0 = COPY [[SUBSXrr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: $x0 = COPY [[SUBSXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_SUB %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -254,17 +254,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: or_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[ORRWrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[ORRWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_OR %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -280,17 +280,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: or_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[ORRXrr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ORRXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_OR %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -308,17 +308,17 @@ registers:
# on 64-bit width vector.
body: |
bb.0:
liveins: %d0, %d1
liveins: $d0, $d1
; CHECK-LABEL: name: or_v2s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
; CHECK: %d0 = COPY [[ORRv8i8_]]
%0(<2 x s32>) = COPY %d0
%1(<2 x s32>) = COPY %d1
; CHECK: $d0 = COPY [[ORRv8i8_]]
%0(<2 x s32>) = COPY $d0
%1(<2 x s32>) = COPY $d1
%2(<2 x s32>) = G_OR %0, %1
%d0 = COPY %2(<2 x s32>)
$d0 = COPY %2(<2 x s32>)
...
---
@ -334,17 +334,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: and_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[ANDWrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[ANDWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_AND %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -360,17 +360,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: and_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[ANDXrr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ANDXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_AND %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -386,17 +386,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: shl_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[LSLVWr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[LSLVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_SHL %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -412,17 +412,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: shl_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[LSLVXr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[LSLVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_SHL %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -438,17 +438,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: lshr_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[LSRVWr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[LSRVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_LSHR %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -464,17 +464,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: lshr_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[LSRVXr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[LSRVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_LSHR %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -490,17 +490,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: ashr_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[ASRVWr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[ASRVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_ASHR %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -516,17 +516,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: ashr_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[ASRVXr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[ASRVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_ASHR %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -543,17 +543,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: mul_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], %wzr
; CHECK: %w0 = COPY [[MADDWrrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
; CHECK: $w0 = COPY [[MADDWrrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_MUL %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -569,17 +569,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: mul_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], %xzr
; CHECK: %x0 = COPY [[MADDXrrr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
; CHECK: $x0 = COPY [[MADDXrrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_MUL %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -591,21 +591,21 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: mulh_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[SMULHrr]]
; CHECK: %x0 = COPY [[UMULHrr]]
%0:gpr(s64) = COPY %x0
%1:gpr(s64) = COPY %x1
; CHECK: $x0 = COPY [[SMULHrr]]
; CHECK: $x0 = COPY [[UMULHrr]]
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_SMULH %0, %1
%3:gpr(s64) = G_UMULH %0, %1
%x0 = COPY %2(s64)
%x0 = COPY %3(s64)
$x0 = COPY %2(s64)
$x0 = COPY %3(s64)
...
---
@ -621,17 +621,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: sdiv_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[SDIVWr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[SDIVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_SDIV %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -647,17 +647,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: sdiv_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[SDIVXr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[SDIVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_SDIV %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -673,17 +673,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: udiv_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[UDIVWr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[UDIVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_UDIV %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -699,17 +699,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: udiv_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[UDIVXr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[UDIVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_UDIV %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -725,17 +725,17 @@ registers:
body: |
bb.0:
liveins: %s0, %s1
liveins: $s0, $s1
; CHECK-LABEL: name: fadd_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
; CHECK: %s0 = COPY [[FADDSrr]]
%0(s32) = COPY %s0
%1(s32) = COPY %s1
; CHECK: $s0 = COPY [[FADDSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FADD %0, %1
%s0 = COPY %2(s32)
$s0 = COPY %2(s32)
...
---
@ -750,17 +750,17 @@ registers:
body: |
bb.0:
liveins: %d0, %d1
liveins: $d0, $d1
; CHECK-LABEL: name: fadd_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
; CHECK: %d0 = COPY [[FADDDrr]]
%0(s64) = COPY %d0
%1(s64) = COPY %d1
; CHECK: $d0 = COPY [[FADDDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FADD %0, %1
%d0 = COPY %2(s64)
$d0 = COPY %2(s64)
...
---
@ -775,17 +775,17 @@ registers:
body: |
bb.0:
liveins: %s0, %s1
liveins: $s0, $s1
; CHECK-LABEL: name: fsub_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
; CHECK: %s0 = COPY [[FSUBSrr]]
%0(s32) = COPY %s0
%1(s32) = COPY %s1
; CHECK: $s0 = COPY [[FSUBSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FSUB %0, %1
%s0 = COPY %2(s32)
$s0 = COPY %2(s32)
...
---
@ -800,17 +800,17 @@ registers:
body: |
bb.0:
liveins: %d0, %d1
liveins: $d0, $d1
; CHECK-LABEL: name: fsub_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
; CHECK: %d0 = COPY [[FSUBDrr]]
%0(s64) = COPY %d0
%1(s64) = COPY %d1
; CHECK: $d0 = COPY [[FSUBDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FSUB %0, %1
%d0 = COPY %2(s64)
$d0 = COPY %2(s64)
...
---
@ -825,17 +825,17 @@ registers:
body: |
bb.0:
liveins: %s0, %s1
liveins: $s0, $s1
; CHECK-LABEL: name: fmul_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
; CHECK: %s0 = COPY [[FMULSrr]]
%0(s32) = COPY %s0
%1(s32) = COPY %s1
; CHECK: $s0 = COPY [[FMULSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FMUL %0, %1
%s0 = COPY %2(s32)
$s0 = COPY %2(s32)
...
---
@ -850,17 +850,17 @@ registers:
body: |
bb.0:
liveins: %d0, %d1
liveins: $d0, $d1
; CHECK-LABEL: name: fmul_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
; CHECK: %d0 = COPY [[FMULDrr]]
%0(s64) = COPY %d0
%1(s64) = COPY %d1
; CHECK: $d0 = COPY [[FMULDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FMUL %0, %1
%d0 = COPY %2(s64)
$d0 = COPY %2(s64)
...
---
@ -875,17 +875,17 @@ registers:
body: |
bb.0:
liveins: %s0, %s1
liveins: $s0, $s1
; CHECK-LABEL: name: fdiv_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
; CHECK: %s0 = COPY [[FDIVSrr]]
%0(s32) = COPY %s0
%1(s32) = COPY %s1
; CHECK: $s0 = COPY [[FDIVSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FDIV %0, %1
%s0 = COPY %2(s32)
$s0 = COPY %2(s32)
...
---
@ -900,15 +900,15 @@ registers:
body: |
bb.0:
liveins: %d0, %d1
liveins: $d0, $d1
; CHECK-LABEL: name: fdiv_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
; CHECK: %d0 = COPY [[FDIVDrr]]
%0(s64) = COPY %d0
%1(s64) = COPY %d1
; CHECK: $d0 = COPY [[FDIVDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FDIV %0, %1
%d0 = COPY %2(s64)
$d0 = COPY %2(s64)
...

10
test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
View File

@ -6,13 +6,13 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: bitcast_v2f32_to_s64
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $x0
; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
; CHECK: %x0 = COPY [[REV]]
%0:fpr(<2 x s32>) = COPY %x0
; CHECK: $x0 = COPY [[REV]]
%0:fpr(<2 x s32>) = COPY $x0
%1:fpr(s64) = G_BITCAST %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...

100
test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
View File

@ -26,14 +26,14 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: bitcast_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
; CHECK: %w0 = COPY [[COPY]]
%0(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
; CHECK: $w0 = COPY [[COPY]]
%0(s32) = COPY $w0
%1(s32) = G_BITCAST %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -47,14 +47,14 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: bitcast_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: %s0 = COPY [[COPY]]
%0(s32) = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: $s0 = COPY [[COPY]]
%0(s32) = COPY $s0
%1(s32) = G_BITCAST %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -68,15 +68,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: bitcast_s32_gpr_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK: %s0 = COPY [[COPY1]]
%0(s32) = COPY %w0
; CHECK: $s0 = COPY [[COPY1]]
%0(s32) = COPY $w0
%1(s32) = G_BITCAST %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -90,15 +90,15 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: bitcast_s32_fpr_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; CHECK: %w0 = COPY [[COPY1]]
%0(s32) = COPY %s0
; CHECK: $w0 = COPY [[COPY1]]
%0(s32) = COPY $s0
%1(s32) = G_BITCAST %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -112,14 +112,14 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: bitcast_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
; CHECK: %x0 = COPY [[COPY]]
%0(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
; CHECK: $x0 = COPY [[COPY]]
%0(s64) = COPY $x0
%1(s64) = G_BITCAST %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -133,14 +133,14 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: bitcast_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: %d0 = COPY [[COPY]]
%0(s64) = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: $d0 = COPY [[COPY]]
%0(s64) = COPY $d0
%1(s64) = G_BITCAST %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -153,15 +153,15 @@ registers:
- { id: 1, class: fpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: bitcast_s64_gpr_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
; CHECK: %d0 = COPY [[COPY1]]
%0(s64) = COPY %x0
; CHECK: $d0 = COPY [[COPY1]]
%0(s64) = COPY $x0
%1(s64) = G_BITCAST %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -175,15 +175,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: bitcast_s64_fpr_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
; CHECK: %x0 = COPY [[COPY1]]
%0(s64) = COPY %d0
; CHECK: $x0 = COPY [[COPY1]]
%0(s64) = COPY $d0
%1(s64) = G_BITCAST %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -197,14 +197,14 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: bitcast_s64_v2f32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: %x0 = COPY [[COPY]]
%0(s64) = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: $x0 = COPY [[COPY]]
%0(s64) = COPY $d0
%1(<2 x s32>) = G_BITCAST %0
%x0 = COPY %1(<2 x s32>)
$x0 = COPY %1(<2 x s32>)
...
---
@ -218,12 +218,12 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: bitcast_s64_v8i8_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: %x0 = COPY [[COPY]]
%0(s64) = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: $x0 = COPY [[COPY]]
%0(s64) = COPY $d0
%1(<8 x s8>) = G_BITCAST %0
%x0 = COPY %1(<8 x s8>)
$x0 = COPY %1(<8 x s8>)
...

6
test/CodeGen/AArch64/GlobalISel/select-br.mir
View File

@ -42,7 +42,7 @@ registers:
body: |
bb.0:
successors: %bb.0, %bb.1
%1(s32) = COPY %w0
%1(s32) = COPY $w0
%0(s1) = G_TRUNC %1
G_BRCOND %0(s1), %bb.1
G_BR %bb.0
@ -61,12 +61,12 @@ registers:
# CHECK: body:
# CHECK: bb.0:
# CHECK: %0:gpr64 = COPY %x0
# CHECK: %0:gpr64 = COPY $x0
# CHECK: BR %0
body: |
bb.0:
successors: %bb.0, %bb.1
%0(p0) = COPY %x0
%0(p0) = COPY $x0
G_BRINDIRECT %0(p0)
bb.1:

20
test/CodeGen/AArch64/GlobalISel/select-bswap.mir
View File

@ -19,15 +19,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: bswap_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
; CHECK: %w0 = COPY [[REVWr]]
%0(s32) = COPY %w0
; CHECK: $w0 = COPY [[REVWr]]
%0(s32) = COPY $w0
%1(s32) = G_BSWAP %0
%w0 = COPY %1
$w0 = COPY %1
...
---
@ -41,13 +41,13 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: bswap_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
; CHECK: %x0 = COPY [[REVXr]]
%0(s64) = COPY %x0
; CHECK: $x0 = COPY [[REVXr]]
%0(s64) = COPY $x0
%1(s64) = G_BSWAP %0
%x0 = COPY %1
$x0 = COPY %1
...

24
test/CodeGen/AArch64/GlobalISel/select-cbz.mir
View File

@ -15,15 +15,15 @@ regBankSelected: true
# CHECK: body:
# CHECK: bb.0:
# CHECK: %0:gpr32 = COPY %w0
# CHECK: %0:gpr32 = COPY $w0
# CHECK: CBZW %0, %bb.1
# CHECK: B %bb.0
body: |
bb.0:
liveins: %w0
liveins: $w0
successors: %bb.0, %bb.1
%0:gpr(s32) = COPY %w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = G_CONSTANT i32 0
%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
%3:gpr(s1) = G_TRUNC %2(s32)
@ -41,15 +41,15 @@ regBankSelected: true
# CHECK: body:
# CHECK: bb.0:
# CHECK: %0:gpr64 = COPY %x0
# CHECK: %0:gpr64 = COPY $x0
# CHECK: CBZX %0, %bb.1
# CHECK: B %bb.0
body: |
bb.0:
liveins: %x0
liveins: $x0
successors: %bb.0, %bb.1
%0:gpr(s64) = COPY %x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 0
%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
%3:gpr(s1) = G_TRUNC %2(s32)
@ -67,15 +67,15 @@ regBankSelected: true
# CHECK: body:
# CHECK: bb.0:
# CHECK: %0:gpr32 = COPY %w0
# CHECK: %0:gpr32 = COPY $w0
# CHECK: CBNZW %0, %bb.1
# CHECK: B %bb.0
body: |
bb.0:
liveins: %w0
liveins: $w0
successors: %bb.0, %bb.1
%0:gpr(s32) = COPY %w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = G_CONSTANT i32 0
%2:gpr(s32) = G_ICMP intpred(ne), %0, %1
%3:gpr(s1) = G_TRUNC %2(s32)
@ -93,15 +93,15 @@ regBankSelected: true
# CHECK: body:
# CHECK: bb.0:
# CHECK: %0:gpr64 = COPY %x0
# CHECK: %0:gpr64 = COPY $x0
# CHECK: CBNZX %0, %bb.1
# CHECK: B %bb.0
body: |
bb.0:
liveins: %x0
liveins: $x0
successors: %bb.0, %bb.1
%0:gpr(s64) = COPY %x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 0
%2:gpr(s32) = G_ICMP intpred(ne), %0, %1
%3:gpr(s1) = G_TRUNC %2(s32)

20
test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
View File

@ -15,19 +15,19 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = CASW [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: %w0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 0
%2:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
...
---
@ -37,17 +37,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = CASX [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: %x0 = COPY [[RES]]
%0:gpr(p0) = COPY %x0
; CHECK: $x0 = COPY [[RES]]
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 0
%2:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
%x0 = COPY %3(s64)
$x0 = COPY %3(s64)
...

24
test/CodeGen/AArch64/GlobalISel/select-constant.mir
View File

@ -24,9 +24,9 @@ body: |
bb.0:
; CHECK-LABEL: name: const_s32
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
; CHECK: %w0 = COPY [[MOVi32imm]]
; CHECK: $w0 = COPY [[MOVi32imm]]
%0(s32) = G_CONSTANT i32 42
%w0 = COPY %0(s32)
$w0 = COPY %0(s32)
...
---
@ -40,9 +40,9 @@ body: |
bb.0:
; CHECK-LABEL: name: const_s64
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
; CHECK: %x0 = COPY [[MOVi64imm]]
; CHECK: $x0 = COPY [[MOVi64imm]]
%0(s64) = G_CONSTANT i64 1234567890123
%x0 = COPY %0(s64)
$x0 = COPY %0(s64)
...
---
@ -57,9 +57,9 @@ body: |
; CHECK-LABEL: name: fconst_s32
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1080033280
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
; CHECK: %s0 = COPY [[COPY]]
; CHECK: $s0 = COPY [[COPY]]
%0(s32) = G_FCONSTANT float 3.5
%s0 = COPY %0(s32)
$s0 = COPY %0(s32)
...
---
@ -74,9 +74,9 @@ body: |
; CHECK-LABEL: name: fconst_s64
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 4607182418800017408
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVi64imm]]
; CHECK: %d0 = COPY [[COPY]]
; CHECK: $d0 = COPY [[COPY]]
%0(s64) = G_FCONSTANT double 1.0
%d0 = COPY %0(s64)
$d0 = COPY %0(s64)
...
---
@ -90,9 +90,9 @@ body: |
bb.0:
; CHECK-LABEL: name: fconst_s32_0
; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
; CHECK: %s0 = COPY [[FMOVS0_]]
; CHECK: $s0 = COPY [[FMOVS0_]]
%0(s32) = G_FCONSTANT float 0.0
%s0 = COPY %0(s32)
$s0 = COPY %0(s32)
...
---
@ -106,7 +106,7 @@ body: |
bb.0:
; CHECK-LABEL: name: fconst_s64_0
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK: %x0 = COPY [[FMOVD0_]]
; CHECK: $x0 = COPY [[FMOVD0_]]
%0(s64) = G_FCONSTANT double 0.0
%x0 = COPY %0(s64)
$x0 = COPY %0(s64)
...

22
test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
View File

@ -41,16 +41,16 @@ legalized: true
regBankSelected: true
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_dbg_value
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
; CHECK: %w0 = COPY [[ADDWrr]]
; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use %noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[ADDWrr]]
; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use $noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = G_ADD %0, %0
%w0 = COPY %1(s32)
DBG_VALUE debug-use %1(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
$w0 = COPY %1(s32)
DBG_VALUE debug-use %1(s32), debug-use $noreg, !7, !DIExpression(), debug-location !9
...
---
@ -59,10 +59,10 @@ legalized: true
regBankSelected: true
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_dbg_value_dead
; CHECK-NOT: COPY
; CHECK: DBG_VALUE debug-use %noreg, debug-use %noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY %w0
DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE debug-use $noreg, debug-use $noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY $w0
DBG_VALUE debug-use %0(s32), debug-use $noreg, !7, !DIExpression(), debug-location !9
...

18
test/CodeGen/AArch64/GlobalISel/select-fma.mir
View File

@ -20,17 +20,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1, %w2
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: FMADDSrrr_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %w1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY %w2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $w2
; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: %w0 = COPY [[FMADDSrrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
%2(s32) = COPY %w2
; CHECK: $w0 = COPY [[FMADDSrrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = COPY $w2
%3(s32) = G_FMA %0, %1, %2
%w0 = COPY %3
$w0 = COPY %3
...

220
test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
View File

@ -44,15 +44,15 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: fptrunc_s16_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
; CHECK: %h0 = COPY [[FCVTHSr]]
%0(s32) = COPY %s0
; CHECK: $h0 = COPY [[FCVTHSr]]
%0(s32) = COPY $s0
%1(s16) = G_FPTRUNC %0
%h0 = COPY %1(s16)
$h0 = COPY %1(s16)
...
---
@ -66,15 +66,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fptrunc_s16_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
; CHECK: %h0 = COPY [[FCVTHDr]]
%0(s64) = COPY %d0
; CHECK: $h0 = COPY [[FCVTHDr]]
%0(s64) = COPY $d0
%1(s16) = G_FPTRUNC %0
%h0 = COPY %1(s16)
$h0 = COPY %1(s16)
...
---
@ -88,15 +88,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fptrunc_s32_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
; CHECK: %s0 = COPY [[FCVTSDr]]
%0(s64) = COPY %d0
; CHECK: $s0 = COPY [[FCVTSDr]]
%0(s64) = COPY $d0
%1(s32) = G_FPTRUNC %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -110,15 +110,15 @@ registers:
body: |
bb.0:
liveins: %h0
liveins: $h0
; CHECK-LABEL: name: fpext_s32_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
; CHECK: %s0 = COPY [[FCVTSHr]]
%0(s16) = COPY %h0
; CHECK: $s0 = COPY [[FCVTSHr]]
%0(s16) = COPY $h0
%1(s32) = G_FPEXT %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -132,15 +132,15 @@ registers:
body: |
bb.0:
liveins: %h0
liveins: $h0
; CHECK-LABEL: name: fpext_s64_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
; CHECK: %d0 = COPY [[FCVTDHr]]
%0(s16) = COPY %h0
; CHECK: $d0 = COPY [[FCVTDHr]]
%0(s16) = COPY $h0
%1(s64) = G_FPEXT %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -154,15 +154,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fpext_s64_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
; CHECK: %d0 = COPY [[FCVTDSr]]
%0(s32) = COPY %s0
; CHECK: $d0 = COPY [[FCVTDSr]]
%0(s32) = COPY $s0
%1(s64) = G_FPEXT %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -176,15 +176,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sitofp_s32_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
; CHECK: %s0 = COPY [[SCVTFUWSri]]
%0(s32) = COPY %w0
; CHECK: $s0 = COPY [[SCVTFUWSri]]
%0(s32) = COPY $w0
%1(s32) = G_SITOFP %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -198,15 +198,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: sitofp_s32_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
; CHECK: %s0 = COPY [[SCVTFUXSri]]
%0(s64) = COPY %x0
; CHECK: $s0 = COPY [[SCVTFUXSri]]
%0(s64) = COPY $x0
%1(s32) = G_SITOFP %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -220,15 +220,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sitofp_s64_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
; CHECK: %d0 = COPY [[SCVTFUWDri]]
%0(s32) = COPY %w0
; CHECK: $d0 = COPY [[SCVTFUWDri]]
%0(s32) = COPY $w0
%1(s64) = G_SITOFP %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -242,15 +242,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: sitofp_s64_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
; CHECK: %d0 = COPY [[SCVTFUXDri]]
%0(s64) = COPY %x0
; CHECK: $d0 = COPY [[SCVTFUXDri]]
%0(s64) = COPY $x0
%1(s64) = G_SITOFP %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -264,15 +264,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: uitofp_s32_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
; CHECK: %s0 = COPY [[UCVTFUWSri]]
%0(s32) = COPY %w0
; CHECK: $s0 = COPY [[UCVTFUWSri]]
%0(s32) = COPY $w0
%1(s32) = G_UITOFP %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -286,15 +286,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: uitofp_s32_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
; CHECK: %s0 = COPY [[UCVTFUXSri]]
%0(s64) = COPY %x0
; CHECK: $s0 = COPY [[UCVTFUXSri]]
%0(s64) = COPY $x0
%1(s32) = G_UITOFP %0
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -308,15 +308,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: uitofp_s64_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
; CHECK: %d0 = COPY [[UCVTFUWDri]]
%0(s32) = COPY %w0
; CHECK: $d0 = COPY [[UCVTFUWDri]]
%0(s32) = COPY $w0
%1(s64) = G_UITOFP %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -330,15 +330,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: uitofp_s64_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
; CHECK: %d0 = COPY [[UCVTFUXDri]]
%0(s64) = COPY %x0
; CHECK: $d0 = COPY [[UCVTFUXDri]]
%0(s64) = COPY $x0
%1(s64) = G_UITOFP %0
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -352,15 +352,15 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: fptosi_s32_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
; CHECK: %w0 = COPY [[FCVTZSUWSr]]
%0(s32) = COPY %s0
; CHECK: $w0 = COPY [[FCVTZSUWSr]]
%0(s32) = COPY $s0
%1(s32) = G_FPTOSI %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -374,15 +374,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fptosi_s32_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
; CHECK: %w0 = COPY [[FCVTZSUWDr]]
%0(s64) = COPY %d0
; CHECK: $w0 = COPY [[FCVTZSUWDr]]
%0(s64) = COPY $d0
%1(s32) = G_FPTOSI %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -396,15 +396,15 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: fptosi_s64_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
; CHECK: %x0 = COPY [[FCVTZSUXSr]]
%0(s32) = COPY %s0
; CHECK: $x0 = COPY [[FCVTZSUXSr]]
%0(s32) = COPY $s0
%1(s64) = G_FPTOSI %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -418,15 +418,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fptosi_s64_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
; CHECK: %x0 = COPY [[FCVTZSUXDr]]
%0(s64) = COPY %d0
; CHECK: $x0 = COPY [[FCVTZSUXDr]]
%0(s64) = COPY $d0
%1(s64) = G_FPTOSI %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -440,15 +440,15 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: fptoui_s32_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
; CHECK: %w0 = COPY [[FCVTZUUWSr]]
%0(s32) = COPY %s0
; CHECK: $w0 = COPY [[FCVTZUUWSr]]
%0(s32) = COPY $s0
%1(s32) = G_FPTOUI %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -462,15 +462,15 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fptoui_s32_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
; CHECK: %w0 = COPY [[FCVTZUUWDr]]
%0(s64) = COPY %d0
; CHECK: $w0 = COPY [[FCVTZUUWDr]]
%0(s64) = COPY $d0
%1(s32) = G_FPTOUI %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -484,15 +484,15 @@ registers:
body: |
bb.0:
liveins: %s0
liveins: $s0
; CHECK-LABEL: name: fptoui_s64_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
; CHECK: %x0 = COPY [[FCVTZUUXSr]]
%0(s32) = COPY %s0
; CHECK: $x0 = COPY [[FCVTZUUXSr]]
%0(s32) = COPY $s0
%1(s64) = G_FPTOUI %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -506,13 +506,13 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: fptoui_s64_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
; CHECK: %x0 = COPY [[FCVTZUUXDr]]
%0(s64) = COPY %d0
; CHECK: $x0 = COPY [[FCVTZUUXDr]]
%0(s64) = COPY $d0
%1(s64) = G_FPTOUI %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...

10
test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
View File

@ -39,12 +39,12 @@ body: |
; CHECK: [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @foo2, 32
; CHECK: [[MOVKXi5:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @foo2, 48
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[MOVKXi5]]
; CHECK: STRWui %wzr, %stack.0.retval, 0 :: (store 4 into %ir.retval)
; CHECK: STRWui $wzr, %stack.0.retval, 0 :: (store 4 into %ir.retval)
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0)`)
; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0)`)
; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; CHECK: %w0 = COPY [[ADDWrr]]
; CHECK: RET_ReallyLR implicit %w0
; CHECK: $w0 = COPY [[ADDWrr]]
; CHECK: RET_ReallyLR implicit $w0
%1:gpr(s32) = G_CONSTANT i32 0
%4:gpr(p0) = G_GLOBAL_VALUE @foo1
%3:gpr(p0) = COPY %4(p0)
@ -55,7 +55,7 @@ body: |
%2:gpr(s32) = G_LOAD %3(p0) :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0)`)
%5:gpr(s32) = G_LOAD %6(p0) :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0)`)
%8:gpr(s32) = G_ADD %2, %5
%w0 = COPY %8(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %8(s32)
RET_ReallyLR implicit $w0
...

12
test/CodeGen/AArch64/GlobalISel/select-imm.mir
View File

@ -20,13 +20,13 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: imm_s32_gpr
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
; CHECK: %w0 = COPY [[MOVi32imm]]
; CHECK: $w0 = COPY [[MOVi32imm]]
%0(s32) = G_CONSTANT i32 -1234
%w0 = COPY %0(s32)
$w0 = COPY %0(s32)
...
---
@ -40,11 +40,11 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: imm_s64_gpr
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234
; CHECK: %x0 = COPY [[MOVi64imm]]
; CHECK: $x0 = COPY [[MOVi64imm]]
%0(s64) = G_CONSTANT i64 1234
%x0 = COPY %0(s64)
$x0 = COPY %0(s64)
...

4
test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
View File

@ -20,8 +20,8 @@ body: |
; CHECK-LABEL: name: implicit_def
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
; CHECK: %w0 = COPY [[ADDWrr]]
; CHECK: $w0 = COPY [[ADDWrr]]
%0(s32) = G_IMPLICIT_DEF
%1(s32) = G_ADD %0, %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...

16
test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
View File

@ -8,9 +8,9 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
%0:gpr(s32) = COPY %w0
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_IMPLICIT_DEF
@ -23,8 +23,8 @@ body: |
; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31
%3:gpr(s64) = G_INSERT %1, %0, 13
%x0 = COPY %2
%x1 = COPY %3
$x0 = COPY %2
$x1 = COPY %3
...
@ -36,9 +36,9 @@ regBankSelected: true
body: |
bb.0:
liveins: %x0
liveins: $x0
%0:gpr(s64) = COPY %x0
%0:gpr(s64) = COPY $x0
; CHECK: body:
; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 0, 31
@ -49,6 +49,6 @@ body: |
; CHECK: %2:gpr32 = COPY [[TMP]].sub_32
%2:gpr(s32) = G_EXTRACT %0, 13
%w0 = COPY %1
%w1 = COPY %2
$w0 = COPY %1
$w1 = COPY %2
...

100
test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
View File

@ -29,15 +29,15 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: anyext_s64_from_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
; CHECK: %x0 = COPY [[SUBREG_TO_REG]]
%0(s32) = COPY %w0
; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
%0(s32) = COPY $w0
%1(s64) = G_ANYEXT %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -51,16 +51,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: anyext_s32_from_s8
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK: %w0 = COPY [[COPY2]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY2]]
%2:gpr(s32) = COPY $w0
%0(s8) = G_TRUNC %2
%1(s32) = G_ANYEXT %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -74,16 +74,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: zext_s64_from_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
; CHECK: %x0 = COPY [[UBFMXri]]
%0(s32) = COPY %w0
; CHECK: $x0 = COPY [[UBFMXri]]
%0(s32) = COPY $w0
%1(s64) = G_ZEXT %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -97,16 +97,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: zext_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
; CHECK: %w0 = COPY [[UBFMWri]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[UBFMWri]]
%2:gpr(s32) = COPY $w0
%0(s16) = G_TRUNC %2
%1(s32) = G_ZEXT %0
%w0 = COPY %1
$w0 = COPY %1
...
---
@ -120,16 +120,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: zext_s32_from_s8
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
; CHECK: %w0 = COPY [[UBFMWri]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[UBFMWri]]
%2:gpr(s32) = COPY $w0
%0(s16) = G_TRUNC %2
%1(s32) = G_ZEXT %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -143,18 +143,18 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: zext_s16_from_s8
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
; CHECK: %w0 = COPY [[COPY2]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY2]]
%2:gpr(s32) = COPY $w0
%0(s8) = G_TRUNC %2
%1(s16) = G_ZEXT %0
%3:gpr(s32) = G_ANYEXT %1
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
...
---
@ -168,16 +168,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sext_s64_from_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
; CHECK: %x0 = COPY [[SBFMXri]]
%0(s32) = COPY %w0
; CHECK: $x0 = COPY [[SBFMXri]]
%0(s32) = COPY $w0
%1(s64) = G_SEXT %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -191,16 +191,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sext_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15
; CHECK: %w0 = COPY [[SBFMWri]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[SBFMWri]]
%2:gpr(s32) = COPY $w0
%0(s16) = G_TRUNC %2
%1(s32) = G_SEXT %0
%w0 = COPY %1
$w0 = COPY %1
...
---
@ -214,16 +214,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sext_s32_from_s8
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
; CHECK: %w0 = COPY [[SBFMWri]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[SBFMWri]]
%2:gpr(s32) = COPY $w0
%0(s8) = G_TRUNC %2
%1(s32) = G_SEXT %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -237,16 +237,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sext_s16_from_s8
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
; CHECK: %w0 = COPY [[COPY2]]
%2:gpr(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY2]]
%2:gpr(s32) = COPY $w0
%0(s8) = G_TRUNC %2
%1(s16) = G_SEXT %0
%3:gpr(s32) = G_ANYEXT %1
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
...

60
test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
View File

@ -22,13 +22,13 @@ registers:
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: inttoptr_p0_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
; CHECK: %x0 = COPY [[COPY]]
%0(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
; CHECK: $x0 = COPY [[COPY]]
%0(s64) = COPY $x0
%1(p0) = G_INTTOPTR %0
%x0 = COPY %1(p0)
$x0 = COPY %1(p0)
...
---
@ -41,13 +41,13 @@ registers:
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s64_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: %x0 = COPY [[COPY]]
%0(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: $x0 = COPY [[COPY]]
%0(p0) = COPY $x0
%1(s64) = G_PTRTOINT %0
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -60,14 +60,14 @@ registers:
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s32_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: %w0 = COPY [[COPY1]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
%1(s32) = G_PTRTOINT %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -80,16 +80,16 @@ registers:
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s16_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK: %w0 = COPY [[COPY2]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[COPY2]]
%0(p0) = COPY $x0
%1(s16) = G_PTRTOINT %0
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -102,16 +102,16 @@ registers:
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s8_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK: %w0 = COPY [[COPY2]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[COPY2]]
%0(p0) = COPY $x0
%1(s8) = G_PTRTOINT %0
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -124,14 +124,14 @@ registers:
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s1_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK: %w0 = COPY [[COPY2]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[COPY2]]
%0(p0) = COPY $x0
%1(s1) = G_PTRTOINT %0
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

2
test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
View File

@ -22,7 +22,7 @@ registers:
# CHECK: HINT 1
body: |
bb.0:
liveins: %w0
liveins: $w0
%0(s32) = G_CONSTANT i32 1
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.hint), %0

14
test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
View File

@ -21,15 +21,15 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: sdiv_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[SDIVWr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[SDIVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

14
test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
View File

@ -10,17 +10,17 @@ regBankSelected: true
body: |
bb.0:
liveins: %q0, %q1
liveins: $q0, $q1
; CHECK-LABEL: name: aesmc_aese
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY %q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY %q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[T0:%[0-9]+]]:fpr128 = AESErr [[COPY]], [[COPY1]]
; CHECK: [[T1:%[0-9]+]]:fpr128 = AESMCrrTied [[T0]]
; CHECK: %q0 = COPY [[T1]]
%0:fpr(<16 x s8>) = COPY %q0
%1:fpr(<16 x s8>) = COPY %q1
; CHECK: $q0 = COPY [[T1]]
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %0, %1
%3:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %2
%q0 = COPY %3(<16 x s8>)
$q0 = COPY %3(<16 x s8>)
...

206
test/CodeGen/AArch64/GlobalISel/select-load.mir
View File

@ -47,15 +47,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr)
; CHECK: %x0 = COPY [[LDRXui]]
%0(p0) = COPY %x0
; CHECK: $x0 = COPY [[LDRXui]]
%0(p0) = COPY $x0
%1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -69,15 +69,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr)
; CHECK: %w0 = COPY [[LDRWui]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[LDRWui]]
%0(p0) = COPY $x0
%1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -91,16 +91,16 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: %w0 = COPY [[LDRHHui]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[LDRHHui]]
%0(p0) = COPY $x0
%1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -114,16 +114,16 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
; CHECK: %w0 = COPY [[LDRBBui]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[LDRBBui]]
%0(p0) = COPY $x0
%1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -140,14 +140,14 @@ stack:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_fi_s64_gpr
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load 8)
; CHECK: %x0 = COPY [[LDRXui]]
; CHECK: $x0 = COPY [[LDRXui]]
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
%1(s64) = G_LOAD %0 :: (load 8)
%x0 = COPY %1(s64)
$x0 = COPY %1(s64)
...
---
@ -163,17 +163,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_128_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr)
; CHECK: %x0 = COPY [[LDRXui]]
%0(p0) = COPY %x0
; CHECK: $x0 = COPY [[LDRXui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 128
%2(p0) = G_GEP %0, %1
%3(s64) = G_LOAD %2 :: (load 8 from %ir.addr)
%x0 = COPY %3
$x0 = COPY %3
...
---
@ -189,17 +189,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_512_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr)
; CHECK: %w0 = COPY [[LDRWui]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[LDRWui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 512
%2(p0) = G_GEP %0, %1
%3(s32) = G_LOAD %2 :: (load 4 from %ir.addr)
%w0 = COPY %3
$w0 = COPY %3
...
---
@ -215,18 +215,18 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_64_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
; CHECK: %w0 = COPY [[LDRHHui]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[LDRHHui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 64
%2(p0) = G_GEP %0, %1
%3(s16) = G_LOAD %2 :: (load 2 from %ir.addr)
%4:gpr(s32) = G_ANYEXT %3
%w0 = COPY %4
$w0 = COPY %4
...
---
@ -242,18 +242,18 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_1_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
; CHECK: %w0 = COPY [[LDRBBui]]
%0(p0) = COPY %x0
; CHECK: $w0 = COPY [[LDRBBui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 1
%2(p0) = G_GEP %0, %1
%3(s8) = G_LOAD %2 :: (load 1 from %ir.addr)
%4:gpr(s32) = G_ANYEXT %3
%w0 = COPY %4
$w0 = COPY %4
...
---
@ -267,15 +267,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
; CHECK: %d0 = COPY [[LDRDui]]
%0(p0) = COPY %x0
; CHECK: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
%1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
%d0 = COPY %1(s64)
$d0 = COPY %1(s64)
...
---
@ -289,15 +289,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr)
; CHECK: %s0 = COPY [[LDRSui]]
%0(p0) = COPY %x0
; CHECK: $s0 = COPY [[LDRSui]]
%0(p0) = COPY $x0
%1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
%s0 = COPY %1(s32)
$s0 = COPY %1(s32)
...
---
@ -311,15 +311,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: %h0 = COPY [[LDRHui]]
%0(p0) = COPY %x0
; CHECK: $h0 = COPY [[LDRHui]]
%0(p0) = COPY $x0
%1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%h0 = COPY %1(s16)
$h0 = COPY %1(s16)
...
---
@ -333,15 +333,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_s8_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr)
; CHECK: %b0 = COPY [[LDRBui]]
%0(p0) = COPY %x0
; CHECK: $b0 = COPY [[LDRBui]]
%0(p0) = COPY $x0
%1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%b0 = COPY %1(s8)
$b0 = COPY %1(s8)
...
---
@ -357,17 +357,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_8_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr)
; CHECK: %d0 = COPY [[LDRDui]]
%0(p0) = COPY %x0
; CHECK: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 8
%2(p0) = G_GEP %0, %1
%3(s64) = G_LOAD %2 :: (load 8 from %ir.addr)
%d0 = COPY %3
$d0 = COPY %3
...
---
@ -383,17 +383,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_16_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr)
; CHECK: %s0 = COPY [[LDRSui]]
%0(p0) = COPY %x0
; CHECK: $s0 = COPY [[LDRSui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 16
%2(p0) = G_GEP %0, %1
%3(s32) = G_LOAD %2 :: (load 4 from %ir.addr)
%s0 = COPY %3
$s0 = COPY %3
...
---
@ -409,17 +409,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_64_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr)
; CHECK: %h0 = COPY [[LDRHui]]
%0(p0) = COPY %x0
; CHECK: $h0 = COPY [[LDRHui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 64
%2(p0) = G_GEP %0, %1
%3(s16) = G_LOAD %2 :: (load 2 from %ir.addr)
%h0 = COPY %3
$h0 = COPY %3
...
---
@ -435,17 +435,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_gep_32_s8_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr)
; CHECK: %b0 = COPY [[LDRBui]]
%0(p0) = COPY %x0
; CHECK: $b0 = COPY [[LDRBui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 32
%2(p0) = G_GEP %0, %1
%3(s8) = G_LOAD %2 :: (load 1 from %ir.addr)
%b0 = COPY %3
$b0 = COPY %3
...
---
name: load_v2s32
@ -458,15 +458,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: load_v2s32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
; CHECK: %d0 = COPY [[LDRDui]]
%0(p0) = COPY %x0
; CHECK: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
%1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr)
%d0 = COPY %1(<2 x s32>)
$d0 = COPY %1(<2 x s32>)
...
---
name: sextload_s32_from_s16
@ -475,16 +475,16 @@ regBankSelected: true
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: sextload_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: %w0 = COPY [[T0]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[T0]]
%0:gpr(p0) = COPY $x0
%1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%2:gpr(s32) = G_SEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -494,16 +494,16 @@ regBankSelected: true
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: zextload_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: %w0 = COPY [[T0]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[T0]]
%0:gpr(p0) = COPY $x0
%1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%2:gpr(s32) = G_ZEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -513,14 +513,14 @@ regBankSelected: true
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: aextload_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: %w0 = COPY [[T0]]
%0:gpr(p0) = COPY %x0
; CHECK: $w0 = COPY [[T0]]
%0:gpr(p0) = COPY $x0
%1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

12
test/CodeGen/AArch64/GlobalISel/select-mul.mir
View File

@ -13,22 +13,22 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; Make sure InstructionSelector is able to match a pattern
; with an SDNodeXForm, trunc_imm.
; def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),
; (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
; CHECK-LABEL: name: mul_i64_sext_imm32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], %xzr
; CHECK: %x0 = COPY [[SMADDLrrr]]
%0:gpr(s32) = COPY %w0
; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
; CHECK: $x0 = COPY [[SMADDLrrr]]
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_SEXT %0(s32)
%2:gpr(s64) = G_CONSTANT i64 3
%3:gpr(s64) = G_MUL %1, %2
%x0 = COPY %3(s64)
$x0 = COPY %3(s64)
...

18
test/CodeGen/AArch64/GlobalISel/select-muladd.mir
View File

@ -23,21 +23,21 @@ registers:
body: |
bb.0:
liveins: %x0, %w1, %w2
liveins: $x0, $w1, $w2
; CHECK-LABEL: name: SMADDLrrr_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY %w2
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: %x0 = COPY [[SMADDLrrr]]
%0(s64) = COPY %x0
%1(s32) = COPY %w1
%2(s32) = COPY %w2
; CHECK: $x0 = COPY [[SMADDLrrr]]
%0(s64) = COPY $x0
%1(s32) = COPY $w1
%2(s32) = COPY $w2
%3(s64) = G_SEXT %1
%4(s64) = G_SEXT %2
%5(s64) = G_MUL %3, %4
%6(s64) = G_ADD %0, %5
%x0 = COPY %6
$x0 = COPY %6
...

10
test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
View File

@ -20,14 +20,14 @@ registers:
body: |
bb.0:
liveins: %d0
liveins: $d0
; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 12
; CHECK: %d1 = COPY [[UCVTFd]]
%0(s64) = COPY %d0
; CHECK: $d1 = COPY [[UCVTFd]]
%0(s64) = COPY $d0
%1(s32) = G_CONSTANT i32 12
%2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1
%d1 = COPY %2(s64)
$d1 = COPY %2(s64)
...

20
test/CodeGen/AArch64/GlobalISel/select-phi.mir
View File

@ -51,11 +51,11 @@ liveins:
body: |
bb.1.entry:
successors: %bb.2.case1(0x40000000), %bb.3.case2(0x40000000)
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: test_phi
; CHECK: [[RES:%.*]]:gpr32 = PHI
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 0
%3(s32) = G_CONSTANT i32 1
%5(s32) = G_CONSTANT i32 2
@ -77,8 +77,8 @@ body: |
bb.4.return:
%7(s32) = G_PHI %4(s32), %bb.2.case1, %6(s32), %bb.3.case2
%w0 = COPY %7(s32)
RET_ReallyLR implicit %w0
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
@ -101,12 +101,12 @@ liveins:
body: |
bb.0:
successors: %bb.1, %bb.2
liveins: %w2, %x0, %x1
liveins: $w2, $x0, $x1
; CHECK-LABEL: name: test_phi_ptr
%0(p0) = COPY %x0
%1(p0) = COPY %x1
%6:gpr(s32) = COPY %w2
%0(p0) = COPY $x0
%1(p0) = COPY $x1
%6:gpr(s32) = COPY $w2
%2(s1) = G_TRUNC %6
G_BRCOND %2(s1), %bb.1
G_BR %bb.2
@ -118,7 +118,7 @@ body: |
bb.2:
; CHECK: %{{[0-9]+}}:gpr64 = PHI %{{[0-9]+}}, %bb.0, %{{[0-9]+}}, %bb.1
%3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
%x0 = COPY %3(p0)
RET_ReallyLR implicit %x0
$x0 = COPY %3(p0)
RET_ReallyLR implicit $x0
...

12
test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
View File

@ -50,17 +50,17 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.1.entry:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: main
; CHECK: liveins: %w0
; CHECK: liveins: $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[EONWrr:%[0-9]+]]:gpr32 = EONWrr [[COPY]], [[MOVi32imm]]
; CHECK: %w0 = COPY [[EONWrr]]
; CHECK: $w0 = COPY [[EONWrr]]
%0(s32) = G_CONSTANT i32 -1
%3(s32) = G_CONSTANT i32 1
%1(s32) = COPY %w0
%1(s32) = COPY $w0
%2(s32) = G_XOR %1, %0
%4(s32) = G_XOR %2, %3
%w0 = COPY %4(s32)
$w0 = COPY %4(s32)
...

152
test/CodeGen/AArch64/GlobalISel/select-store.mir
View File

@ -42,14 +42,14 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: store_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
%0(p0) = COPY %x0
%1(s64) = COPY %x1
%0(p0) = COPY $x0
%1(s64) = COPY $x1
G_STORE %1, %0 :: (store 8 into %ir.addr)
...
@ -65,14 +65,14 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: store_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
%0(p0) = COPY %x0
%1(s32) = COPY %w1
%0(p0) = COPY $x0
%1(s32) = COPY $w1
G_STORE %1, %0 :: (store 4 into %ir.addr)
...
@ -88,14 +88,14 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: store_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr)
%0(p0) = COPY %x0
%2:gpr(s32) = COPY %w1
%0(p0) = COPY $x0
%2:gpr(s32) = COPY $w1
%1(s16) = G_TRUNC %2
G_STORE %1, %0 :: (store 2 into %ir.addr)
@ -112,14 +112,14 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: store_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr)
%0(p0) = COPY %x0
%2:gpr(s32) = COPY %w1
%0(p0) = COPY $x0
%2:gpr(s32) = COPY $w1
%1(s8) = G_TRUNC %2
G_STORE %1, %0 :: (store 1 into %ir.addr)
@ -136,12 +136,12 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: store_zero_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: STRXui %xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
%0(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: STRXui $xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 0
G_STORE %1, %0 :: (store 8 into %ir.addr)
@ -158,12 +158,12 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: store_zero_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: STRWui %wzr, [[COPY]], 0 :: (store 4 into %ir.addr)
%0(p0) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: STRWui $wzr, [[COPY]], 0 :: (store 4 into %ir.addr)
%0(p0) = COPY $x0
%1(s32) = G_CONSTANT i32 0
G_STORE %1, %0 :: (store 4 into %ir.addr)
@ -183,12 +183,12 @@ stack:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: store_fi_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
%0(p0) = COPY %x0
%0(p0) = COPY $x0
%1(p0) = G_FRAME_INDEX %stack.0.ptr0
G_STORE %0, %1 :: (store 8)
...
@ -206,14 +206,14 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: store_gep_128_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store 8 into %ir.addr)
%0(p0) = COPY %x0
%1(s64) = COPY %x1
%0(p0) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_CONSTANT i64 128
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 8 into %ir.addr)
@ -232,14 +232,14 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: store_gep_512_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store 4 into %ir.addr)
%0(p0) = COPY %x0
%1(s32) = COPY %w1
%0(p0) = COPY $x0
%1(s32) = COPY $w1
%2(s64) = G_CONSTANT i64 512
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 4 into %ir.addr)
@ -258,14 +258,14 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: store_gep_64_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr)
%0(p0) = COPY %x0
%4:gpr(s32) = COPY %w1
%0(p0) = COPY $x0
%4:gpr(s32) = COPY $w1
%1(s16) = G_TRUNC %4
%2(s64) = G_CONSTANT i64 64
%3(p0) = G_GEP %0, %2
@ -285,14 +285,14 @@ registers:
body: |
bb.0:
liveins: %x0, %w1
liveins: $x0, $w1
; CHECK-LABEL: name: store_gep_1_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr)
%0(p0) = COPY %x0
%4:gpr(s32) = COPY %w1
%0(p0) = COPY $x0
%4:gpr(s32) = COPY $w1
%1(s8) = G_TRUNC %4
%2(s64) = G_CONSTANT i64 1
%3(p0) = G_GEP %0, %2
@ -310,14 +310,14 @@ registers:
body: |
bb.0:
liveins: %x0, %d1
liveins: $x0, $d1
; CHECK-LABEL: name: store_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
%0(p0) = COPY %x0
%1(s64) = COPY %d1
%0(p0) = COPY $x0
%1(s64) = COPY $d1
G_STORE %1, %0 :: (store 8 into %ir.addr)
...
@ -333,14 +333,14 @@ registers:
body: |
bb.0:
liveins: %x0, %s1
liveins: $x0, $s1
; CHECK-LABEL: name: store_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
%0(p0) = COPY %x0
%1(s32) = COPY %s1
%0(p0) = COPY $x0
%1(s32) = COPY $s1
G_STORE %1, %0 :: (store 4 into %ir.addr)
...
@ -358,14 +358,14 @@ registers:
body: |
bb.0:
liveins: %x0, %d1
liveins: $x0, $d1
; CHECK-LABEL: name: store_gep_8_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store 8 into %ir.addr)
%0(p0) = COPY %x0
%1(s64) = COPY %d1
%0(p0) = COPY $x0
%1(s64) = COPY $d1
%2(s64) = G_CONSTANT i64 8
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 8 into %ir.addr)
@ -384,14 +384,14 @@ registers:
body: |
bb.0:
liveins: %x0, %s1
liveins: $x0, $s1
; CHECK-LABEL: name: store_gep_8_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store 4 into %ir.addr)
%0(p0) = COPY %x0
%1(s32) = COPY %s1
%0(p0) = COPY $x0
%1(s32) = COPY $s1
%2(s64) = G_CONSTANT i64 8
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 4 into %ir.addr)
@ -407,14 +407,14 @@ registers:
body: |
bb.0:
liveins: %x0, %d1
liveins: $x0, $d1
; CHECK-LABEL: name: store_v2s32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
%0(p0) = COPY %x0
%1(<2 x s32>) = COPY %d1
%0(p0) = COPY $x0
%1(<2 x s32>) = COPY $d1
G_STORE %1, %0 :: (store 8 into %ir.addr)
...

30
test/CodeGen/AArch64/GlobalISel/select-trunc.mir
View File

@ -20,15 +20,15 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: trunc_s32_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
; CHECK: %w0 = COPY [[COPY1]]
%0(s64) = COPY %x0
; CHECK: $w0 = COPY [[COPY1]]
%0(s64) = COPY $x0
%1(s32) = G_TRUNC %0
%w0 = COPY %1(s32)
$w0 = COPY %1(s32)
...
---
@ -42,17 +42,17 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: trunc_s8_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK: %w0 = COPY [[COPY2]]
%0(s64) = COPY %x0
; CHECK: $w0 = COPY [[COPY2]]
%0(s64) = COPY $x0
%1(s8) = G_TRUNC %0
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -66,14 +66,14 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: trunc_s1_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK: %w0 = COPY [[COPY2]]
%0(s32) = COPY %w0
; CHECK: $w0 = COPY [[COPY2]]
%0(s32) = COPY $w0
%1(s1) = G_TRUNC %0
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

64
test/CodeGen/AArch64/GlobalISel/select-xor.mir
View File

@ -26,17 +26,17 @@ registers:
body: |
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
; CHECK-LABEL: name: xor_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[EORWrr]]
%0(s32) = COPY %w0
%1(s32) = COPY %w1
; CHECK: $w0 = COPY [[EORWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_XOR %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -52,17 +52,17 @@ registers:
body: |
bb.0:
liveins: %x0, %x1
liveins: $x0, $x1
; CHECK-LABEL: name: xor_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[EORXrr:%[0-9]+]]:gpr64 = EORXrr [[COPY]], [[COPY1]]
; CHECK: %x0 = COPY [[EORXrr]]
%0(s64) = COPY %x0
%1(s64) = COPY %x1
; CHECK: $x0 = COPY [[EORXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_XOR %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -79,16 +79,16 @@ registers:
body: |
bb.0:
liveins: %w0
liveins: $w0
; CHECK-LABEL: name: xor_constant_n1_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[COPY]]
; CHECK: %w0 = COPY [[ORNWrr]]
%0(s32) = COPY %w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
; CHECK: $w0 = COPY [[ORNWrr]]
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_XOR %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...
---
@ -104,16 +104,16 @@ registers:
body: |
bb.0:
liveins: %x0
liveins: $x0
; CHECK-LABEL: name: xor_constant_n1_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
; CHECK: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr %xzr, [[COPY]]
; CHECK: %x0 = COPY [[ORNXrr]]
%0(s64) = COPY %x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY]]
; CHECK: $x0 = COPY [[ORNXrr]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 -1
%2(s64) = G_XOR %0, %1
%x0 = COPY %2(s64)
$x0 = COPY %2(s64)
...
---
@ -134,16 +134,16 @@ body: |
; CHECK: successors: %bb.1(0x80000000)
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[COPY]]
; CHECK: %w0 = COPY [[ORNWrr]]
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
; CHECK: $w0 = COPY [[ORNWrr]]
bb.0:
liveins: %w0, %w1
liveins: $w0, $w1
successors: %bb.1
%1(s32) = G_CONSTANT i32 -1
G_BR %bb.1
bb.1:
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%2(s32) = G_XOR %0, %1
%w0 = COPY %2(s32)
$w0 = COPY %2(s32)
...

108
test/CodeGen/AArch64/GlobalISel/select.mir
View File

@ -47,7 +47,7 @@ stack:
body: |
bb.0:
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
%x0 = COPY %0(p0)
$x0 = COPY %0(p0)
...
---
@ -65,11 +65,11 @@ registers:
# CHECK: %2:gpr64 = ADDXrr %0, %1
body: |
bb.0:
liveins: %x0
%0(p0) = COPY %x0
liveins: $x0
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 42
%2(p0) = G_GEP %0, %1(s64)
%x0 = COPY %2(p0)
$x0 = COPY %2(p0)
...
---
@ -82,10 +82,10 @@ regBankSelected: true
# CHECK: %1:gpr64sp = ANDXri %0, 8060
body: |
bb.0:
liveins: %x0
%0:gpr(p0) = COPY %x0
liveins: $x0
%0:gpr(p0) = COPY $x0
%1:gpr(p0) = G_PTR_MASK %0, 3
%x0 = COPY %1(p0)
$x0 = COPY %1(p0)
...
---
@ -104,7 +104,7 @@ registers:
body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @var_local
%x0 = COPY %0(p0)
$x0 = COPY %0(p0)
...
---
@ -122,7 +122,7 @@ registers:
body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @var_got
%x0 = COPY %0(p0)
$x0 = COPY %0(p0)
...
---
@ -153,36 +153,36 @@ registers:
- { id: 11, class: gpr }
# CHECK: body:
# CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv
# CHECK: %1:gpr32 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
# CHECK: $wzr = SUBSWrr %0, %0, implicit-def $nzcv
# CHECK: %1:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
# CHECK: %xzr = SUBSXrr %2, %2, implicit-def %nzcv
# CHECK: %3:gpr32 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
# CHECK: $xzr = SUBSXrr %2, %2, implicit-def $nzcv
# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
# CHECK: %xzr = SUBSXrr %4, %4, implicit-def %nzcv
# CHECK: %5:gpr32 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
# CHECK: $xzr = SUBSXrr %4, %4, implicit-def $nzcv
# CHECK: %5:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
body: |
bb.0:
liveins: %w0, %x0
liveins: $w0, $x0
%0(s32) = COPY %w0
%0(s32) = COPY $w0
%1(s32) = G_ICMP intpred(eq), %0, %0
%6(s1) = G_TRUNC %1(s32)
%9(s32) = G_ANYEXT %6
%w0 = COPY %9(s32)
$w0 = COPY %9(s32)
%2(s64) = COPY %x0
%2(s64) = COPY $x0
%3(s32) = G_ICMP intpred(uge), %2, %2
%7(s1) = G_TRUNC %3(s32)
%10(s32) = G_ANYEXT %7
%w0 = COPY %10(s32)
$w0 = COPY %10(s32)
%4(p0) = COPY %x0
%4(p0) = COPY $x0
%5(s32) = G_ICMP intpred(ne), %4, %4
%8(s1) = G_TRUNC %5(s32)
%11(s32) = G_ANYEXT %8
%w0 = COPY %11(s32)
$w0 = COPY %11(s32)
...
---
@ -209,29 +209,29 @@ registers:
- { id: 7, class: gpr }
# CHECK: body:
# CHECK: FCMPSrr %0, %0, implicit-def %nzcv
# CHECK: [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr %wzr, %wzr, 5, implicit %nzcv
# CHECK: [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr %wzr, %wzr, 13, implicit %nzcv
# CHECK: FCMPSrr %0, %0, implicit-def $nzcv
# CHECK: [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
# CHECK: [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
# CHECK: %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
# CHECK: FCMPDrr %2, %2, implicit-def %nzcv
# CHECK: %3:gpr32 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
# CHECK: FCMPDrr %2, %2, implicit-def $nzcv
# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
body: |
bb.0:
liveins: %w0, %x0
liveins: $w0, $x0
%0(s32) = COPY %s0
%0(s32) = COPY $s0
%1(s32) = G_FCMP floatpred(one), %0, %0
%4(s1) = G_TRUNC %1(s32)
%6(s32) = G_ANYEXT %4
%w0 = COPY %6(s32)
$w0 = COPY %6(s32)
%2(s64) = COPY %d0
%2(s64) = COPY $d0
%3(s32) = G_FCMP floatpred(uge), %2, %2
%5(s1) = G_TRUNC %3(s32)
%7(s32) = G_ANYEXT %5
%w0 = COPY %7(s32)
$w0 = COPY %7(s32)
...
@ -257,10 +257,10 @@ registers:
body: |
bb.0:
liveins: %s0, %w0
liveins: $s0, $w0
successors: %bb.1
%0(s32) = COPY %s0
%3:gpr(s32) = COPY %w0
%0(s32) = COPY $s0
%3:gpr(s32) = COPY $w0
%1(s1) = G_TRUNC %3
bb.1:
@ -269,8 +269,8 @@ body: |
G_BRCOND %1, %bb.1
bb.2:
%s0 = COPY %2
RET_ReallyLR implicit %s0
$s0 = COPY %2
RET_ReallyLR implicit $s0
...
---
@ -304,30 +304,30 @@ registers:
- { id: 9, class: gpr }
# CHECK: body:
# CHECK: %wzr = ANDSWri %10, 0, implicit-def %nzcv
# CHECK: %3:gpr32 = CSELWr %1, %2, 1, implicit %nzcv
# CHECK: %wzr = ANDSWri %10, 0, implicit-def %nzcv
# CHECK: %6:gpr64 = CSELXr %4, %5, 1, implicit %nzcv
# CHECK: %wzr = ANDSWri %10, 0, implicit-def %nzcv
# CHECK: %9:gpr64 = CSELXr %7, %8, 1, implicit %nzcv
# CHECK: $wzr = ANDSWri %10, 0, implicit-def $nzcv
# CHECK: %3:gpr32 = CSELWr %1, %2, 1, implicit $nzcv
# CHECK: $wzr = ANDSWri %10, 0, implicit-def $nzcv
# CHECK: %6:gpr64 = CSELXr %4, %5, 1, implicit $nzcv
# CHECK: $wzr = ANDSWri %10, 0, implicit-def $nzcv
# CHECK: %9:gpr64 = CSELXr %7, %8, 1, implicit $nzcv
body: |
bb.0:
liveins: %w0, %w1, %w2
%10:gpr(s32) = COPY %w0
liveins: $w0, $w1, $w2
%10:gpr(s32) = COPY $w0
%0(s1) = G_TRUNC %10
%1(s32) = COPY %w1
%2(s32) = COPY %w2
%1(s32) = COPY $w1
%2(s32) = COPY $w2
%3(s32) = G_SELECT %0, %1, %2
%w0 = COPY %3(s32)
$w0 = COPY %3(s32)
%4(s64) = COPY %x0
%5(s64) = COPY %x1
%4(s64) = COPY $x0
%5(s64) = COPY $x1
%6(s64) = G_SELECT %0, %4, %5
%x0 = COPY %6(s64)
$x0 = COPY %6(s64)
%7(p0) = COPY %x0
%8(p0) = COPY %x1
%7(p0) = COPY $x0
%8(p0) = COPY $x1
%9(p0) = G_SELECT %0, %7, %8
%x0 = COPY %9(p0)
$x0 = COPY %9(p0)
...

58
test/CodeGen/AArch64/GlobalISel/translate-gep.ll
View File

@ -5,7 +5,7 @@
define i8* @translate_element_size1(i64 %arg) {
; CHECK-LABEL: name: translate_element_size1
; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[BASE:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]]
%tmp = getelementptr i8, i8* null, i64 %arg
@ -16,12 +16,12 @@ define %type* @first_offset_const(%type* %addr) {
; CHECK-LABEL: name: first_offset_const
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: %x0 = COPY [[GEP]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[GEP]](p0)
; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 1
ret %type* %res
}
@ -30,11 +30,11 @@ define %type* @first_offset_trivial(%type* %addr) {
; CHECK-LABEL: name: first_offset_trivial
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK: %x0 = COPY [[COPY1]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[COPY1]](p0)
; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 0
ret %type* %res
}
@ -43,15 +43,15 @@ define %type* @first_offset_variable(%type* %addr, i64 %idx) {
; CHECK-LABEL: name: first_offset_variable
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: %x0, %x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[COPY1]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
; CHECK: %x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i64 %idx
ret %type* %res
}
@ -60,16 +60,16 @@ define %type* @first_offset_ext(%type* %addr, i32 %idx) {
; CHECK-LABEL: name: first_offset_ext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: %w1, %x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
; CHECK: liveins: $w1, $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
; CHECK: %x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 %idx
ret %type* %res
}
@ -79,17 +79,17 @@ define i32* @const_then_var(%type1* %addr, i64 %idx) {
; CHECK-LABEL: name: const_then_var
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: %x0, %x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C1]], [[COPY1]]
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP1]](p0)
; CHECK: %x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx
ret i32* %res
}
@ -98,16 +98,16 @@ define i32* @var_then_const(%type1* %addr, i64 %idx) {
; CHECK-LABEL: name: var_then_const
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: %x0, %x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[COPY1]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[C1]](s64)
; CHECK: %x0 = COPY [[GEP1]](p0)
; CHECK: RET_ReallyLR implicit %x0
; CHECK: $x0 = COPY [[GEP1]](p0)
; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
ret i32* %res
}

2
test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
View File

@ -6,7 +6,7 @@ define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
; CHECK: fixedStack:
; CHECK: - { id: [[VARARGS_SLOT:[0-9]+]], type: default, offset: 8
; CHECK: body:
; CHECK: [[LIST:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[LIST:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[VARARGS_AREA:%[0-9]+]]:gpr64common = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
; CHECK: STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 0)
call void @llvm.va_start(i8* %list)

2
test/CodeGen/AArch64/GlobalISel/vastart.ll
View File

@ -5,7 +5,7 @@
declare void @llvm.va_start(i8*)
define void @test_va_start(i8* %list) {
; CHECK-LABEL: name: test_va_start
; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store 8 into %ir.list, align 0)
; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store 32 into %ir.list, align 0)
call void @llvm.va_start(i8* %list)

4
test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
View File

@ -17,6 +17,6 @@ registers:
- { id: 0, class: _ }
body: |
bb.0:
liveins: %x0
%0(s64) = COPY %x0
liveins: $x0
%0(s64) = COPY $x0
...

6
test/CodeGen/AArch64/GlobalISel/verify-selected.mir
View File

@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr }
body: |
bb.0:
liveins: %x0
%0 = COPY %x0
liveins: $x0
%0 = COPY $x0
; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
; CHECK: instruction: %1:gpr64 = G_ADD
@ -28,5 +28,5 @@ body: |
; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function ***
; CHECK: instruction: %2:gpr(s64) = COPY
; CHECK: operand 0: %2
%2(s64) = COPY %x0
%2(s64) = COPY $x0
...

66
test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
View File

@ -12,13 +12,13 @@ registers:
- { id: 4, class: fpr64 }
body: |
bb.0.entry:
%2:fpr64 = COPY %d2
%1:fpr64 = COPY %d1
%0:fpr64 = COPY %d0
%2:fpr64 = COPY $d2
%1:fpr64 = COPY $d1
%0:fpr64 = COPY $d0
%3:fpr64 = FMULv2f32 %0, %1
%4:fpr64 = FSUBv2f32 killed %3, %2
%d0 = COPY %4
RET_ReallyLR implicit %d0
$d0 = COPY %4
RET_ReallyLR implicit $d0
...
# UNPROFITABLE-LABEL: name: f1_2s
@ -38,13 +38,13 @@ registers:
- { id: 4, class: fpr128 }
body: |
bb.0.entry:
%2:fpr128 = COPY %q2
%1:fpr128 = COPY %q1
%0:fpr128 = COPY %q0
%2:fpr128 = COPY $q2
%1:fpr128 = COPY $q1
%0:fpr128 = COPY $q0
%3:fpr128 = FMULv4f32 %0, %1
%4:fpr128 = FSUBv4f32 killed %3, %2
%q0 = COPY %4
RET_ReallyLR implicit %q0
$q0 = COPY %4
RET_ReallyLR implicit $q0
...
# UNPROFITABLE-LABEL: name: f1_4s
@ -64,13 +64,13 @@ registers:
- { id: 4, class: fpr128 }
body: |
bb.0.entry:
%2:fpr128 = COPY %q2
%1:fpr128 = COPY %q1
%0:fpr128 = COPY %q0
%2:fpr128 = COPY $q2
%1:fpr128 = COPY $q1
%0:fpr128 = COPY $q0
%3:fpr128 = FMULv2f64 %0, %1
%4:fpr128 = FSUBv2f64 killed %3, %2
%q0 = COPY %4
RET_ReallyLR implicit %q0
$q0 = COPY %4
RET_ReallyLR implicit $q0
...
# UNPROFITABLE-LABEL: name: f1_2d
@ -92,15 +92,15 @@ registers:
- { id: 6, class: fpr64 }
body: |
bb.0.entry:
%3:fpr64 = COPY %q3
%2:fpr64 = COPY %q2
%1:fpr64 = COPY %q1
%0:fpr64 = COPY %q0
%3:fpr64 = COPY $q3
%2:fpr64 = COPY $q2
%1:fpr64 = COPY $q1
%0:fpr64 = COPY $q0
%4:fpr64 = FMULv2f32 %0, %1
%5:fpr64 = FMULv2f32 %2, %3
%6:fpr64 = FSUBv2f32 killed %4, %5
%q0 = COPY %6
RET_ReallyLR implicit %q0
$q0 = COPY %6
RET_ReallyLR implicit $q0
...
# ALL-LABEL: name: f1_both_fmul_2s
@ -118,15 +118,15 @@ registers:
- { id: 6, class: fpr128 }
body: |
bb.0.entry:
%3:fpr128 = COPY %q3
%2:fpr128 = COPY %q2
%1:fpr128 = COPY %q1
%0:fpr128 = COPY %q0
%3:fpr128 = COPY $q3
%2:fpr128 = COPY $q2
%1:fpr128 = COPY $q1
%0:fpr128 = COPY $q0
%4:fpr128 = FMULv4f32 %0, %1
%5:fpr128 = FMULv4f32 %2, %3
%6:fpr128 = FSUBv4f32 killed %4, %5
%q0 = COPY %6
RET_ReallyLR implicit %q0
$q0 = COPY %6
RET_ReallyLR implicit $q0
...
# ALL-LABEL: name: f1_both_fmul_4s
@ -144,15 +144,15 @@ registers:
- { id: 6, class: fpr128 }
body: |
bb.0.entry:
%3:fpr128 = COPY %q3
%2:fpr128 = COPY %q2
%1:fpr128 = COPY %q1
%0:fpr128 = COPY %q0
%3:fpr128 = COPY $q3
%2:fpr128 = COPY $q2
%1:fpr128 = COPY $q1
%0:fpr128 = COPY $q0
%4:fpr128 = FMULv2f64 %0, %1
%5:fpr128 = FMULv2f64 %2, %3
%6:fpr128 = FSUBv2f64 killed %4, %5
%q0 = COPY %6
RET_ReallyLR implicit %q0
$q0 = COPY %6
RET_ReallyLR implicit $q0
...
# ALL-LABEL: name: f1_both_fmul_2d

4
test/CodeGen/AArch64/arm64-csldst-mmo.ll
View File

@ -10,8 +10,8 @@
;
; CHECK: Before post-MI-sched:
; CHECK-LABEL: # Machine code for function test1:
; CHECK: SU(2): STRWui %wzr
; CHECK: SU(3): %x21, %x20 = frame-destroy LDPXi %sp, 2
; CHECK: SU(2): STRWui $wzr
; CHECK: SU(3): $x21, $x20 = frame-destroy LDPXi $sp, 2
; CHECK: Predecessors:
; CHECK-NEXT: SU(0): Out
; CHECK-NEXT: SU(0): Out

106
test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir
View File

@ -1,115 +1,115 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
---
# CHECK-LABEL: name: test_LDURSi_post
# CHECK: LDRSpost %x0, -4
# CHECK: LDRSpost $x0, -4
name: test_LDURSi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%s0 = LDURSi %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$s0 = LDURSi $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_LDURDi_post
# CHECK: LDRDpost %x0, -4
# CHECK: LDRDpost $x0, -4
name: test_LDURDi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%d0 = LDURDi %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$d0 = LDURDi $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_LDURQi_post
# CHECK: LDRQpost %x0, -4
# CHECK: LDRQpost $x0, -4
name: test_LDURQi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%q0 = LDURQi %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$q0 = LDURQi $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_LDURWi_post
# CHECK: LDRWpost %x0, -4
# CHECK: LDRWpost $x0, -4
name: test_LDURWi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%w1 = LDURWi %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$w1 = LDURWi $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_LDURXi_post
# CHECK: %x1 = LDRXpost %x0, -4
# CHECK: $x1 = LDRXpost $x0, -4
name: test_LDURXi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%x1 = LDURXi %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$x1 = LDURXi $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_STURSi_post
# CHECK: STRSpost %s0, %x0, -4
# CHECK: STRSpost $s0, $x0, -4
name: test_STURSi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%s0 = FMOVS0
STURSi %s0, %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$s0 = FMOVS0
STURSi $s0, $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_STURDi_post
# CHECK: STRDpost %d0, %x0, -4
# CHECK: STRDpost $d0, $x0, -4
name: test_STURDi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%d0 = FMOVD0
STURDi %d0, %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$d0 = FMOVD0
STURDi $d0, $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_STURQi_post
# CHECK: STRQpost %q0, %x0, -4
# CHECK: STRQpost $q0, $x0, -4
name: test_STURQi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
%q0 = MOVIv4i32 0, 0
STURQi %q0, %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
$q0 = MOVIv4i32 0, 0
STURQi $q0, $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_STURWi_post
# CHECK: STRWpost %wzr, %x0, -4
# CHECK: STRWpost $wzr, $x0, -4
name: test_STURWi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
STURWi %wzr, %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
STURWi $wzr, $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...
# CHECK-LABEL: name: test_STURXi_post
# CHECK: STRXpost %xzr, %x0, -4
# CHECK: STRXpost $xzr, $x0, -4
name: test_STURXi_post
body: |
bb.0.entry:
liveins: %x0
liveins: $x0
STURXi %xzr, %x0, 0
%x0 = SUBXri %x0, 4, 0
RET_ReallyLR implicit %x0
STURXi $xzr, $x0, 0
$x0 = SUBXri $x0, 4, 0
RET_ReallyLR implicit $x0
...

6
test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
View File

@ -9,11 +9,11 @@
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2
; CHECK-NEXT: SU(4): Ord Latency=0
; CHECK: SU(3): STRWui %wzr, %0:gpr64common, 0; mem:ST4[%ptr1]
; CHECK: SU(3): STRWui $wzr, %0:gpr64common, 0; mem:ST4[%ptr1]
; CHECK: Successors:
; CHECK: SU(4): Ord Latency=0
; CHECK: SU(4): STRWui %wzr, %1:gpr64common, 0; mem:ST4[%ptr2]
; CHECK: SU(5): %w0 = COPY %2
; CHECK: SU(4): STRWui $wzr, %1:gpr64common, 0; mem:ST4[%ptr2]
; CHECK: SU(5): $w0 = COPY %2
; CHECK: ** ScheduleDAGMI::schedule picking next node
define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
entry:

4
test/CodeGen/AArch64/arm64-misched-multimmo.ll
View File

@ -8,11 +8,11 @@
; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
;
; CHECK-LABEL: # Machine code for function foo:
; CHECK: SU(2): renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi
; CHECK: SU(2): renamable $w{{[0-9]+}}, renamable $w{{[0-9]+}} = LDPWi
; CHECK: Successors:
; CHECK-NOT: ch SU(4)
; CHECK: SU(3)
; CHECK: SU(4): STRWui %wzr, renamable %x{{[0-9]+}}
; CHECK: SU(4): STRWui $wzr, renamable $x{{[0-9]+}}
define i32 @foo() {
entry:
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4

14
test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
View File

@ -1,6 +1,6 @@
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s
# CHECK: %1:gpr32common = ANDWri {{.*}}
# CHECK-NEXT: %wzr = SUBSWri {{.*}}
# CHECK-NEXT: $wzr = SUBSWri {{.*}}
--- |
define i32 @test01() nounwind {
entry:
@ -27,15 +27,15 @@ body: |
%0 = MOVi32imm 1
%1 = ANDWri killed %1, 15
%wzr = SUBSWri killed %1, 0, 0, implicit-def %nzcv
Bcc 9, %bb.2.if.end, implicit %nzcv
$wzr = SUBSWri killed %1, 0, 0, implicit-def $nzcv
Bcc 9, %bb.2.if.end, implicit $nzcv
bb.1.if.then:
%w0 = MOVi32imm 1
RET_ReallyLR implicit %w0
$w0 = MOVi32imm 1
RET_ReallyLR implicit $w0
bb.2.if.end:
%w0 = MOVi32imm 0
RET_ReallyLR implicit %w0
$w0 = MOVi32imm 0
RET_ReallyLR implicit $w0
...

18
test/CodeGen/AArch64/ccmp-successor-probs.mir
View File

@ -6,7 +6,7 @@
# CHECK-LABEL: name: aarch64-ccmp-successor-probs
# CHECK: bb.0:
# CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
# CHECK: CCMPXr %5, %4, 0, 10, implicit-def %nzcv, implicit %nzcv
# CHECK: CCMPXr %5, %4, 0, 10, implicit-def $nzcv, implicit $nzcv
#
name: aarch64-ccmp-successor-probs
registers:
@ -22,21 +22,21 @@ body : |
bb.0:
successors: %bb.1(0x7e000000), %bb.2(0x02000000)
%0 = LDRXui killed %x0, 69
%1 = COPY %xzr
%2 = SUBSXrr %1, %0, implicit-def dead %nzcv
%3 = SUBSXri %x1, 1, 0, implicit-def dead %nzcv
%0 = LDRXui killed $x0, 69
%1 = COPY $xzr
%2 = SUBSXrr %1, %0, implicit-def dead $nzcv
%3 = SUBSXri $x1, 1, 0, implicit-def dead $nzcv
%4 = COPY %0
%5 = COPY %3
%6 = SUBSXrr %x1, killed %2, implicit-def %nzcv
Bcc 11, %bb.2, implicit %nzcv
%6 = SUBSXrr $x1, killed %2, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1:
successors: %bb.2(0x02082082), %bb.3(0x7df7df7e)
%7 = SUBSXrr %5, %4, implicit-def %nzcv
Bcc 12, %bb.2, implicit %nzcv
%7 = SUBSXrr %5, %4, implicit-def $nzcv
Bcc 12, %bb.2, implicit $nzcv
B %bb.3
bb.2:

30
test/CodeGen/AArch64/cfi_restore.mir
View File

@ -9,29 +9,29 @@ frameInfo:
hasCalls: true
stack:
- { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: 0,
callee-saved-register: '%lr' }
callee-saved-register: '$lr' }
- { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 8, stack-id: 0,
callee-saved-register: '%fp' }
callee-saved-register: '$fp' }
body: |
bb.0:
liveins: %fp, %lr
liveins: $fp, $lr
%sp = frame-setup SUBXri %sp, 16, 0
frame-setup STRXui killed %fp, %sp, 0 :: (store 8 into %stack.1)
frame-setup CFI_INSTRUCTION offset %w29, -16
$sp = frame-setup SUBXri $sp, 16, 0
frame-setup STRXui killed $fp, $sp, 0 :: (store 8 into %stack.1)
frame-setup CFI_INSTRUCTION offset $w29, -16
; CHECK: .cfi_offset w29, -16
frame-setup STRXui killed %lr, %sp, 1 :: (store 8 into %stack.0)
frame-setup CFI_INSTRUCTION offset %w30, -8
frame-setup STRXui killed $lr, $sp, 1 :: (store 8 into %stack.0)
frame-setup CFI_INSTRUCTION offset $w30, -8
; CHECK: .cfi_offset w30, -8
%fp = frame-setup ADDXri %sp, 0, 0
frame-setup CFI_INSTRUCTION def_cfa %w29, 16
%lr = LDRXui %sp, 1 :: (load 8 from %stack.0)
CFI_INSTRUCTION restore %w30
$fp = frame-setup ADDXri $sp, 0, 0
frame-setup CFI_INSTRUCTION def_cfa $w29, 16
$lr = LDRXui $sp, 1 :: (load 8 from %stack.0)
CFI_INSTRUCTION restore $w30
; CHECK: .cfi_restore w30
%fp = LDRXui %sp, 0 :: (load 8 from %stack.1)
CFI_INSTRUCTION restore %w29
$fp = LDRXui $sp, 0 :: (load 8 from %stack.1)
CFI_INSTRUCTION restore $w29
; CHECK: .cfi_restore w29
%sp = ADDXri %sp, 16, 0
$sp = ADDXri $sp, 16, 0
RET_ReallyLR
; CHECK: .cfi_endproc
...

306
test/CodeGen/AArch64/falkor-hwpf-fix.mir
View File

@ -3,147 +3,147 @@
# Verify that the tag collision between the loads is resolved for various load opcodes.
# CHECK-LABEL: name: hwpf1
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LDRWui %[[BASE]], 0
# CHECK: LDRWui %x1, 1
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LDRWui $[[BASE]], 0
# CHECK: LDRWui $x1, 1
name: hwpf1
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1
liveins: $w0, $x1
%w2 = LDRWui %x1, 0 :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 1
$w2 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 1
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpf2
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1i64 %q2, 0, %[[BASE]]
# CHECK: LDRWui %x1, 0
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1i64 $q2, 0, $[[BASE]]
# CHECK: LDRWui $x1, 0
name: hwpf2
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %q2
liveins: $w0, $x1, $q2
%q2 = LD1i64 %q2, 0, %x1 :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 0
$q2 = LD1i64 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 0
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpf3
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1i8 %q2, 0, %[[BASE]]
# CHECK: LDRWui %x1, 0
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1i8 $q2, 0, $[[BASE]]
# CHECK: LDRWui $x1, 0
name: hwpf3
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %q2
liveins: $w0, $x1, $q2
%q2 = LD1i8 %q2, 0, %x1 :: ("aarch64-strided-access" load 4)
%w0 = LDRWui %x1, 0
$q2 = LD1i8 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
$w0 = LDRWui $x1, 0
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpf4
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1Onev1d %[[BASE]]
# CHECK: LDRWui %x1, 0
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1Onev1d $[[BASE]]
# CHECK: LDRWui $x1, 0
name: hwpf4
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1
liveins: $w0, $x1
%d2 = LD1Onev1d %x1 :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 0
$d2 = LD1Onev1d $x1 :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 0
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpf5
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1Twov1d %[[BASE]]
# CHECK: LDRWui %x1, 0
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1Twov1d $[[BASE]]
# CHECK: LDRWui $x1, 0
name: hwpf5
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1
liveins: $w0, $x1
%d2_d3 = LD1Twov1d %x1 :: ("aarch64-strided-access" load 4)
%w0 = LDRWui %x1, 0
$d2_d3 = LD1Twov1d $x1 :: ("aarch64-strided-access" load 4)
$w0 = LDRWui $x1, 0
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpf6
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LDPQi %[[BASE]]
# CHECK: LDRWui %x1, 3
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LDPQi $[[BASE]]
# CHECK: LDRWui $x1, 3
name: hwpf6
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1
liveins: $w0, $x1
%q2, %q3 = LDPQi %x1, 3 :: ("aarch64-strided-access" load 4)
%w0 = LDRWui %x1, 3
$q2, $q3 = LDPQi $x1, 3 :: ("aarch64-strided-access" load 4)
$w0 = LDRWui $x1, 3
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpf7
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LDPXi %[[BASE]]
# CHECK: LDRWui %x1, 2
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LDPXi $[[BASE]]
# CHECK: LDRWui $x1, 2
name: hwpf7
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1
liveins: $w0, $x1
%x2, %x3 = LDPXi %x1, 3 :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 2
$x2, $x3 = LDPXi $x1, 3 :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 2
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
@ -153,154 +153,154 @@ body: |
# for post increment addressing for various load opcodes.
# CHECK-LABEL: name: hwpfinc1
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LDRWpost %[[BASE]], 0
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWui %x1, 1
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LDRWpost $[[BASE]], 0
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWui $x1, 1
name: hwpfinc1
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1
liveins: $w0, $x1
%x1, %w2 = LDRWpost %x1, 0 :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 1
$x1, $w2 = LDRWpost $x1, 0 :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 1
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpfinc2
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1i64_POST %q2, 0, %[[BASE]]
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWui %x1, 1
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1i64_POST $q2, 0, $[[BASE]]
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWui $x1, 1
name: hwpfinc2
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %q2
liveins: $w0, $x1, $q2
%x1, %q2 = LD1i64_POST %q2, 0, %x1, %x1 :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 132
$x1, $q2 = LD1i64_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 132
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpfinc3
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1i8_POST %q2, 0, %[[BASE]]
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWui %x1, 132
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1i8_POST $q2, 0, $[[BASE]]
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWui $x1, 132
name: hwpfinc3
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %q2
liveins: $w0, $x1, $q2
%x1, %q2 = LD1i8_POST %q2, 0, %x1, %x1 :: ("aarch64-strided-access" load 4)
%w0 = LDRWui %x1, 132
$x1, $q2 = LD1i8_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4)
$w0 = LDRWui $x1, 132
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpfinc4
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD1Rv1d_POST %[[BASE]]
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWui %x1, 252
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD1Rv1d_POST $[[BASE]]
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWui $x1, 252
name: hwpfinc4
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %q2
liveins: $w0, $x1, $q2
%x1, %d2 = LD1Rv1d_POST %x1, %xzr :: ("aarch64-strided-access" load 4)
%w2 = LDRWui %x1, 252
$x1, $d2 = LD1Rv1d_POST $x1, $xzr :: ("aarch64-strided-access" load 4)
$w2 = LDRWui $x1, 252
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpfinc5
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LD3Threev2s_POST %[[BASE]]
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWroX %x17, %x0
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LD3Threev2s_POST $[[BASE]]
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWroX $x17, $x0
name: hwpfinc5
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %x17, %q2
liveins: $w0, $x1, $x17, $q2
%x1, %d2_d3_d4 = LD3Threev2s_POST %x1, %x0 :: ("aarch64-strided-access" load 4)
%w0 = LDRWroX %x17, %x0, 0, 0
$x1, $d2_d3_d4 = LD3Threev2s_POST $x1, $x0 :: ("aarch64-strided-access" load 4)
$w0 = LDRWroX $x17, $x0, 0, 0
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpfinc6
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LDPDpost %[[BASE]]
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWui %x17, 2
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LDPDpost $[[BASE]]
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWui $x17, 2
name: hwpfinc6
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %x17, %q2
liveins: $w0, $x1, $x17, $q2
%x1, %d2, %d3 = LDPDpost %x1, 3 :: ("aarch64-strided-access" load 4)
%w16 = LDRWui %x17, 2
$x1, $d2, $d3 = LDPDpost $x1, 3 :: ("aarch64-strided-access" load 4)
$w16 = LDRWui $x17, 2
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
...
---
# CHECK-LABEL: name: hwpfinc7
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
# CHECK: LDPXpost %[[BASE]]
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
# CHECK: LDRWui %x17, 2
# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
# CHECK: LDPXpost $[[BASE]]
# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
# CHECK: LDRWui $x17, 2
name: hwpfinc7
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %x17, %q2
liveins: $w0, $x1, $x17, $q2
%x1, %x2, %x3 = LDPXpost %x1, 3 :: ("aarch64-strided-access" load 4)
%w18 = LDRWui %x17, 2
$x1, $x2, $x3 = LDPXpost $x1, 3 :: ("aarch64-strided-access" load 4)
$w18 = LDRWui $x17, 2
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
@ -309,23 +309,23 @@ body: |
# Check that we handle case of strided load with no HW prefetcher tag correctly.
# CHECK-LABEL: name: hwpf_notagbug
# CHECK-NOT: ORRXrs %xzr
# CHECK: LDARW %x1
# CHECK-NOT: ORRXrs %xzr
# CHECK: LDRWui %x1
# CHECK-NOT: ORRXrs $xzr
# CHECK: LDARW $x1
# CHECK-NOT: ORRXrs $xzr
# CHECK: LDRWui $x1
name: hwpf_notagbug
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x1, %x17
liveins: $w0, $x1, $x17
%w1 = LDARW %x1 :: ("aarch64-strided-access" load 4)
%w1 = LDRWui %x1, 0 :: ("aarch64-strided-access" load 4)
%w17 = LDRWui %x17, 0 :: ("aarch64-strided-access" load 4)
$w1 = LDARW $x1 :: ("aarch64-strided-access" load 4)
$w1 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4)
$w17 = LDRWui $x17, 0 :: ("aarch64-strided-access" load 4)
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR
@ -334,21 +334,21 @@ body: |
# Check that we treat sp based loads as non-prefetching.
# CHECK-LABEL: name: hwpf_spbase
# CHECK-NOT: ORRXrs %xzr
# CHECK: LDRWui %x15
# CHECK: LDRWui %sp
# CHECK-NOT: ORRXrs $xzr
# CHECK: LDRWui $x15
# CHECK: LDRWui $sp
name: hwpf_spbase
tracksRegLiveness: true
body: |
bb.0:
liveins: %w0, %x15
liveins: $w0, $x15
%w1 = LDRWui %x15, 0 :: ("aarch64-strided-access" load 4)
%w17 = LDRWui %sp, 0
$w1 = LDRWui $x15, 0 :: ("aarch64-strided-access" load 4)
$w17 = LDRWui $sp, 0
%w0 = SUBWri %w0, 1, 0
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
Bcc 9, %bb.0, implicit %nzcv
$w0 = SUBWri $w0, 1, 0
$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
Bcc 9, %bb.0, implicit $nzcv
bb.1:
RET_ReallyLR

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