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[RISCV] When matching RORIW, make sure the same input is given to both shifts.

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The code is looking for (sext_inreg (or (shl X, C2), (shr (and Y, C3), C1))).
We need to ensure X and Y are the same.

Differential Revision: https://reviews.llvm.org/D90580
This commit is contained in:
Craig Topper 2020-11-02 08:45:33 -08:00
parent aeaa523af1
commit d4f846d5af
2 changed files with 17 additions and 8 deletions
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7
lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View File

@ -427,8 +427,8 @@ bool RISCVDAGToDAGISel::SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
// Check that it is a RORIW (i32 Right Rotate Immediate on RV64).
// We first check that it is the right node tree:
//
// (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
// (SRL (AND (AssertSext RS2, i32), VC3), VC1)))
// (SIGN_EXTEND_INREG (OR (SHL RS1, VC2),
// (SRL (AND RS1, VC3), VC1)))
//
// Then we check that the constant operands respect these constraints:
//
@ -450,7 +450,8 @@ bool RISCVDAGToDAGISel::SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
SDValue Srl = Or.getOperand(1);
if (Srl.getOperand(0).getOpcode() == ISD::AND) {
SDValue And = Srl.getOperand(0);
if (isa<ConstantSDNode>(Srl.getOperand(1)) &&
if (And.getOperand(0) == Shl.getOperand(0) &&
isa<ConstantSDNode>(Srl.getOperand(1)) &&
isa<ConstantSDNode>(Shl.getOperand(1)) &&
isa<ConstantSDNode>(And.getOperand(1))) {
uint32_t VC1 = Srl.getConstantOperandVal(1);

18
test/CodeGen/RISCV/rv64Zbbp.ll
View File

@ -345,8 +345,7 @@ define signext i32 @rori_i32_fshr(i32 signext %a) nounwind {
; This test is similar to the type legalized version of the fshl/fshr tests, but
; instead of having the same input to both shifts it has different inputs. Make
; sure we don't match it has a roriw.
; FIXME: We're currently missing a check that the inputs are the same.
; sure we don't match it as a roriw.
define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
; RV64I-LABEL: not_rori_i32:
; RV64I: # %bb.0:
@ -358,17 +357,26 @@ define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
;
; RV64IB-LABEL: not_rori_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: roriw a0, a0, 1
; RV64IB-NEXT: slli a0, a0, 31
; RV64IB-NEXT: srliw a1, a1, 1
; RV64IB-NEXT: or a0, a0, a1
; RV64IB-NEXT: sext.w a0, a0
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: not_rori_i32:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: roriw a0, a0, 1
; RV64IBB-NEXT: slli a0, a0, 31
; RV64IBB-NEXT: srliw a1, a1, 1
; RV64IBB-NEXT: or a0, a0, a1
; RV64IBB-NEXT: sext.w a0, a0
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: not_rori_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: roriw a0, a0, 1
; RV64IBP-NEXT: slli a0, a0, 31
; RV64IBP-NEXT: srliw a1, a1, 1
; RV64IBP-NEXT: or a0, a0, a1
; RV64IBP-NEXT: sext.w a0, a0
; RV64IBP-NEXT: ret
%a = shl i32 %x, 31
%b = lshr i32 %y, 1