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This fixes functions like
void f (int a1, int a2, int a3, int a4, int a5,...) In ARMTargetLowering::LowerFormalArguments if the function has 4 or more regular arguments we used to set VarArgsFrameIndex using an offset of 0, which is only correct if the function has exactly 4 regular arguments. llvm-svn: 85590
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@ -1629,13 +1629,12 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned VARegSize = (4 - NumGPRs) * 4;
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unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
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unsigned ArgOffset = 0;
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unsigned ArgOffset = CCInfo.getNextStackOffset();
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if (VARegSaveSize) {
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// If this function is vararg, store any remaining integer argument regs
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// to their spots on the stack so that they may be loaded by deferencing
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// the result of va_next.
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AFI->setVarArgsRegSaveSize(VARegSaveSize);
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ArgOffset = CCInfo.getNextStackOffset();
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VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
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VARegSaveSize - VARegSize);
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SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
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17
test/CodeGen/ARM/2009-10-30.ll
Normal file
17
test/CodeGen/ARM/2009-10-30.ll
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@ -0,0 +1,17 @@
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; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
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; This test checks that the address of the varg arguments is correctly
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; computed when there are 5 or more regular arguments.
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define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) {
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entry:
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;CHECK: sub sp, sp, #4
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;CHECK: add r0, sp, #8
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;CHECK: str r0, [sp], #+4
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;CHECK: bx lr
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%ap = alloca i8*, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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