RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

[AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG combine phase where I had originally meant to put it.

Browse Source 
llvm-svn: 293157
This commit is contained in:
Craig Topper 2017-01-26 07:17:58 +00:00
parent ebed70c5a8
commit d519e39f21
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -29505,7 +29505,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Look for vselects with LHS/RHS being bitcasted from an operation that // Look for vselects with LHS/RHS being bitcasted from an operation that
// can be executed on another type. Push the bitcast to the inputs of // can be executed on another type. Push the bitcast to the inputs of
// the operation. This exposes opportunities for using masking instructions. // the operation. This exposes opportunities for using masking instructions.
if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalizeOps() && if (N->getOpcode() == ISD::VSELECT && DCI.isAfterLegalizeVectorOps() &&
CondVT.getVectorElementType() == MVT::i1) { CondVT.getVectorElementType() == MVT::i1) {
if (combineBitcastForMaskedOp(LHS, DAG, DCI)) if (combineBitcastForMaskedOp(LHS, DAG, DCI))
return SDValue(N, 0); return SDValue(N, 0);