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TargetRegisterInfo: Add getRegAsmName()

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Summary:
The motivation for this new function is to move an invalid assumption
about the relationship between the names of register definitions in
tablegen files and their assembly names into TargetRegisterInfo, so that
we can begin working on fixing this assumption.

The current problem is that if you have a register definition in
TableGen like:

def MYReg0 : Register<"r0", 0>;

The function TargetLowering::getRegForInlineAsmConstraint() derives the
assembly name from the tablegen name: "MyReg0" rather than the given
assembly name "r0".  This is working, because on most targets the
tablegen name and the assembly names are case insensitive matches for
each other (e.g. def EAX : X86Reg<"eax", ...>

getRegAsmName() will allow targets to override this default assumption and
return the correct assembly name.

Reviewers: echristo, hfinkel

Subscribers: SamWot, echristo, hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D15614

llvm-svn: 265955
This commit is contained in:
Tom Stellard 2016-04-11 16:21:12 +00:00
parent 9d615dcbe9
commit d52acda33e
2 changed files with 12 additions and 1 deletions
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11
include/llvm/Target/TargetRegisterInfo.h
View File

@ -880,6 +880,17 @@ public:
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const = 0;
/// Return the assembly name for \p Reg.
virtual std::string getRegAsmName(unsigned Reg) const {
// FIXME: We are assuming that the assembly name is equal to the TableGen
// name converted to lower case
//
// The TableGen name is the name of the definition for this register in the
// target's tablegen files. For example, the TableGen name of
// def EAX : Register <...>; is "EAX"
return StringRef(getName(Reg)).lower();
}
//===--------------------------------------------------------------------===//
/// Subtarget Hooks

2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -2330,7 +2330,7 @@ TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I) {
if (RegName.equals_lower(RI->getName(*I))) {
if (RegName.equals_lower(RI->getRegAsmName(*I))) {
std::pair<unsigned, const TargetRegisterClass*> S =
std::make_pair(*I, RC);