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PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. llvm-svn: 205524
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@ -5408,11 +5408,16 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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Operands.size() == 4) {
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ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
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assert(Op->isReg() && "expected register argument");
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assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
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&MRI->getRegClass(ARM::GPRPairRegClassID))
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&& "expected register pair");
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unsigned SuperReg = MRI->getMatchingSuperReg(
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Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
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assert(SuperReg && "expected register pair");
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unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
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Operands.insert(Operands.begin() + 3,
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ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
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ARMOperand::CreateReg(PairedReg, Op->getStartLoc(),
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Op->getEndLoc()));
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}
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9
test/MC/ARM/ldrd-strd-gnu-sp.s
Normal file
9
test/MC/ARM/ldrd-strd-gnu-sp.s
Normal file
@ -0,0 +1,9 @@
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// PR19320
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// RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
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.text
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// CHECK: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1]
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ldrd r12, [r0, #32]
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// CHECK: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1]
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strd r12, [r0, #32]
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