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https://github.com/RPCS3/llvm-mirror.git
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[AVR] Optimize 16-bit int shift
Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D90092
This commit is contained in:
Ben Shi
parent
9b80fe63e4
commit
d588dec200
@ -1402,6 +1402,135 @@ bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// swap Rh
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// swap Rl
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buildMI(MBB, MBBI, AVR::SWAPRd)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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buildMI(MBB, MBBI, AVR::SWAPRd)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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// andi Rh, 0xf0
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auto MI0 =
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buildMI(MBB, MBBI, AVR::ANDIRdK)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addImm(0xf0);
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// SREG is implicitly dead.
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MI0->getOperand(3).setIsDead();
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// eor Rh, Rl
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auto MI1 =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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// SREG is implicitly dead.
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MI1->getOperand(3).setIsDead();
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// andi Rl, 0xf0
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auto MI2 =
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buildMI(MBB, MBBI, AVR::ANDIRdK)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addImm(0xf0);
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// SREG is implicitly dead.
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MI2->getOperand(3).setIsDead();
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// eor Rh, Rl
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auto MI3 =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MI3->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSLW8Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// mov Rh, Rl
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buildMI(MBB, MBBI, AVR::MOVRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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// clr Rl
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auto MIBLO =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MIBLO->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSLW12Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// mov Rh, Rl
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buildMI(MBB, MBBI, AVR::MOVRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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// swap Rh
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buildMI(MBB, MBBI, AVR::SWAPRd)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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// andi Rh, 0xf0
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auto MI0 =
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buildMI(MBB, MBBI, AVR::ANDIRdK)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addImm(0xf0);
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// SREG is implicitly dead.
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MI0->getOperand(3).setIsDead();
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// clr Rl
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auto MI1 =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MI1->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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@ -1433,6 +1562,135 @@ bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// swap Rh
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// swap Rl
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buildMI(MBB, MBBI, AVR::SWAPRd)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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buildMI(MBB, MBBI, AVR::SWAPRd)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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// andi Rl, 0xf
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auto MI0 =
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buildMI(MBB, MBBI, AVR::ANDIRdK)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addImm(0xf);
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// SREG is implicitly dead.
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MI0->getOperand(3).setIsDead();
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// eor Rl, Rh
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auto MI1 =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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// SREG is implicitly dead.
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MI1->getOperand(3).setIsDead();
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// andi Rh, 0xf
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auto MI2 =
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buildMI(MBB, MBBI, AVR::ANDIRdK)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addImm(0xf);
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// SREG is implicitly dead.
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MI2->getOperand(3).setIsDead();
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// eor Rl, Rh
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auto MI3 =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MI3->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSRW8Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// Move upper byte to lower byte.
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buildMI(MBB, MBBI, AVR::MOVRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg);
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// Clear upper byte.
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auto MIBHI =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MIBHI->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSRW12Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// Move upper byte to lower byte.
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buildMI(MBB, MBBI, AVR::MOVRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg);
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// swap Rl
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buildMI(MBB, MBBI, AVR::SWAPRd)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill));
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// andi Rl, 0xf
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auto MI0 =
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buildMI(MBB, MBBI, AVR::ANDIRdK)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstLoReg, getKillRegState(DstIsKill))
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.addImm(0xf);
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// SREG is implicitly dead.
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MI0->getOperand(3).setIsDead();
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// Clear upper byte.
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auto MIBHI =
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buildMI(MBB, MBBI, AVR::EORRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MIBHI->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
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llvm_unreachable("RORW unimplemented");
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@ -1476,6 +1734,39 @@ bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::ASRW8Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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Register DstLoReg, DstHiReg;
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool DstIsKill = MI.getOperand(1).isKill();
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bool ImpIsDead = MI.getOperand(2).isDead();
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TRI->splitReg(DstReg, DstLoReg, DstHiReg);
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// Move upper byte to lower byte.
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buildMI(MBB, MBBI, AVR::MOVRdRr)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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// Move the sign bit to the C flag.
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buildMI(MBB, MBBI, AVR::ADDRdRr).addReg(DstHiReg)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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// Set upper byte to 0 or -1.
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auto MIBHI =
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buildMI(MBB, MBBI, AVR::SBCRdRr)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstHiReg, getKillRegState(DstIsKill))
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.addReg(DstHiReg, getKillRegState(DstIsKill));
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if (ImpIsDead)
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MIBHI->getOperand(3).setIsDead();
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MI.eraseFromParent();
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return true;
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}
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template <>
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bool AVRExpandPseudo::expand<AVR::LSLB7Rd>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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@ -1798,10 +2089,17 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
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EXPAND(AVR::ROLBRd);
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EXPAND(AVR::RORBRd);
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EXPAND(AVR::LSLWRd);
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EXPAND(AVR::LSLW4Rd);
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EXPAND(AVR::LSLW8Rd);
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EXPAND(AVR::LSLW12Rd);
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EXPAND(AVR::LSRWRd);
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EXPAND(AVR::LSRW4Rd);
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EXPAND(AVR::LSRW8Rd);
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EXPAND(AVR::LSRW12Rd);
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EXPAND(AVR::RORWRd);
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EXPAND(AVR::ROLWRd);
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EXPAND(AVR::ASRWRd);
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EXPAND(AVR::ASRW8Rd);
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EXPAND(AVR::LSLB7Rd);
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EXPAND(AVR::LSRB7Rd);
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EXPAND(AVR::ASRB7Rd);
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@ -334,7 +334,7 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
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llvm_unreachable("Invalid shift opcode");
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}
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// Optimize int8 shifts.
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// Optimize int8/int16 shifts.
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if (VT.getSizeInBits() == 8) {
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if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
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// Optimize LSL when 4 <= ShiftAmount <= 6.
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@ -362,6 +362,50 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
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Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim);
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ShiftAmount = 0;
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}
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} else if (VT.getSizeInBits() == 16) {
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if (4 <= ShiftAmount && ShiftAmount < 8)
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switch (Op.getOpcode()) {
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case ISD::SHL:
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Victim = DAG.getNode(AVRISD::LSL4, dl, VT, Victim);
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ShiftAmount -= 4;
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break;
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case ISD::SRL:
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Victim = DAG.getNode(AVRISD::LSR4, dl, VT, Victim);
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ShiftAmount -= 4;
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break;
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default:
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break;
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}
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else if (8 <= ShiftAmount && ShiftAmount < 12)
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switch (Op.getOpcode()) {
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case ISD::SHL:
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Victim = DAG.getNode(AVRISD::LSL8, dl, VT, Victim);
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ShiftAmount -= 8;
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break;
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case ISD::SRL:
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Victim = DAG.getNode(AVRISD::LSR8, dl, VT, Victim);
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ShiftAmount -= 8;
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break;
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case ISD::SRA:
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Victim = DAG.getNode(AVRISD::ASR8, dl, VT, Victim);
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ShiftAmount -= 8;
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break;
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default:
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break;
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}
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else if (12 <= ShiftAmount)
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switch (Op.getOpcode()) {
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case ISD::SHL:
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Victim = DAG.getNode(AVRISD::LSL12, dl, VT, Victim);
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ShiftAmount -= 12;
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break;
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case ISD::SRL:
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Victim = DAG.getNode(AVRISD::LSR12, dl, VT, Victim);
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ShiftAmount -= 12;
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break;
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default:
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break;
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}
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}
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while (ShiftAmount--) {
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@ -36,8 +36,15 @@ enum NodeType {
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/// TargetExternalSymbol, and TargetGlobalAddress.
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WRAPPER,
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LSL, ///< Logical shift left.
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LSL4, ///< Logical shift left 4 bits.
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LSL8, ///< Logical shift left 8 bits.
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LSL12, ///< Logical shift left 12 bits.
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LSR, ///< Logical shift right.
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LSR4, ///< Logical shift right 4 bits.
|
||||
LSR8, ///< Logical shift right 8 bits.
|
||||
LSR12, ///< Logical shift right 12 bits.
|
||||
ASR, ///< Arithmetic shift right.
|
||||
ASR8, ///< Arithmetic shift right 8 bits.
|
||||
LSL7, ///< Logical shift left 7 bits.
|
||||
LSR7, ///< Logical shift right 7 bits.
|
||||
ASR7, ///< Arithmetic shift right 7 bits.
|
||||
|
||||
@ -55,10 +55,17 @@ def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
|
||||
|
||||
// Shift nodes.
|
||||
def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
|
||||
def AVRlsl4 : SDNode<"AVRISD::LSL4", SDTIntUnaryOp>;
|
||||
def AVRlsl8 : SDNode<"AVRISD::LSL8", SDTIntUnaryOp>;
|
||||
def AVRlsl12 : SDNode<"AVRISD::LSL12", SDTIntUnaryOp>;
|
||||
def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
|
||||
def AVRlsr4 : SDNode<"AVRISD::LSR4", SDTIntUnaryOp>;
|
||||
def AVRlsr8 : SDNode<"AVRISD::LSR8", SDTIntUnaryOp>;
|
||||
def AVRlsr12 : SDNode<"AVRISD::LSR12", SDTIntUnaryOp>;
|
||||
def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
|
||||
def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
|
||||
def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
|
||||
def AVRasr8 : SDNode<"AVRISD::ASR8", SDTIntUnaryOp>;
|
||||
def AVRlsl7 : SDNode<"AVRISD::LSL7", SDTIntUnaryOp>;
|
||||
def AVRlsr7 : SDNode<"AVRISD::LSR7", SDTIntUnaryOp>;
|
||||
def AVRasr7 : SDNode<"AVRISD::ASR7", SDTIntUnaryOp>;
|
||||
@ -1674,6 +1681,21 @@ Defs = [SREG] in
|
||||
"lslb7\t$rd",
|
||||
[(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSLW4Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"lslw4\t$rd",
|
||||
[(set i16:$rd, (AVRlsl4 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSLW8Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"lslw8\t$rd",
|
||||
[(set i16:$rd, (AVRlsl8 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSLW12Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"lslw12\t$rd",
|
||||
[(set i16:$rd, (AVRlsl12 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSRRd : FRd<0b1001,
|
||||
0b0100110,
|
||||
(outs GPR8:$rd),
|
||||
@ -1691,6 +1713,21 @@ Defs = [SREG] in
|
||||
"lsrw\t$rd",
|
||||
[(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSRW4Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"lsrw4\t$rd",
|
||||
[(set i16:$rd, (AVRlsr4 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSRW8Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"lsrw8\t$rd",
|
||||
[(set i16:$rd, (AVRlsr8 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def LSRW12Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"lsrw12\t$rd",
|
||||
[(set i16:$rd, (AVRlsr12 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def ASRRd : FRd<0b1001,
|
||||
0b0100101,
|
||||
(outs GPR8:$rd),
|
||||
@ -1708,6 +1745,11 @@ Defs = [SREG] in
|
||||
"asrw\t$rd",
|
||||
[(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>;
|
||||
|
||||
def ASRW8Rd : Pseudo<(outs DREGS:$rd),
|
||||
(ins DREGS:$src),
|
||||
"asrw8\t$rd",
|
||||
[(set i16:$rd, (AVRasr8 i16:$src)), (implicit SREG)]>;
|
||||
|
||||
// Bit rotate operations.
|
||||
let Uses = [SREG] in
|
||||
{
|
||||
@ -2123,12 +2165,7 @@ def : Pat<(store i16:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
|
||||
def : Pat<(i16 (AVRWrapper tblockaddress:$dst)),
|
||||
(LDIWRdK tblockaddress:$dst)>;
|
||||
|
||||
// hi-reg truncation : trunc(int16 >> 8)
|
||||
//:FIXME: i think it's better to emit an extract subreg node in the DAG than
|
||||
// all this mess once we get optimal shift code
|
||||
// lol... I think so, too. [@agnat]
|
||||
def : Pat<(i8 (trunc (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr
|
||||
(AVRlsr DREGS:$src)))))))))),
|
||||
def : Pat<(i8 (trunc (AVRlsr8 DREGS:$src))),
|
||||
(EXTRACT_SUBREG DREGS:$src, sub_hi)>;
|
||||
|
||||
// :FIXME: DAGCombiner produces an shl node after legalization from these seq:
|
||||
|
||||
@ -178,3 +178,93 @@ define i8 @asr_i8_7(i8 %a) {
|
||||
%result = ashr i8 %a, 7
|
||||
ret i8 %result
|
||||
}
|
||||
|
||||
define i16 @lsl_i16_5(i16 %a) {
|
||||
; CHECK-LABEL: lsl_i16_5
|
||||
; CHECK: swap r25
|
||||
; CHECK-NEXT: swap r24
|
||||
; CHECK-NEXT: andi r25, 240
|
||||
; CHECK-NEXT: eor r25, r24
|
||||
; CHECK-NEXT: andi r24, 240
|
||||
; CHECK-NEXT: eor r25, r24
|
||||
; CHECK-NEXT: lsl r24
|
||||
; CHECK-NEXT: rol r25
|
||||
; CHECK-NEXT: ret
|
||||
%result = shl i16 %a, 5
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
define i16 @lsl_i16_9(i16 %a) {
|
||||
; CHECK-LABEL: lsl_i16_9
|
||||
; CHECK: mov r25, r24
|
||||
; CHECK-NEXT: clr r24
|
||||
; CHECK-NEXT: lsl r24
|
||||
; CHECK-NEXT: rol r25
|
||||
; CHECK-NEXT: ret
|
||||
%result = shl i16 %a, 9
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
define i16 @lsl_i16_13(i16 %a) {
|
||||
; CHECK-LABEL: lsl_i16_13
|
||||
; CHECK: mov r25, r24
|
||||
; CHECK-NEXT: swap r25
|
||||
; CHECK-NEXT: andi r25, 240
|
||||
; CHECK-NEXT: clr r24
|
||||
; CHECK-NEXT: lsl r24
|
||||
; CHECK-NEXT: rol r25
|
||||
; CHECK-NEXT: ret
|
||||
%result = shl i16 %a, 13
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
define i16 @lsr_i16_5(i16 %a) {
|
||||
; CHECK-LABEL: lsr_i16_5
|
||||
; CHECK: swap r25
|
||||
; CHECK-NEXT: swap r24
|
||||
; CHECK-NEXT: andi r24, 15
|
||||
; CHECK-NEXT: eor r24, r25
|
||||
; CHECK-NEXT: andi r25, 15
|
||||
; CHECK-NEXT: eor r24, r25
|
||||
; CHECK-NEXT: lsr r25
|
||||
; CHECK-NEXT: ror r24
|
||||
; CHECK-NEXT: ret
|
||||
%result = lshr i16 %a, 5
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
define i16 @lsr_i16_9(i16 %a) {
|
||||
; CHECK-LABEL: lsr_i16_9
|
||||
; CHECK: mov r24, r25
|
||||
; CHECK-NEXT: clr r25
|
||||
; CHECK-NEXT: lsr r25
|
||||
; CHECK-NEXT: ror r24
|
||||
; CHECK-NEXT: ret
|
||||
%result = lshr i16 %a, 9
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
define i16 @lsr_i16_13(i16 %a) {
|
||||
; CHECK-LABEL: lsr_i16_13
|
||||
; CHECK: mov r24, r25
|
||||
; CHECK-NEXT: swap r24
|
||||
; CHECK-NEXT: andi r24, 15
|
||||
; CHECK-NEXT: clr r25
|
||||
; CHECK-NEXT: lsr r25
|
||||
; CHECK-NEXT: ror r24
|
||||
; CHECK-NEXT: ret
|
||||
%result = lshr i16 %a, 13
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
define i16 @asr_i16_9(i16 %a) {
|
||||
; CHECK-LABEL: asr_i16_9
|
||||
; CHECK: mov r24, r25
|
||||
; CHECK-NEXT: lsl r25
|
||||
; CHECK-NEXT: sbc r25, r25
|
||||
; CHECK-NEXT: asr r25
|
||||
; CHECK-NEXT: ror r24
|
||||
; CHECK-NEXT: ret
|
||||
%result = ashr i16 %a, 9
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user