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[X86] Remove a bunch of 'else' after returns in reduceVMULWidth. NFC

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This reduces indentation and makes it obvious this function always returns something.

llvm-svn: 349671
This commit is contained in:
Craig Topper 2018-12-19 19:39:34 +00:00
parent 5e40209fa5
commit d6124cff35
1 changed files with 73 additions and 74 deletions
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11
lib/Target/X86/X86ISelLowering.cpp
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@ -34866,10 +34866,10 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
// Generate the lower part of mul: pmullw. For MULU8/MULS8, only the // Generate the lower part of mul: pmullw. For MULU8/MULS8, only the
// lower part is needed. // lower part is needed.
SDValue MulLo = DAG.getNode(ISD::MUL, DL, ReducedVT, NewN0, NewN1); SDValue MulLo = DAG.getNode(ISD::MUL, DL, ReducedVT, NewN0, NewN1);
if (Mode == MULU8 || Mode == MULS8) { if (Mode == MULU8 || Mode == MULS8)
return DAG.getNode((Mode == MULU8) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND, return DAG.getNode((Mode == MULU8) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND,
DL, VT, MulLo); DL, VT, MulLo);
} else {
MVT ResVT = MVT::getVectorVT(MVT::i32, NumElts / 2); MVT ResVT = MVT::getVectorVT(MVT::i32, NumElts / 2);
// Generate the higher part of mul: pmulhw/pmulhuw. For MULU16/MULS16, // Generate the higher part of mul: pmulhw/pmulhuw. For MULU16/MULS16,
// the higher part is also needed. // the higher part is also needed.
@ -34897,7 +34897,7 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
ResHi = DAG.getBitcast(ResVT, ResHi); ResHi = DAG.getBitcast(ResVT, ResHi);
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ResLo, ResHi); return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ResLo, ResHi);
} }
} else {
// When VT.getVectorNumElements() < OpsVT.getVectorNumElements(), we want // When VT.getVectorNumElements() < OpsVT.getVectorNumElements(), we want
// to legalize the mul explicitly because implicit legalization for type // to legalize the mul explicitly because implicit legalization for type
// <4 x i16> to <4 x i32> sometimes involves unnecessary unpack // <4 x i16> to <4 x i32> sometimes involves unnecessary unpack
@ -34930,7 +34930,8 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
DL, ResVT, Mul); DL, ResVT, Mul);
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
DAG.getIntPtrConstant(0, DL)); DAG.getIntPtrConstant(0, DL));
} else { }
// Generate the lower and higher part of mul: pmulhw/pmulhuw. For // Generate the lower and higher part of mul: pmulhw/pmulhuw. For
// MULU16/MULS16, both parts are needed. // MULU16/MULS16, both parts are needed.
SDValue MulLo = DAG.getNode(ISD::MUL, DL, OpsVT, NewN0, NewN1); SDValue MulLo = DAG.getNode(ISD::MUL, DL, OpsVT, NewN0, NewN1);
@ -34944,8 +34945,6 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
Res = DAG.getBitcast(ResVT, Res); Res = DAG.getBitcast(ResVT, Res);
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
DAG.getIntPtrConstant(0, DL)); DAG.getIntPtrConstant(0, DL));
}
}
} }
static SDValue combineMulSpecial(uint64_t MulAmt, SDNode *N, SelectionDAG &DAG, static SDValue combineMulSpecial(uint64_t MulAmt, SDNode *N, SelectionDAG &DAG,