mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
refactor the conditional jump instructions in the .td file to
use a multipattern that generates both the 1-byte and 4-byte versions from the same defm llvm-svn: 95901
This commit is contained in:
Chris Lattner
parent
472348ab92
commit
d69e1c1bb2
@ -828,30 +828,30 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
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std::swap(TrueMBB, FalseMBB);
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Predicate = CmpInst::FCMP_UNE;
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// FALL THROUGH
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case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
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case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
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case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
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case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
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case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
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case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
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case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
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case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
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case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
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case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
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case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
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case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
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case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
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case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
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case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
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case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
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case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
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case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
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case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
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case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
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case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
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case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
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case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
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case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
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case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
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case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
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case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
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case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
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case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
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case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
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case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
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case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
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case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
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case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
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case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
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case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
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case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
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case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
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case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
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case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
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case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
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case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
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case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
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case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
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case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
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case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
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default:
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return false;
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}
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@ -869,7 +869,7 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
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if (Predicate == CmpInst::FCMP_UNE) {
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// X86 requires a second branch to handle UNE (and OEQ,
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// which is mapped to UNE above).
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BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
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BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
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}
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FastEmitBranch(FalseMBB);
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@ -923,7 +923,8 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
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unsigned OpCode = SetMI->getOpcode();
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if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
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BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB))
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BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
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X86::JO_4 : X86::JB_4))
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.addMBB(TrueMBB);
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FastEmitBranch(FalseMBB);
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MBB->addSuccessor(TrueMBB);
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@ -939,7 +940,7 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
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if (OpReg == 0) return false;
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BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
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BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
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BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
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FastEmitBranch(FalseMBB);
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MBB->addSuccessor(TrueMBB);
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return true;
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@ -1652,8 +1652,8 @@ static bool HasNoSignedComparisonUses(SDNode *N) {
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case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
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case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
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case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
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case X86::JA: case X86::JAE: case X86::JB: case X86::JBE:
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case X86::JE: case X86::JNE: case X86::JP: case X86::JNP:
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case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
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case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
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case X86::CMOVA16rr: case X86::CMOVA16rm:
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case X86::CMOVA32rr: case X86::CMOVA32rm:
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case X86::CMOVA64rr: case X86::CMOVA64rm:
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@ -7934,7 +7934,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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MIB.addReg(EAXreg);
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// insert branch
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BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
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BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
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F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
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return nextMBB;
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@ -8091,7 +8091,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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MIB.addReg(X86::EDX);
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// insert branch
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BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
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BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
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F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
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return nextMBB;
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@ -8194,7 +8194,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
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MIB.addReg(X86::EAX);
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// insert branch
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BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
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BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
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F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
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return nextMBB;
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@ -8276,7 +8276,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
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if (!Subtarget->isTargetWin64()) {
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// If %al is 0, branch around the XMM save block.
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BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
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BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
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BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
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MBB->addSuccessor(EndMBB);
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}
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@ -1587,44 +1587,44 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
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switch (BrOpc) {
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default: return X86::COND_INVALID;
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case X86::JE: return X86::COND_E;
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case X86::JNE: return X86::COND_NE;
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case X86::JL: return X86::COND_L;
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case X86::JLE: return X86::COND_LE;
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case X86::JG: return X86::COND_G;
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case X86::JGE: return X86::COND_GE;
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case X86::JB: return X86::COND_B;
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case X86::JBE: return X86::COND_BE;
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case X86::JA: return X86::COND_A;
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case X86::JAE: return X86::COND_AE;
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case X86::JS: return X86::COND_S;
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case X86::JNS: return X86::COND_NS;
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case X86::JP: return X86::COND_P;
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case X86::JNP: return X86::COND_NP;
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case X86::JO: return X86::COND_O;
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case X86::JNO: return X86::COND_NO;
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case X86::JE_4: return X86::COND_E;
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case X86::JNE_4: return X86::COND_NE;
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case X86::JL_4: return X86::COND_L;
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case X86::JLE_4: return X86::COND_LE;
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case X86::JG_4: return X86::COND_G;
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case X86::JGE_4: return X86::COND_GE;
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case X86::JB_4: return X86::COND_B;
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case X86::JBE_4: return X86::COND_BE;
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case X86::JA_4: return X86::COND_A;
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case X86::JAE_4: return X86::COND_AE;
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case X86::JS_4: return X86::COND_S;
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case X86::JNS_4: return X86::COND_NS;
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case X86::JP_4: return X86::COND_P;
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case X86::JNP_4: return X86::COND_NP;
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case X86::JO_4: return X86::COND_O;
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case X86::JNO_4: return X86::COND_NO;
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}
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}
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unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case X86::COND_E: return X86::JE;
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case X86::COND_NE: return X86::JNE;
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case X86::COND_L: return X86::JL;
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case X86::COND_LE: return X86::JLE;
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case X86::COND_G: return X86::JG;
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case X86::COND_GE: return X86::JGE;
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case X86::COND_B: return X86::JB;
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case X86::COND_BE: return X86::JBE;
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case X86::COND_A: return X86::JA;
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case X86::COND_AE: return X86::JAE;
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case X86::COND_S: return X86::JS;
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case X86::COND_NS: return X86::JNS;
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case X86::COND_P: return X86::JP;
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case X86::COND_NP: return X86::JNP;
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case X86::COND_O: return X86::JO;
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case X86::COND_NO: return X86::JNO;
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case X86::COND_E: return X86::JE_4;
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case X86::COND_NE: return X86::JNE_4;
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case X86::COND_L: return X86::JL_4;
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case X86::COND_LE: return X86::JLE_4;
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case X86::COND_G: return X86::JG_4;
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case X86::COND_GE: return X86::JGE_4;
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case X86::COND_B: return X86::JB_4;
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case X86::COND_BE: return X86::JBE_4;
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case X86::COND_A: return X86::JA_4;
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case X86::COND_AE: return X86::JAE_4;
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case X86::COND_S: return X86::JS_4;
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case X86::COND_NS: return X86::JNS_4;
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case X86::COND_P: return X86::JP_4;
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case X86::COND_NP: return X86::JNP_4;
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case X86::COND_O: return X86::JO_4;
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case X86::COND_NO: return X86::JNO_4;
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}
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}
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@ -1694,7 +1694,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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return true;
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// Handle unconditional branches.
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if (I->getOpcode() == X86::JMP) {
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if (I->getOpcode() == X86::JMP_4) {
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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@ -1778,7 +1778,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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while (I != MBB.begin()) {
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--I;
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if (I->getOpcode() != X86::JMP &&
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if (I->getOpcode() != X86::JMP_4 &&
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GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
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break;
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// Remove the branch.
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@ -1804,7 +1804,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
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BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
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return 1;
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}
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@ -1814,16 +1814,16 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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switch (CC) {
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case X86::COND_NP_OR_E:
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// Synthesize NP_OR_E with two branches.
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BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
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BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
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++Count;
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BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
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BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
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++Count;
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break;
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case X86::COND_NE_OR_P:
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// Synthesize NE_OR_P with two branches.
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BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
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BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
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++Count;
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BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
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BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
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++Count;
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break;
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default: {
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@ -1834,7 +1834,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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}
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if (FBB) {
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// Two-way Conditional branch. Insert the second branch.
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BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
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BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
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++Count;
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}
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return Count;
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@ -596,7 +596,7 @@ let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
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"", []>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions...
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// Control Flow Instructions.
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//
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// Return instructions.
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@ -615,15 +615,47 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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}
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// All branches are RawFrm, Void, Branch, and Terminators
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// Unconditional branches.
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let isBranch = 1, isTerminator = 1 in
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class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
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I<opcode, RawFrm, (outs), ins, asm, pattern>;
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let isBranch = 1, isBarrier = 1 in {
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def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
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def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
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let isBarrier = 1 in {
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def JMP_4 : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
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def JMP_1 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
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multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
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def _1 : I<opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
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def _4 : I<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
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[(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
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}
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}
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defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
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defm JNO : ICBr<0x71, 0x81, "jo\t$dst" , X86_COND_NO>;
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defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
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defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
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defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
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defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
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defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
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defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
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defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
|
||||
defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
|
||||
defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
|
||||
defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
|
||||
defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
|
||||
defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
|
||||
defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
|
||||
defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
|
||||
|
||||
// FIXME: What about the CX/RCX versions of this instruction?
|
||||
let Uses = [ECX] in
|
||||
def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
|
||||
|
||||
|
||||
// Indirect branches
|
||||
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
|
||||
@ -644,63 +676,6 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
"ljmp{l}\t{*}$dst", []>;
|
||||
}
|
||||
|
||||
// Conditional branches
|
||||
let Uses = [EFLAGS] in {
|
||||
// Short conditional jumps
|
||||
def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
|
||||
def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
|
||||
def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
|
||||
def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
|
||||
def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
|
||||
def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
|
||||
def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
|
||||
def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
|
||||
def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
|
||||
def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
|
||||
def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
|
||||
def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
|
||||
def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
|
||||
def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
|
||||
def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
|
||||
def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
|
||||
|
||||
def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
|
||||
|
||||
def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
|
||||
def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
|
||||
def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
|
||||
def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
|
||||
def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
|
||||
def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
|
||||
|
||||
def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
|
||||
def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
|
||||
def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
|
||||
def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
|
||||
|
||||
def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
|
||||
def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
|
||||
def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
|
||||
def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
|
||||
def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
|
||||
def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
|
||||
[(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
|
||||
} // Uses = [EFLAGS]
|
||||
|
||||
// Loop instructions
|
||||
|
||||
|
||||
@ -571,6 +571,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
|
||||
// If there is a remaining operand, it must be a trailing immediate. Emit it
|
||||
// according to the right size for the instruction.
|
||||
// FIXME: This should pass in whether the value is pc relative or not. This
|
||||
// information should be aquired from TSFlags as well.
|
||||
if (CurOp != NumOps)
|
||||
EmitImmediate(MI.getOperand(CurOp++), X86II::getSizeOfImm(TSFlags),
|
||||
CurByte, OS, Fixups);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user