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ARM: stop asserting on weird <3 x Ty> vectors in ISelLowering.

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llvm-svn: 263741
This commit is contained in:
Tim Northover 2016-03-17 20:10:28 +00:00
parent e634bbeadd
commit d69f4092d3
3 changed files with 19 additions and 2 deletions
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5
lib/Target/ARM/ARMISelLowering.cpp
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@ -10124,7 +10124,8 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
SDValue Op = N->getOperand(0);
if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
Op.getOpcode() != ISD::FMUL)
return SDValue();
SDValue ConstVec = Op->getOperand(1);
@ -10181,7 +10182,7 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
SDValue Op = N->getOperand(0);
unsigned OpOpcode = Op.getNode()->getOpcode();
if (!N->getValueType(0).isVector() ||
if (!N->getValueType(0).isVector() || !N->getValueType(0).isSimple() ||
(OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
return SDValue();

8
test/CodeGen/ARM/vcvt_combine.ll
View File

@ -62,3 +62,11 @@ define <4 x i32> @t5(<4 x float> %in) {
%vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
ret <4 x i32> %vcvt.i
}
; CHECK-LABEL: test_illegal_fp_to_int:
; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2
define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
%scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
%val = fptosi <3 x float> %scale to <3 x i32>
ret <3 x i32> %val
}

8
test/CodeGen/ARM/vdiv_combine.ll
View File

@ -153,3 +153,11 @@ define <4 x float> @test8(<4 x i32> %in) {
%div.i = fdiv <4 x float> %vcvt.i, <float 2.0, float 2.0, float 2.0, float undef>
ret <4 x float> %div.i
}
; CHECK-LABEL: test_illegal_int_to_fp:
; CHECK: vcvt.f32.s32
define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) {
%conv = sitofp <3 x i32> %in to <3 x float>
%res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0>
ret <3 x float> %res
}