RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected

Browse Source 
This is necessary to avoid an assertion in the included test case and similar 
assembler inputs.

llvm-svn: 316168
This commit is contained in:
Alex Bradbury 2017-10-19 16:22:51 +00:00
parent 082e584fbd
commit d6a686e827
2 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
View File

@ -146,6 +146,8 @@ public:
template <int N> bool isBareSimmNLsb0() const { template <int N> bool isBareSimmNLsb0() const {
int64_t Imm; int64_t Imm;
RISCVMCExpr::VariantKind VK; RISCVMCExpr::VariantKind VK;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(Imm, VK); bool IsConstantImm = evaluateConstantImm(Imm, VK);
bool IsValid; bool IsValid;
if (!IsConstantImm) if (!IsConstantImm)
@ -185,6 +187,8 @@ public:
bool isUImm5() const { bool isUImm5() const {
int64_t Imm; int64_t Imm;
RISCVMCExpr::VariantKind VK; RISCVMCExpr::VariantKind VK;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(Imm, VK); bool IsConstantImm = evaluateConstantImm(Imm, VK);
return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
} }
@ -193,6 +197,8 @@ public:
RISCVMCExpr::VariantKind VK; RISCVMCExpr::VariantKind VK;
int64_t Imm; int64_t Imm;
bool IsValid; bool IsValid;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(Imm, VK); bool IsConstantImm = evaluateConstantImm(Imm, VK);
if (!IsConstantImm) if (!IsConstantImm)
IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
@ -205,6 +211,8 @@ public:
bool isUImm12() const { bool isUImm12() const {
int64_t Imm; int64_t Imm;
RISCVMCExpr::VariantKind VK; RISCVMCExpr::VariantKind VK;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(Imm, VK); bool IsConstantImm = evaluateConstantImm(Imm, VK);
return IsConstantImm && isUInt<12>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; return IsConstantImm && isUInt<12>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
} }
@ -215,6 +223,8 @@ public:
RISCVMCExpr::VariantKind VK; RISCVMCExpr::VariantKind VK;
int64_t Imm; int64_t Imm;
bool IsValid; bool IsValid;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(Imm, VK); bool IsConstantImm = evaluateConstantImm(Imm, VK);
if (!IsConstantImm) if (!IsConstantImm)
IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);

3
test/MC/RISCV/rv32i-invalid.s
View File

@ -122,6 +122,9 @@ sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
# Memory operand not formatted correctly
lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2048, 2047]
# Too few operands # Too few operands
ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction