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[CodeGen] Make use of MachineInstrBuilder::getReg

Browse Source 
Reviewers: arsenm

Subscribers: wdng, hiraditya, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73262
This commit is contained in:
Jay Foad 2020-01-23 11:51:35 +00:00
parent 41ea30c256
commit d6a7ab5e54
13 changed files with 159 additions and 163 deletions
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2
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
View File

@ -129,7 +129,7 @@ CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
if (DstOps.size() == 1) {
const DstOp &Op = DstOps[0];
if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg)
return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());
return buildCopy(Op.getReg(), MIB.getReg(0));
}
return MIB;
}

2
lib/CodeGen/GlobalISel/CallLowering.cpp
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@ -469,7 +469,7 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg,
return ValReg;
case CCValAssign::AExt: {
auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
return MIB->getOperand(0).getReg();
return MIB.getReg(0);
}
case CCValAssign::SExt: {
Register NewReg = MRI.createGenericVirtualRegister(LocTy);

2
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -1916,7 +1916,7 @@ bool IRTranslator::translateExtractElement(const User &U,
Idx = getOrCreateVReg(*U.getOperand(1));
if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
const LLT &VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0);
}
MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
return true;

33
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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@ -751,7 +751,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
SmallVector<Register, 2> DstRegs;
for (int i = 0; i < NumParts; ++i)
DstRegs.push_back(
MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
MIRBuilder.buildUndef(NarrowTy).getReg(0));
Register DstReg = MI.getOperand(0).getReg();
if(MRI.getType(DstReg).isVector())
@ -1091,7 +1091,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
// sign-extending the dst.
MachineOperand &MO1 = MI.getOperand(1);
auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
MO1.setReg(TruncMIB->getOperand(0).getReg());
MO1.setReg(TruncMIB.getReg(0));
MachineOperand &MO2 = MI.getOperand(0);
Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
@ -1127,8 +1127,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Register AshrCstReg =
MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
->getOperand(0)
.getReg();
.getReg(0);
Register FullExtensionReg = 0;
Register PartialExtensionReg = 0;
@ -1145,8 +1144,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
}
DstRegs.push_back(
MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
->getOperand(0)
.getReg());
.getReg(0));
FullExtensionReg = DstRegs.back();
} else {
DstRegs.push_back(
@ -1154,8 +1152,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
.buildInstr(
TargetOpcode::G_SEXT_INREG, {NarrowTy},
{SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
->getOperand(0)
.getReg());
.getReg(0));
PartialExtensionReg = DstRegs.back();
}
}
@ -1195,14 +1192,14 @@ void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
unsigned OpIdx, unsigned ExtOpcode) {
MachineOperand &MO = MI.getOperand(OpIdx);
auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
MO.setReg(ExtB->getOperand(0).getReg());
MO.setReg(ExtB.getReg(0));
}
void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
unsigned OpIdx) {
MachineOperand &MO = MI.getOperand(OpIdx);
auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
MO.setReg(ExtB->getOperand(0).getReg());
MO.setReg(ExtB.getReg(0));
}
void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
@ -1415,7 +1412,7 @@ LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
Observer.changingInstr(MI);
MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
MI.getOperand(NumDst).setReg(WideSrc.getReg(0));
for (unsigned I = 0; I != NumDst; ++I)
widenScalarDst(MI, WideTy, I);
@ -2145,7 +2142,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
*cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
Register SubByReg = MI.getOperand(1).getReg();
Register ZeroReg = Zero->getOperand(0).getReg();
Register ZeroReg = Zero.getReg(0);
MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
MI.eraseFromParent();
return Legalized;
@ -3769,14 +3766,14 @@ LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
{Src0Regs[I], Src1Regs[I]});
DstRegs.push_back(Inst->getOperand(0).getReg());
DstRegs.push_back(Inst.getReg(0));
}
for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
auto Inst = MIRBuilder.buildInstr(
MI.getOpcode(),
{LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
DstLeftoverRegs.push_back(Inst.getReg(0));
}
insertParts(DstReg, DstTy, NarrowTy, DstRegs,
@ -3836,13 +3833,13 @@ LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
auto Select = MIRBuilder.buildSelect(NarrowTy,
CondReg, Src1Regs[I], Src2Regs[I]);
DstRegs.push_back(Select->getOperand(0).getReg());
DstRegs.push_back(Select.getReg(0));
}
for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
auto Select = MIRBuilder.buildSelect(
LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
DstLeftoverRegs.push_back(Select.getReg(0));
}
insertParts(DstReg, DstTy, NarrowTy, DstRegs,
@ -3901,7 +3898,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
auto MIBOp =
MIRBuilder.buildOr(Ty, Op, MIRBuilder.buildLShr(Ty, Op, MIBShiftAmt));
Op = MIBOp->getOperand(0).getReg();
Op = MIBOp.getReg(0);
}
auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op);
MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(Ty, Len),
@ -3948,7 +3945,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
return Legalized;
}
MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
MI.getOperand(1).setReg(MIBTmp.getReg(0));
return Legalized;
}
}

2
lib/CodeGen/MachineSSAUpdater.cpp
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@ -204,7 +204,7 @@ unsigned MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB) {
if (InsertedPHIs) InsertedPHIs->push_back(InsertedPHI);
LLVM_DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n");
return InsertedPHI->getOperand(0).getReg();
return InsertedPHI.getReg(0);
}
static

3
lib/Target/AArch64/AArch64CallLowering.cpp
View File

@ -178,8 +178,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
Size = VA.getLocVT().getSizeInBits() / 8;
ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg)
->getOperand(0)
.getReg();
.getReg(0);
}
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
MPO, MachineMemOperand::MOStore, Size, 1);

28
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -239,17 +239,17 @@ static bool selectMergeValues(MachineInstrBuilder &MIB,
// We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
// into one DPR.
Register VReg0 = MIB->getOperand(0).getReg();
Register VReg0 = MIB.getReg(0);
(void)VReg0;
assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
"Unsupported operand for G_MERGE_VALUES");
Register VReg1 = MIB->getOperand(1).getReg();
Register VReg1 = MIB.getReg(1);
(void)VReg1;
assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
"Unsupported operand for G_MERGE_VALUES");
Register VReg2 = MIB->getOperand(2).getReg();
Register VReg2 = MIB.getReg(2);
(void)VReg2;
assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
@ -271,17 +271,17 @@ static bool selectUnmergeValues(MachineInstrBuilder &MIB,
// We only support G_UNMERGE_VALUES as a way to break up one DPR into two
// GPRs.
Register VReg0 = MIB->getOperand(0).getReg();
Register VReg0 = MIB.getReg(0);
(void)VReg0;
assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
"Unsupported operand for G_UNMERGE_VALUES");
Register VReg1 = MIB->getOperand(1).getReg();
Register VReg1 = MIB.getReg(1);
(void)VReg1;
assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
"Unsupported operand for G_UNMERGE_VALUES");
Register VReg2 = MIB->getOperand(2).getReg();
Register VReg2 = MIB.getReg(2);
(void)VReg2;
assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
@ -530,7 +530,7 @@ bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
MachineRegisterInfo &MRI) const {
const InsertInfo I(MIB);
auto ResReg = MIB->getOperand(0).getReg();
auto ResReg = MIB.getReg(0);
if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
return false;
@ -542,8 +542,8 @@ bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
return true;
}
auto LHSReg = MIB->getOperand(2).getReg();
auto RHSReg = MIB->getOperand(3).getReg();
auto LHSReg = MIB.getReg(2);
auto RHSReg = MIB.getReg(3);
if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
Helper.OperandRegBankID))
return false;
@ -687,7 +687,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
if (Indirect) {
if (!UseOpcodeThatLoads) {
auto ResultReg = MIB->getOperand(0).getReg();
auto ResultReg = MIB.getReg(0);
auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
MIB->getOperand(0).setReg(AddressReg);
@ -773,7 +773,7 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
auto &DbgLoc = MIB->getDebugLoc();
// Compare the condition to 1.
auto CondReg = MIB->getOperand(1).getReg();
auto CondReg = MIB.getReg(1);
assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
"Unsupported types for select operation");
auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
@ -785,9 +785,9 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
// Move a value into the result register based on the result of the
// comparison.
auto ResReg = MIB->getOperand(0).getReg();
auto TrueReg = MIB->getOperand(2).getReg();
auto FalseReg = MIB->getOperand(3).getReg();
auto ResReg = MIB.getReg(0);
auto TrueReg = MIB.getReg(2);
auto FalseReg = MIB.getReg(3);
assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
"Unsupported types for select operation");

2
lib/Target/X86/X86CallLowering.cpp
View File

@ -139,7 +139,7 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
if (PhysRegSize > ValSize && LocSize == ValSize) {
assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
ExtReg = MIB->getOperand(0).getReg();
ExtReg = MIB.getReg(0);
} else
ExtReg = extendRegister(ValVReg, VA);

34
lib/Target/X86/X86InstrInfo.cpp
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@ -3877,15 +3877,15 @@ MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
const MCInstrDesc &Desc) {
assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Register Reg = MIB->getOperand(0).getReg();
Register Reg = MIB.getReg(0);
MIB->setDesc(Desc);
// MachineInstr::addOperand() will insert explicit operands before any
// implicit operands.
MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
// But we don't trust that.
assert(MIB->getOperand(1).getReg() == Reg &&
MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
assert(MIB.getReg(1) == Reg &&
MIB.getReg(2) == Reg && "Misplaced operand");
return true;
}
@ -3907,7 +3907,7 @@ static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
bool MinusOne) {
MachineBasicBlock &MBB = *MIB->getParent();
DebugLoc DL = MIB->getDebugLoc();
Register Reg = MIB->getOperand(0).getReg();
Register Reg = MIB.getReg(0);
// Insert the XOR.
BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
@ -3951,7 +3951,7 @@ static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
MIB->setDesc(TII.get(X86::POP64r));
MIB->getOperand(0)
.setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
.setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
} else {
assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
StackAdjustment = 4;
@ -3981,7 +3981,7 @@ static void expandLoadStackGuard(MachineInstrBuilder &MIB,
const TargetInstrInfo &TII) {
MachineBasicBlock &MBB = *MIB->getParent();
DebugLoc DL = MIB->getDebugLoc();
Register Reg = MIB->getOperand(0).getReg();
Register Reg = MIB.getReg(0);
const GlobalValue *GV =
cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
auto Flags = MachineMemOperand::MOLoad |
@ -4019,7 +4019,7 @@ static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
const MCInstrDesc &LoadDesc,
const MCInstrDesc &BroadcastDesc,
unsigned SubIdx) {
Register DestReg = MIB->getOperand(0).getReg();
Register DestReg = MIB.getReg(0);
// Check if DestReg is XMM16-31 or YMM16-31.
if (TRI->getEncodingValue(DestReg) < 16) {
// We can use a normal VEX encoded load.
@ -4042,7 +4042,7 @@ static bool expandNOVLXStore(MachineInstrBuilder &MIB,
const MCInstrDesc &StoreDesc,
const MCInstrDesc &ExtractDesc,
unsigned SubIdx) {
Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
Register SrcReg = MIB.getReg(X86::AddrNumOperands);
// Check if DestReg is XMM16-31 or YMM16-31.
if (TRI->getEncodingValue(SrcReg) < 16) {
// We can use a normal VEX encoded store.
@ -4065,7 +4065,7 @@ static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
// Temporarily remove the immediate so we can add another source register.
MIB->RemoveOperand(2);
// Add the register. Don't copy the kill flag if there is one.
MIB.addReg(MIB->getOperand(1).getReg(),
MIB.addReg(MIB.getReg(1),
getUndefRegState(MIB->getOperand(1).isUndef()));
// Add back the immediate.
MIB.addImm(ShiftAmt);
@ -4103,7 +4103,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::AVX_SET0: {
assert(HasAVX && "AVX not supported");
const TargetRegisterInfo *TRI = &getRegisterInfo();
Register SrcReg = MIB->getOperand(0).getReg();
Register SrcReg = MIB.getReg(0);
Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
MIB->getOperand(0).setReg(XReg);
Expand2AddrUndef(MIB, get(X86::VXORPSrr));
@ -4115,7 +4115,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::AVX512_FsFLD0SD:
case X86::AVX512_FsFLD0F128: {
bool HasVLX = Subtarget.hasVLX();
Register SrcReg = MIB->getOperand(0).getReg();
Register SrcReg = MIB.getReg(0);
const TargetRegisterInfo *TRI = &getRegisterInfo();
if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
return Expand2AddrUndef(MIB,
@ -4129,7 +4129,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::AVX512_256_SET0:
case X86::AVX512_512_SET0: {
bool HasVLX = Subtarget.hasVLX();
Register SrcReg = MIB->getOperand(0).getReg();
Register SrcReg = MIB.getReg(0);
const TargetRegisterInfo *TRI = &getRegisterInfo();
if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
@ -4152,14 +4152,14 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::AVX2_SETALLONES:
return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
case X86::AVX1_SETALLONES: {
Register Reg = MIB->getOperand(0).getReg();
Register Reg = MIB.getReg(0);
// VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
MIB->setDesc(get(X86::VCMPPSYrri));
MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
return true;
}
case X86::AVX512_512_SETALLONES: {
Register Reg = MIB->getOperand(0).getReg();
Register Reg = MIB.getReg(0);
MIB->setDesc(get(X86::VPTERNLOGDZrri));
// VPTERNLOGD needs 3 register inputs and an immediate.
// 0xff will return 1s for any input.
@ -4169,8 +4169,8 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
}
case X86::AVX512_512_SEXT_MASK_32:
case X86::AVX512_512_SEXT_MASK_64: {
Register Reg = MIB->getOperand(0).getReg();
Register MaskReg = MIB->getOperand(1).getReg();
Register Reg = MIB.getReg(0);
Register MaskReg = MIB.getReg(1);
unsigned MaskState = getRegState(MIB->getOperand(1));
unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
@ -4207,7 +4207,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
case X86::MOV32ri64: {
Register Reg = MIB->getOperand(0).getReg();
Register Reg = MIB.getReg(0);
Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
MI.setDesc(get(X86::MOV32ri));
MIB->getOperand(0).setReg(Reg32);

8
unittests/CodeGen/GlobalISel/CSETest.cpp
View File

@ -60,13 +60,13 @@ TEST_F(GISelMITest, TestCSE) {
// CSE.
auto Splat0 = CSEB.buildConstant(LLT::vector(2, s32), 0);
EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, Splat0->getOpcode());
EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0->getOperand(1).getReg()));
EXPECT_EQ(Splat0.getReg(1), Splat0.getReg(2));
EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0.getReg(1)));
auto FSplat = CSEB.buildFConstant(LLT::vector(2, s32), 1.0);
EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, FSplat->getOpcode());
EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat->getOperand(1).getReg()));
EXPECT_EQ(FSplat.getReg(1), FSplat.getReg(2));
EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat.getReg(1)));
// Check G_UNMERGE_VALUES
auto MIBUnmerge = CSEB.buildUnmerge({s32, s32}, Copies[0]);

114
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp
View File

@ -28,14 +28,14 @@ TEST_F(GISelMITest, FoldWithBuilder) {
auto MIBCAdd =
CFB.buildAdd(s32, CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1));
// This should be a constant now.
bool match = mi_match(MIBCAdd->getOperand(0).getReg(), *MRI, m_ICst(Cst));
bool match = mi_match(MIBCAdd.getReg(0), *MRI, m_ICst(Cst));
EXPECT_TRUE(match);
EXPECT_EQ(Cst, 1);
auto MIBCAdd1 =
CFB.buildInstr(TargetOpcode::G_ADD, {s32},
{CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1)});
// This should be a constant now.
match = mi_match(MIBCAdd1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
match = mi_match(MIBCAdd1.getReg(0), *MRI, m_ICst(Cst));
EXPECT_TRUE(match);
EXPECT_EQ(Cst, 1);
@ -47,7 +47,7 @@ TEST_F(GISelMITest, FoldWithBuilder) {
CFB1.buildInstr(TargetOpcode::G_SUB, {s32},
{CFB1.buildConstant(s32, 1), CFB1.buildConstant(s32, 1)});
// This should be a constant now.
match = mi_match(MIBCSub->getOperand(0).getReg(), *MRI, m_ICst(Cst));
match = mi_match(MIBCSub.getReg(0), *MRI, m_ICst(Cst));
EXPECT_TRUE(match);
EXPECT_EQ(Cst, 0);
@ -55,7 +55,7 @@ TEST_F(GISelMITest, FoldWithBuilder) {
CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32},
{CFB1.buildConstant(s32, 0x01), uint64_t(8)});
// This should be a constant now.
match = mi_match(MIBCSext1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
match = mi_match(MIBCSext1.getReg(0), *MRI, m_ICst(Cst));
EXPECT_TRUE(match);
EXPECT_EQ(1, Cst);
@ -63,7 +63,7 @@ TEST_F(GISelMITest, FoldWithBuilder) {
CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32},
{CFB1.buildConstant(s32, 0x80), uint64_t(8)});
// This should be a constant now.
match = mi_match(MIBCSext2->getOperand(0).getReg(), *MRI, m_ICst(Cst));
match = mi_match(MIBCSext2.getReg(0), *MRI, m_ICst(Cst));
EXPECT_TRUE(match);
EXPECT_EQ(-0x80, Cst);
}
@ -81,157 +81,157 @@ TEST_F(GISelMITest, FoldBinOp) {
// Test G_ADD folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGAddInt =
ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGAddInt.hasValue());
EXPECT_EQ(25ULL, FoldGAddInt.getValue().getLimitedValue());
Optional<APInt> FoldGAddMix =
ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGAddMix.hasValue());
EXPECT_EQ(1073741840ULL, FoldGAddMix.getValue().getLimitedValue());
// Test G_AND folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGAndInt =
ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGAndInt.hasValue());
EXPECT_EQ(0ULL, FoldGAndInt.getValue().getLimitedValue());
Optional<APInt> FoldGAndMix =
ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2->getOperand(0).getReg(),
MIBFCst1->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2.getReg(0),
MIBFCst1.getReg(0), *MRI);
EXPECT_TRUE(FoldGAndMix.hasValue());
EXPECT_EQ(1ULL, FoldGAndMix.getValue().getLimitedValue());
// Test G_ASHR folding Integer + Mixed cases
Optional<APInt> FoldGAShrInt =
ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGAShrInt.hasValue());
EXPECT_EQ(0ULL, FoldGAShrInt.getValue().getLimitedValue());
Optional<APInt> FoldGAShrMix =
ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGAShrMix.hasValue());
EXPECT_EQ(2097152ULL, FoldGAShrMix.getValue().getLimitedValue());
// Test G_LSHR folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGLShrInt =
ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGLShrInt.hasValue());
EXPECT_EQ(0ULL, FoldGLShrInt.getValue().getLimitedValue());
Optional<APInt> FoldGLShrMix =
ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGLShrMix.hasValue());
EXPECT_EQ(2080768ULL, FoldGLShrMix.getValue().getLimitedValue());
// Test G_MUL folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGMulInt =
ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGMulInt.hasValue());
EXPECT_EQ(144ULL, FoldGMulInt.getValue().getLimitedValue());
Optional<APInt> FoldGMulMix =
ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGMulMix.hasValue());
EXPECT_EQ(0ULL, FoldGMulMix.getValue().getLimitedValue());
// Test G_OR folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGOrInt =
ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGOrInt.hasValue());
EXPECT_EQ(25ULL, FoldGOrInt.getValue().getLimitedValue());
Optional<APInt> FoldGOrMix =
ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGOrMix.hasValue());
EXPECT_EQ(1073741840ULL, FoldGOrMix.getValue().getLimitedValue());
// Test G_SHL folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGShlInt =
ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGShlInt.hasValue());
EXPECT_EQ(8192ULL, FoldGShlInt.getValue().getLimitedValue());
Optional<APInt> FoldGShlMix =
ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGShlMix.hasValue());
EXPECT_EQ(0ULL, FoldGShlMix.getValue().getLimitedValue());
// Test G_SUB folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGSubInt =
ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGSubInt.hasValue());
EXPECT_EQ(7ULL, FoldGSubInt.getValue().getLimitedValue());
Optional<APInt> FoldGSubMix =
ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGSubMix.hasValue());
EXPECT_EQ(3221225488ULL, FoldGSubMix.getValue().getLimitedValue());
// Test G_XOR folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGXorInt =
ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGXorInt.hasValue());
EXPECT_EQ(25ULL, FoldGXorInt.getValue().getLimitedValue());
Optional<APInt> FoldGXorMix =
ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGXorMix.hasValue());
EXPECT_EQ(1073741840ULL, FoldGXorMix.getValue().getLimitedValue());
// Test G_UDIV folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGUdivInt =
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGUdivInt.hasValue());
EXPECT_EQ(1ULL, FoldGUdivInt.getValue().getLimitedValue());
Optional<APInt> FoldGUdivMix =
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGUdivMix.hasValue());
EXPECT_EQ(0ULL, FoldGUdivMix.getValue().getLimitedValue());
// Test G_SDIV folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGSdivInt =
ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGSdivInt.hasValue());
EXPECT_EQ(1ULL, FoldGSdivInt.getValue().getLimitedValue());
Optional<APInt> FoldGSdivMix =
ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGSdivMix.hasValue());
EXPECT_EQ(0ULL, FoldGSdivMix.getValue().getLimitedValue());
// Test G_UREM folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGUremInt =
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGUremInt.hasValue());
EXPECT_EQ(1ULL, FoldGUremInt.getValue().getLimitedValue());
Optional<APInt> FoldGUremMix =
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGUremMix.hasValue());
EXPECT_EQ(0ULL, FoldGUremMix.getValue().getLimitedValue());
// Test G_SREM folding Integer + Mixed Int-Float cases
Optional<APInt> FoldGSremInt =
ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
MIBCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1.getReg(0),
MIBCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGSremInt.hasValue());
EXPECT_EQ(7ULL, FoldGSremInt.getValue().getLimitedValue());
Optional<APInt> FoldGSremMix =
ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
MIBFCst2->getOperand(0).getReg(), *MRI);
ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1.getReg(0),
MIBFCst2.getReg(0), *MRI);
EXPECT_TRUE(FoldGSremMix.hasValue());
EXPECT_EQ(16ULL, FoldGSremMix.getValue().getLimitedValue());
}

12
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
View File

@ -330,10 +330,10 @@ TEST_F(GISelMITest, BuildMerge) {
return;
LLT S32 = LLT::scalar(32);
Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
Register RegC0 = B.buildConstant(S32, 0).getReg(0);
Register RegC1 = B.buildConstant(S32, 1).getReg(0);
Register RegC2 = B.buildConstant(S32, 2).getReg(0);
Register RegC3 = B.buildConstant(S32, 3).getReg(0);
// Merging plain constants as one big blob of bit should produce a
// G_MERGE_VALUES.
@ -341,9 +341,9 @@ TEST_F(GISelMITest, BuildMerge) {
// Merging plain constants to a vector should produce a G_BUILD_VECTOR.
LLT V2x32 = LLT::vector(2, 32);
Register RegC0C1 =
B.buildMerge(V2x32, {RegC0, RegC1})->getOperand(0).getReg();
B.buildMerge(V2x32, {RegC0, RegC1}).getReg(0);
Register RegC2C3 =
B.buildMerge(V2x32, {RegC2, RegC3})->getOperand(0).getReg();
B.buildMerge(V2x32, {RegC2, RegC3}).getReg(0);
// Merging vector constants to a vector should produce a G_CONCAT_VECTORS.
B.buildMerge(LLT::vector(4, 32), {RegC0C1, RegC2C3});
// Merging vector constants to a plain type is not allowed.

80
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
View File

@ -36,7 +36,7 @@ TEST_F(GISelMITest, MatchIntConstant) {
return;
auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
int64_t Cst;
bool match = mi_match(MIBCst->getOperand(0).getReg(), *MRI, m_ICst(Cst));
bool match = mi_match(MIBCst.getReg(0), *MRI, m_ICst(Cst));
EXPECT_TRUE(match);
EXPECT_EQ(Cst, 42);
}
@ -49,10 +49,10 @@ TEST_F(GISelMITest, MatchBinaryOp) {
auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
// Test case for no bind.
bool match =
mi_match(MIBAdd->getOperand(0).getReg(), *MRI, m_GAdd(m_Reg(), m_Reg()));
mi_match(MIBAdd.getReg(0), *MRI, m_GAdd(m_Reg(), m_Reg()));
EXPECT_TRUE(match);
Register Src0, Src1, Src2;
match = mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
match = mi_match(MIBAdd.getReg(0), *MRI,
m_GAdd(m_Reg(Src0), m_Reg(Src1)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -62,14 +62,14 @@ TEST_F(GISelMITest, MatchBinaryOp) {
auto MIBMul = B.buildMul(s64, MIBAdd, Copies[2]);
// Try to match MUL.
match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
match = mi_match(MIBMul.getReg(0), *MRI,
m_GMul(m_Reg(Src0), m_Reg(Src1)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, MIBAdd->getOperand(0).getReg());
EXPECT_EQ(Src0, MIBAdd.getReg(0));
EXPECT_EQ(Src1, Copies[2]);
// Try to match MUL(ADD)
match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
match = mi_match(MIBMul.getReg(0), *MRI,
m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -81,7 +81,7 @@ TEST_F(GISelMITest, MatchBinaryOp) {
// Try to match MUL(Cst, Reg) on src of MUL(Reg, Cst) to validate
// commutativity.
int64_t Cst;
match = mi_match(MIBMul2->getOperand(0).getReg(), *MRI,
match = mi_match(MIBMul2.getReg(0), *MRI,
m_GMul(m_ICst(Cst), m_Reg(Src0)));
EXPECT_TRUE(match);
EXPECT_EQ(Cst, 42);
@ -89,14 +89,14 @@ TEST_F(GISelMITest, MatchBinaryOp) {
// Make sure commutative doesn't work with something like SUB.
auto MIBSub = B.buildSub(s64, Copies[0], B.buildConstant(s64, 42));
match = mi_match(MIBSub->getOperand(0).getReg(), *MRI,
match = mi_match(MIBSub.getReg(0), *MRI,
m_GSub(m_ICst(Cst), m_Reg(Src0)));
EXPECT_FALSE(match);
auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64},
{Copies[0], B.buildConstant(s64, 42)});
// Match and test commutativity for FMUL.
match = mi_match(MIBFMul->getOperand(0).getReg(), *MRI,
match = mi_match(MIBFMul.getReg(0), *MRI,
m_GFMul(m_ICst(Cst), m_Reg(Src0)));
EXPECT_TRUE(match);
EXPECT_EQ(Cst, 42);
@ -105,7 +105,7 @@ TEST_F(GISelMITest, MatchBinaryOp) {
// FSUB
auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64},
{Copies[0], B.buildConstant(s64, 42)});
match = mi_match(MIBFSub->getOperand(0).getReg(), *MRI,
match = mi_match(MIBFSub.getReg(0), *MRI,
m_GFSub(m_Reg(Src0), m_Reg()));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -113,7 +113,7 @@ TEST_F(GISelMITest, MatchBinaryOp) {
// Build AND %0, %1
auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]);
// Try to match AND.
match = mi_match(MIBAnd->getOperand(0).getReg(), *MRI,
match = mi_match(MIBAnd.getReg(0), *MRI,
m_GAnd(m_Reg(Src0), m_Reg(Src1)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -122,7 +122,7 @@ TEST_F(GISelMITest, MatchBinaryOp) {
// Build OR %0, %1
auto MIBOr = B.buildOr(s64, Copies[0], Copies[1]);
// Try to match OR.
match = mi_match(MIBOr->getOperand(0).getReg(), *MRI,
match = mi_match(MIBOr.getReg(0), *MRI,
m_GOr(m_Reg(Src0), m_Reg(Src1)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -141,23 +141,23 @@ TEST_F(GISelMITest, MatchFPUnaryOp) {
// Match G_FABS.
auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32});
bool match =
mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg()));
mi_match(MIBFabs.getReg(0), *MRI, m_GFabs(m_Reg()));
EXPECT_TRUE(match);
Register Src;
auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});
match = mi_match(MIBFNeg->getOperand(0).getReg(), *MRI, m_GFNeg(m_Reg(Src)));
match = mi_match(MIBFNeg.getReg(0), *MRI, m_GFNeg(m_Reg(Src)));
EXPECT_TRUE(match);
EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
EXPECT_EQ(Src, Copy0s32.getReg(0));
match = mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg(Src)));
match = mi_match(MIBFabs.getReg(0), *MRI, m_GFabs(m_Reg(Src)));
EXPECT_TRUE(match);
EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
EXPECT_EQ(Src, Copy0s32.getReg(0));
// Build and match FConstant.
auto MIBFCst = B.buildFConstant(s32, .5);
const ConstantFP *TmpFP{};
match = mi_match(MIBFCst->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP));
match = mi_match(MIBFCst.getReg(0), *MRI, m_GFCst(TmpFP));
EXPECT_TRUE(match);
EXPECT_TRUE(TmpFP);
APFloat APF((float).5);
@ -168,7 +168,7 @@ TEST_F(GISelMITest, MatchFPUnaryOp) {
LLT s64 = LLT::scalar(64);
auto MIBFCst64 = B.buildFConstant(s64, .5);
const ConstantFP *TmpFP64{};
match = mi_match(MIBFCst64->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP64));
match = mi_match(MIBFCst64.getReg(0), *MRI, m_GFCst(TmpFP64));
EXPECT_TRUE(match);
EXPECT_TRUE(TmpFP64);
APFloat APF64(.5);
@ -180,7 +180,7 @@ TEST_F(GISelMITest, MatchFPUnaryOp) {
LLT s16 = LLT::scalar(16);
auto MIBFCst16 = B.buildFConstant(s16, .5);
const ConstantFP *TmpFP16{};
match = mi_match(MIBFCst16->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP16));
match = mi_match(MIBFCst16.getReg(0), *MRI, m_GFCst(TmpFP16));
EXPECT_TRUE(match);
EXPECT_TRUE(TmpFP16);
bool Ignored;
@ -205,34 +205,34 @@ TEST_F(GISelMITest, MatchExtendsTrunc) {
auto MIBSExt = B.buildSExt(s64, MIBTrunc);
Register Src0;
bool match =
mi_match(MIBTrunc->getOperand(0).getReg(), *MRI, m_GTrunc(m_Reg(Src0)));
mi_match(MIBTrunc.getReg(0), *MRI, m_GTrunc(m_Reg(Src0)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
match =
mi_match(MIBAExt->getOperand(0).getReg(), *MRI, m_GAnyExt(m_Reg(Src0)));
mi_match(MIBAExt.getReg(0), *MRI, m_GAnyExt(m_Reg(Src0)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
EXPECT_EQ(Src0, MIBTrunc.getReg(0));
match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI, m_GSExt(m_Reg(Src0)));
match = mi_match(MIBSExt.getReg(0), *MRI, m_GSExt(m_Reg(Src0)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
EXPECT_EQ(Src0, MIBTrunc.getReg(0));
match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI, m_GZExt(m_Reg(Src0)));
match = mi_match(MIBZExt.getReg(0), *MRI, m_GZExt(m_Reg(Src0)));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
EXPECT_EQ(Src0, MIBTrunc.getReg(0));
// Match ext(trunc src)
match = mi_match(MIBAExt->getOperand(0).getReg(), *MRI,
match = mi_match(MIBAExt.getReg(0), *MRI,
m_GAnyExt(m_GTrunc(m_Reg(Src0))));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI,
match = mi_match(MIBSExt.getReg(0), *MRI,
m_GSExt(m_GTrunc(m_Reg(Src0))));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI,
match = mi_match(MIBZExt.getReg(0), *MRI,
m_GZExt(m_GTrunc(m_Reg(Src0))));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -247,20 +247,20 @@ TEST_F(GISelMITest, MatchSpecificType) {
LLT s64 = LLT::scalar(64);
LLT s32 = LLT::scalar(32);
auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
EXPECT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
EXPECT_FALSE(mi_match(MIBAdd.getReg(0), *MRI,
m_GAdd(m_SpecificType(s32), m_Reg())));
EXPECT_TRUE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
EXPECT_TRUE(mi_match(MIBAdd.getReg(0), *MRI,
m_GAdd(m_SpecificType(s64), m_Reg())));
// Try to match the destination type of a bitcast.
LLT v2s32 = LLT::vector(2, 32);
auto MIBCast = B.buildCast(v2s32, Copies[0]);
EXPECT_TRUE(
mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_GBitcast(m_Reg())));
mi_match(MIBCast.getReg(0), *MRI, m_GBitcast(m_Reg())));
EXPECT_TRUE(
mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_SpecificType(v2s32)));
mi_match(MIBCast.getReg(0), *MRI, m_SpecificType(v2s32)));
EXPECT_TRUE(
mi_match(MIBCast->getOperand(1).getReg(), *MRI, m_SpecificType(s64)));
mi_match(MIBCast.getReg(1), *MRI, m_SpecificType(s64)));
// Build a PTRToInt and INTTOPTR and match and test them.
LLT PtrTy = LLT::pointer(0, 64);
@ -269,7 +269,7 @@ TEST_F(GISelMITest, MatchSpecificType) {
Register Src0;
// match the ptrtoint(inttoptr reg)
bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), *MRI,
bool match = mi_match(MIBPtrToInt.getReg(0), *MRI,
m_GPtrToInt(m_GIntToPtr(m_Reg(Src0))));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -285,18 +285,18 @@ TEST_F(GISelMITest, MatchCombinators) {
auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
Register Src0, Src1;
bool match =
mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
mi_match(MIBAdd.getReg(0), *MRI,
m_all_of(m_SpecificType(s64), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
EXPECT_EQ(Src1, Copies[1]);
// Check for s32 (which should fail).
match =
mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
mi_match(MIBAdd.getReg(0), *MRI,
m_all_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
EXPECT_FALSE(match);
match =
mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
mi_match(MIBAdd.getReg(0), *MRI,
m_any_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
EXPECT_TRUE(match);
EXPECT_EQ(Src0, Copies[0]);
@ -304,7 +304,7 @@ TEST_F(GISelMITest, MatchCombinators) {
// Match a case where none of the predicates hold true.
match = mi_match(
MIBAdd->getOperand(0).getReg(), *MRI,
MIBAdd.getReg(0), *MRI,
m_any_of(m_SpecificType(LLT::scalar(16)), m_GSub(m_Reg(), m_Reg())));
EXPECT_FALSE(match);
}