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[AMDGPU][llvm-mc] Support for 32-bit inline literals
Patch by: Artem Tamazov Summary: Note: Support for 64-bit inline literals TBD Added: Support of abs/neg modifiers for literals (incomplete; parsing TBD). Added: Some TODO comments. Reworked/clarity: rename isInlineImm() to isInlinableImm() Reworked/robustness: disallow BitsToFloat() with undefined value in isInlinableImm() Reworked/reuse: isSSrc32/64(), isVSrc32/64() Tests added. Reviewers: tstellarAMD, arsenm Subscribers: vpykhtin, nhaustov, SamWot, arsenm Projects: #llvm-amdgpu-spb Differential Revision: http://reviews.llvm.org/D17204 llvm-svn: 261559
This commit is contained in:
Tom Stellard
parent
5186536b5b
commit
d6c924b960
@ -79,6 +79,7 @@ public:
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bool IsFPImm;
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ImmTy Type;
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int64_t Val;
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int Modifiers;
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};
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struct RegOp {
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@ -109,15 +110,20 @@ public:
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}
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void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
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if (isReg())
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if (isRegKind())
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addRegOperands(Inst, N);
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else
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addImmOperands(Inst, N);
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}
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void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createImm(Reg.Modifiers));
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addRegOperands(Inst, N);
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void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {
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if (isRegKind()) {
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Inst.addOperand(MCOperand::createImm(Reg.Modifiers));
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addRegOperands(Inst, N);
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} else {
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Inst.addOperand(MCOperand::createImm(Imm.Modifiers));
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addImmOperands(Inst, N);
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}
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}
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void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
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@ -143,12 +149,18 @@ public:
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return Kind == Immediate;
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}
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bool isInlineImm() const {
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float F = BitsToFloat(Imm.Val);
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// TODO: Add 0.5pi for VI
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return isImm() && ((Imm.Val <= 64 && Imm.Val >= -16) ||
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bool isInlinableImm() const {
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if (!isImm() || Imm.Type != AMDGPUOperand::ImmTyNone /* Only plain
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immediates are inlinable (e.g. "clamp" attribute is not) */ )
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return false;
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// TODO: We should avoid using host float here. It would be better to
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// check the float bit values which is what a few other places do.
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// We've had bot failures before due to weird NaN support on mips hosts.
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const float F = BitsToFloat(Imm.Val);
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// TODO: Add 1/(2*pi) for VI
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return (Imm.Val <= 64 && Imm.Val >= -16) ||
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(F == 0.0 || F == 0.5 || F == -0.5 || F == 1.0 || F == -1.0 ||
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F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0));
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F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0);
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}
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bool isDSOffset0() const {
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@ -178,8 +190,8 @@ public:
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return Kind == Register && Reg.Modifiers == 0;
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}
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bool isRegWithInputMods() const {
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return Kind == Register;
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bool isRegOrImmWithInputMods() const {
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return Kind == Register || isInlinableImm();
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}
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bool isClamp() const {
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@ -195,13 +207,16 @@ public:
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}
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void setModifiers(unsigned Mods) {
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assert(isReg());
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Reg.Modifiers = Mods;
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assert(isReg() || (isImm() && Imm.Modifiers == 0));
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if (isReg())
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Reg.Modifiers = Mods;
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else
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Imm.Modifiers = Mods;
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}
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bool hasModifiers() const {
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assert(isRegKind());
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return Reg.Modifiers != 0;
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assert(isRegKind() || isImm());
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return isRegKind() ? Reg.Modifiers != 0 : Imm.Modifiers != 0;
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}
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unsigned getReg() const override {
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@ -217,36 +232,42 @@ public:
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}
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bool isSCSrc32() const {
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return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
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}
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bool isSSrc32() const {
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return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
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}
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bool isSSrc64() const {
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return isImm() || isInlineImm() ||
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(isReg() && isRegClass(AMDGPU::SReg_64RegClassID));
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return isInlinableImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
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}
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bool isSCSrc64() const {
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return (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)) || isInlineImm();
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return isInlinableImm() || (isReg() && isRegClass(AMDGPU::SReg_64RegClassID));
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}
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bool isSSrc32() const {
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return isImm() || isSCSrc32();
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}
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bool isSSrc64() const {
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// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
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// See isVSrc64().
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return isImm() || isSCSrc64();
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}
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bool isVCSrc32() const {
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return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
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return isInlinableImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
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}
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bool isVCSrc64() const {
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return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
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return isInlinableImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
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}
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bool isVSrc32() const {
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return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
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return isImm() || isVCSrc32();
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}
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bool isVSrc64() const {
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return isImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
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// TODO: Check if the 64-bit value (coming from assembly source) can be
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// narrowed to 32 bits (in the instruction stream). That require knowledge
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// of instruction type (unsigned/signed, floating or "untyped"/B64),
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// see [AMD GCN3 ISA 6.3.1].
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// TODO: How 64-bit values are formed from 32-bit literals in _B64 insns?
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return isImm() || isVCSrc64();
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}
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bool isMem() const override {
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@ -275,7 +296,10 @@ public:
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OS << "<register " << getReg() << " mods: " << Reg.Modifiers << '>';
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break;
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case Immediate:
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OS << getImm();
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if (Imm.Type != AMDGPUOperand::ImmTyNone)
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OS << getImm();
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else
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OS << '<' << getImm() << " mods: " << Imm.Modifiers << '>';
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break;
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case Token:
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OS << '\'' << getToken() << '\'';
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@ -293,6 +317,7 @@ public:
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Op->Imm.Val = Val;
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Op->Imm.IsFPImm = IsFPImm;
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Op->Imm.Type = Type;
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Op->Imm.Modifiers = 0;
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Op->StartLoc = Loc;
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Op->EndLoc = Loc;
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return Op;
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@ -1099,6 +1124,8 @@ static bool operandsHaveModifiers(const OperandVector &Operands) {
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const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
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if (Op.isRegKind() && Op.hasModifiers())
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return true;
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if (Op.isImm() && Op.hasModifiers())
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return true;
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if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod ||
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Op.getImmTy() == AMDGPUOperand::ImmTyClamp))
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return true;
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@ -1843,7 +1870,7 @@ AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) {
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// previous register operands have modifiers
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for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
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if (Op.isReg())
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if ((Op.isReg() || Op.isImm()) && !Op.hasModifiers())
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Op.setModifiers(0);
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}
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}
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@ -1892,14 +1919,12 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
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unsigned ClampIdx = 0, OModIdx = 0;
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for (unsigned E = Operands.size(); I != E; ++I) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
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if (Op.isRegWithInputMods()) {
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Op.addRegWithInputModsOperands(Inst, 2);
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if (Op.isRegOrImmWithInputMods()) {
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Op.addRegOrImmWithInputModsOperands(Inst, 2);
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} else if (Op.isClamp()) {
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ClampIdx = I;
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} else if (Op.isOMod()) {
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OModIdx = I;
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} else if (Op.isImm()) {
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Op.addImmOperands(Inst, 1);
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} else {
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assert(false);
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}
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@ -1073,7 +1073,7 @@ def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
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}
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def InputModsMatchClass : AsmOperandClass {
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let Name = "RegWithInputMods";
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let Name = "RegOrImmWithInputMods";
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}
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def InputModsNoDefault : Operand <i32> {
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@ -3,3 +3,6 @@
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v_add_f32_e64 v0, v1
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// CHECK: error: too few operands for instruction
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v_div_scale_f32 v24, vcc, v22, 1.1, v22
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// CHECK: error: invalid operand for instruction
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@ -289,3 +289,19 @@ v_div_scale_f32 v24, vcc, s[10:11], v22, v20
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v_div_scale_f32 v24, s[10:11], v22, v22, v20
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// SICI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xda,0xd2,0x16,0x2d,0x52,0x04]
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// VI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xe0,0xd1,0x16,0x2d,0x52,0x04]
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v_div_scale_f32 v24, vcc, v22, 1.0, v22
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// SICI: v_div_scale_f32 v24, vcc, v22, 1.0, v22 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0xe5,0x59,0x04]
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// VI: v_div_scale_f32 v24, vcc, v22, 1.0, v22 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0xe5,0x59,0x04]
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v_div_scale_f32 v24, vcc, v22, v22, -2.0
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// SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]
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// VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd6,0x03]
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v_div_scale_f32 v24, vcc, v22, v22, 0xc0000000
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// SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]
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// VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd6,0x03]
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v_mad_f32 v9, 0.5, v5, -v8
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// SICI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0x82,0xd2,0xf0,0x0a,0x22,0x84]
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// VI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0xc1,0xd1,0xf0,0x0a,0x22,0x84]
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