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[AMDGPU] gfx1010 tests. NFC.
Added tests which now pass after code commits. llvm-svn: 360300
This commit is contained in:
Stanislav Mekhanoshin
parent
2afe8534a5
commit
d6ccc6c648
@ -1,10 +1,11 @@
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=SICI,PREGFX10
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=VI,PREGFX10
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;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10
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;CHECK-LABEL: {{^}}buffer_load:
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
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;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
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;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
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;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
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;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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main_body:
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@ -17,6 +18,25 @@ main_body:
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_dlc:
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;PREGFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
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;PREGFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
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;PREGFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
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;GFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc{{$}}
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;GFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc{{$}}
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;GFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc{{$}}
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4)
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%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5)
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%data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs:
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
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;CHECK: s_waitcnt
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@ -74,7 +94,8 @@ main_body:
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}
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;CHECK-LABEL: {{^}}buffer_load_negative_offset:
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;CHECK: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
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;PREGFX10: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
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;GFX10: v_add_nc_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], -16, v0
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;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen
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define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
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main_body:
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@ -280,7 +301,7 @@ main_body:
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;CHECK-LABEL: {{^}}raw_buffer_load_ushort:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0
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;CHECK-NEXT: s_waitcnt vmcnt(0)
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @raw_buffer_load_ushort(<4 x i32> inreg %rsrc) {
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@ -294,7 +315,7 @@ main_body:
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;CHECK-LABEL: {{^}}raw_buffer_load_sbyte:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0
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;CHECK-NEXT: s_waitcnt vmcnt(0)
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
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@ -308,7 +329,7 @@ main_body:
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;CHECK-LABEL: {{^}}raw_buffer_load_sshort:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0
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;CHECK-NEXT: s_waitcnt vmcnt(0)
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
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@ -1,18 +1,23 @@
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=PREGFX10 %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=PREGFX10 %s
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;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=GFX10 %s
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; GCN-LABEL: {{^}}tbuffer_load:
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:3, 0 glc
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0 slc
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:3, 0 glc
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0 slc
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0 glc
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:63, 0 glc
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:22, 0 slc
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:22, 0 glc dlc
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; GCN: s_waitcnt
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define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @tbuffer_load(<4 x i32> inreg) {
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 78, i32 0)
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%vdata_glc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 63, i32 1)
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%vdata_slc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 22, i32 2)
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%vdata_f32 = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 22, i32 0)
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%vdata_f32 = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 22, i32 5)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
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%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
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@ -24,7 +29,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}tbuffer_load_immoffs:
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
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; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0 offset:42
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define amdgpu_vs <4 x float> @tbuffer_load_immoffs(<4 x i32> inreg) {
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 42, i32 0, i32 78, i32 0)
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@ -33,9 +39,12 @@ main_body:
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}
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; GCN-LABEL: {{^}}tbuffer_load_immoffs_large
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:2, 61 offset:4095
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:3, {{s[0-9]+}} offset:73
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, {{s[0-9]+}} offset:1
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:2, 61 offset:4095
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:3, {{s[0-9]+}} offset:73
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, {{s[0-9]+}} offset:1
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:47, 61 offset:4095
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:62, {{s[0-9]+}} offset:73
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; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:77, {{s[0-9]+}} offset:1
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; GCN: s_waitcnt
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define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_large(<4 x i32> inreg, i32 inreg %soffs) {
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%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 4095, i32 61, i32 47, i32 0)
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@ -51,7 +60,8 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
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}
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; GCN-LABEL: {{^}}tbuffer_load_ofs:
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen
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; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0 offen
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define amdgpu_vs <4 x float> @tbuffer_load_ofs(<4 x i32> inreg, i32 %voffs) {
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 %voffs, i32 0, i32 78, i32 0)
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@ -60,7 +70,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}tbuffer_load_ofs_imm:
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; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:52
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; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:52
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; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0 offen offset:52
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define amdgpu_vs <4 x float> @tbuffer_load_ofs_imm(<4 x i32> inreg, i32 %voffs) {
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main_body:
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%ofs = add i32 %voffs, 52
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@ -70,7 +81,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}buffer_load_xy:
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; GCN: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
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; PREGFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
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; GFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:77, 0
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define amdgpu_vs <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
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%vdata = call <2 x i32> @llvm.amdgcn.raw.tbuffer.load.v2i32(<4 x i32> %rsrc, i32 0, i32 0, i32 77, i32 0)
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%vdata.f = bitcast <2 x i32> %vdata to <2 x float>
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@ -78,7 +90,8 @@ define amdgpu_vs <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
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}
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; GCN-LABEL: {{^}}buffer_load_x:
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; GCN: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
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; PREGFX10: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
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; GFX10: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:77, 0
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define amdgpu_vs float @buffer_load_x(<4 x i32> inreg %rsrc) {
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%vdata = call i32 @llvm.amdgcn.raw.tbuffer.load.i32(<4 x i32> %rsrc, i32 0, i32 0, i32 77, i32 0)
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%vdata.f = bitcast i32 %vdata to float
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7
test/MC/AMDGPU/gfx9-vop2be-literal.s
Normal file
7
test/MC/AMDGPU/gfx9-vop2be-literal.s
Normal file
@ -0,0 +1,7 @@
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# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding < %s 2>&1 | FileCheck -check-prefix=GFX9-ERR %s
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v_addc_co_u32_e32 v3, vcc, 12345, v3, vcc
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// GFX9-ERR: error: invalid operand (violates constant bus restrictions)
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v_cndmask_b32 v0, 12345, v1, vcc
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// GFX9-ERR: error: invalid operand (violates constant bus restrictions)
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@ -69,3 +69,9 @@ s_waitcnt vmcnt(62) lgkmcnt(14)
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s_waitcnt vmcnt(62) expcnt(6) lgkmcnt(14)
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// GFX9: s_waitcnt vmcnt(62) expcnt(6) lgkmcnt(14) ; encoding: [0x6e,0xce,0x8c,0xbf]
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s_sendmsg 9
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// GCN: s_sendmsg sendmsg(MSG_GS_ALLOC_REQ) ; encoding: [0x09,0x00,0x90,0xbf]
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s_sendmsg sendmsg(MSG_GS_ALLOC_REQ)
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// GFX9: s_sendmsg sendmsg(MSG_GS_ALLOC_REQ) ; encoding: [0x09,0x00,0x90,0xbf]
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40
test/MC/AMDGPU/vcmpx-gfx10.s
Normal file
40
test/MC/AMDGPU/vcmpx-gfx10.s
Normal file
@ -0,0 +1,40 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
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// GFX10: v_cmpx_le_f32_e64 v1, v0 ; encoding: [0x00,0x00,0x13,0xd4,0x01,0x01,0x02,0x00]
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v_cmpx_le_f32_e64 v1, v0
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// GFX10: v_cmpx_le_f32_e64 -|v1|, v0 ; encoding: [0x00,0x01,0x13,0xd4,0x01,0x01,0x02,0x20]
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v_cmpx_le_f32_e64 -|v1|, v0
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// GFX10: v_cmpx_le_f32_e64 -|v1|, v0 ; encoding: [0x00,0x01,0x13,0xd4,0x01,0x01,0x02,0x20]
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v_cmpx_le_f32 -|v1|, v0
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// GFX10: v_cmpx_le_f32_e64 -|v1|, v0 clamp ; encoding: [0x00,0x81,0x13,0xd4,0x01,0x01,0x02,0x20]
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v_cmpx_le_f32 -|v1|, v0 clamp
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||||
|
||||
// GFX10: v_cmpx_le_f32_e32 v1, v0 ; encoding: [0x01,0x01,0x26,0x7c]
|
||||
v_cmpx_le_f32 v1, v0
|
||||
|
||||
// GFX10: v_cmpx_le_f32_e32 v1, v0 ; encoding: [0x01,0x01,0x26,0x7c]
|
||||
v_cmpx_le_f32_e32 v1, v0
|
||||
|
||||
// GFX10: v_cmpx_le_u32_e32 0, v0 ; encoding: [0x80,0x00,0xa6,0x7d]
|
||||
v_cmpx_le_u32 0, v0
|
||||
|
||||
// GFX10: v_cmpx_le_u32_e32 0, v0 ; encoding: [0x80,0x00,0xa6,0x7d]
|
||||
v_cmpx_le_u32_e32 0, v0
|
||||
|
||||
// GFX10: v_cmpx_le_u32_e64 0, v0 ; encoding: [0x00,0x00,0xd3,0xd4,0x80,0x00,0x02,0x00]
|
||||
v_cmpx_le_u32_e64 0, v0
|
||||
|
||||
// GFX10: v_cmpx_le_f16_sdwa v3, v4 src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0xb6,0x7d,0x03,0x00,0x05,0x06]
|
||||
v_cmpx_le_f16_sdwa v3, v4 src0_sel:WORD_1 src1_sel:DWORD
|
||||
|
||||
// GFX10: v_cmpx_le_f16_sdwa v3, v4 src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0xb6,0x7d,0x03,0x00,0x05,0x06]
|
||||
v_cmpx_le_f16 v3, v4 src0_sel:WORD_1 src1_sel:DWORD
|
||||
|
||||
// GFX10: v_cmpx_class_f32_e64 v0, 1 ; encoding: [0x00,0x00,0x98,0xd4,0x00,0x03,0x01,0x00]
|
||||
v_cmpx_class_f32 v0, 1
|
||||
|
||||
// GFX10: v_cmpx_class_f32_e64 v0, 1 ; encoding: [0x00,0x00,0x98,0xd4,0x00,0x03,0x01,0x00]
|
||||
v_cmpx_class_f32_e64 v0, 1
|
||||
@ -1,30 +1,31 @@
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1001 -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
|
||||
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s 2>&1 | FileCheck -check-prefix=XNACKERR %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s | FileCheck -check-prefix=XNACK %s
|
||||
|
||||
s_mov_b64 xnack_mask, -1
|
||||
// NOSICIVI: error: not a valid operand.
|
||||
// NOSICIVI10: error: not a valid operand.
|
||||
// XNACK: s_mov_b64 xnack_mask, -1 ; encoding: [0xc1,0x01,0xe8,0xbe]
|
||||
|
||||
s_mov_b32 xnack_mask_lo, -1
|
||||
// NOSICIVI: error: not a valid operand.
|
||||
// NOSICIVI10: error: not a valid operand.
|
||||
// XNACK: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
|
||||
|
||||
s_mov_b32 xnack_mask_hi, -1
|
||||
// NOSICIVI: error: not a valid operand.
|
||||
// NOSICIVI10: error: not a valid operand.
|
||||
// XNACK: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
|
||||
|
||||
s_mov_b32 xnack_mask, -1
|
||||
// NOSICIVI: error: not a valid operand.
|
||||
// NOSICIVI10: error: not a valid operand.
|
||||
// XNACKERR: error: invalid operand for instruction
|
||||
|
||||
s_mov_b64 xnack_mask_lo, -1
|
||||
// NOSICIVI: error: not a valid operand.
|
||||
// NOSICIVI10: error: not a valid operand.
|
||||
// XNACKERR: error: invalid operand for instruction
|
||||
|
||||
s_mov_b64 xnack_mask_hi, -1
|
||||
// NOSICIVI: error: not a valid operand.
|
||||
// NOSICIVI10: error: not a valid operand.
|
||||
// XNACKERR: error: invalid operand for instruction
|
||||
|
||||
36
test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt
Normal file
36
test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt
Normal file
@ -0,0 +1,36 @@
|
||||
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
|
||||
|
||||
#===------------------------------------------------------------------------===#
|
||||
# Regular v_cmpx encoding
|
||||
#===------------------------------------------------------------------------===#
|
||||
|
||||
# GFX10: v_cmpx_eq_f16_e64 s1, v2
|
||||
0x00,0x00,0xda,0xd4,0x01,0x04,0x02,0x00
|
||||
|
||||
# GFX10: v_cmpx_class_f32_e64 v0, 1
|
||||
0x00,0x00,0x98,0xd4,0x00,0x03,0x01,0x00
|
||||
|
||||
# GFX10: v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
|
||||
0xf9,0x04,0xb4,0x7d,0x01,0x00,0x16,0x06
|
||||
|
||||
# GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
|
||||
0xf9,0x02,0x31,0x7d,0x00,0x00,0x05,0x86
|
||||
|
||||
#===------------------------------------------------------------------------===#
|
||||
# v_cmpx with arbitrary DST value should also be decodable
|
||||
#===------------------------------------------------------------------------===#
|
||||
|
||||
# GFX10: v_cmpx_eq_f16_e64 s1, v2
|
||||
0x7e,0x00,0xda,0xd4,0x01,0x04,0x02,0x00
|
||||
|
||||
# GFX10: v_cmpx_class_f32_e64 v0, 1
|
||||
0x7e,0x00,0x98,0xd4,0x00,0x03,0x01,0x00
|
||||
|
||||
# GFX10: v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
|
||||
0xf9,0x04,0xb4,0x7d,0x01,0x7e,0x16,0x06
|
||||
|
||||
# GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
|
||||
0xf9,0x02,0x31,0x7d,0x00,0x7e,0x05,0x86
|
||||
|
||||
# GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
|
||||
0xf9,0x02,0x31,0x7d,0x00,0x7d,0x05,0x86
|
||||
Loading…
Reference in New Issue
Block a user