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[GlobalISel] Insert translated switch icmp blocks after switch parent.
Now that we preserve the IR layout, we would end up with all the newly synthesized switch comparison blocks at the end of the function. Instead, use a hopefully more reasonable layout, with the comparison blocks immediately following the switch comparison blocks. llvm-svn: 297869
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@ -258,7 +258,8 @@ bool IRTranslator::translateSwitch(const User &U,
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MachineBasicBlock *FalseMBB =
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MachineBasicBlock *FalseMBB =
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MF->CreateMachineBasicBlock(SwInst.getParent());
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MF->CreateMachineBasicBlock(SwInst.getParent());
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MF->push_back(FalseMBB);
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// Insert the comparison blocks one after the other.
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MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
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MIRBuilder.buildBr(*FalseMBB);
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MIRBuilder.buildBr(*FalseMBB);
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CurMBB.addSuccessor(FalseMBB);
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CurMBB.addSuccessor(FalseMBB);
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@ -117,7 +117,17 @@ false:
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; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
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; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
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; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
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; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
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;
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;
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; CHECK: [[BB_DEFAULT:bb.[0-9]+.default]]:
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; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
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; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
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; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
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; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
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; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
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;
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; CHECK: [[BB_NOTCASE200_CHECKNEXT]]:
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; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000)
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; CHECK: G_BR %[[BB_DEFAULT]]
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;
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; CHECK: [[BB_DEFAULT]]:
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; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
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; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
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; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]]
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; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]]
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; CHECK: G_BR %[[BB_RET]]
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; CHECK: G_BR %[[BB_RET]]
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@ -127,7 +137,7 @@ false:
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; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]]
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; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]]
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; CHECK: G_BR %[[BB_RET]]
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; CHECK: G_BR %[[BB_RET]]
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;
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;
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; CHECK: [[BB_CASE200:bb.[0-9]+.case200]]:
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; CHECK: [[BB_CASE200]]:
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; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
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; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
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; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]]
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; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]]
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; CHECK: G_BR %[[BB_RET]]
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; CHECK: G_BR %[[BB_RET]]
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@ -137,15 +147,6 @@ false:
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; CHECK: %w0 = COPY %[[regret]](s32)
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; CHECK: %w0 = COPY %[[regret]](s32)
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; CHECK: RET_ReallyLR implicit %w0
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; CHECK: RET_ReallyLR implicit %w0
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;
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;
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; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
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; CHECK-NEXT: successors: %[[BB_CASE200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
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; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
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; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
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; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
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;
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; CHECK: [[BB_NOTCASE200_CHECKNEXT]]:
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; CHECK-NEXT: successors: %[[BB_DEFAULT]](0x80000000)
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; CHECK: G_BR %[[BB_DEFAULT]]
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define i32 @switch(i32 %argc) {
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define i32 @switch(i32 %argc) {
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entry:
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entry:
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switch i32 %argc, label %default [
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switch i32 %argc, label %default [
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@ -174,12 +175,17 @@ return:
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; %entry block is no longer a predecessor for the phi instruction. We need to
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; %entry block is no longer a predecessor for the phi instruction. We need to
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; use the correct lowered MachineBasicBlock instead.
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; use the correct lowered MachineBasicBlock instead.
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; CHECK-LABEL: name: test_cfg_remap
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; CHECK-LABEL: name: test_cfg_remap
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; CHECK: [[PHI_BLOCK:bb.[0-9]+.phi.block]]:
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; CHECK: {{bb.[0-9]+.entry}}:
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; CHECK-NEXT: PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32),
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; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000)
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; CHECK: [[NOTCASE1_BLOCK]]:
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; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000)
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; CHECK: [[NOTCASE57_BLOCK]]:
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; CHECK: [[NOTCASE57_BLOCK]]:
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; CHECK-NEXT: successors: %[[PHI_BLOCK]]
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; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000)
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; CHECK: G_BR %[[PHI_BLOCK]]
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; CHECK: G_BR %[[PHI_BLOCK]]
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;
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; CHECK: [[PHI_BLOCK]]:
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; CHECK-NEXT: PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32),
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;
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define i32 @test_cfg_remap(i32 %in) {
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define i32 @test_cfg_remap(i32 %in) {
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entry:
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entry:
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switch i32 %in, label %phi.block [i32 1, label %next
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switch i32 %in, label %phi.block [i32 1, label %next
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