RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

Add a target legalize hook for SplitVectorOperand (again)

Browse Source 
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

Attempt to fix the buildbots by making the X86 test I just added platform independent

llvm-svn: 187202
This commit is contained in:
Justin Holewinski 2013-07-26 13:28:29 +00:00
parent c3d143707e
commit d714d8ebe8
4 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -1031,6 +1031,10 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
dbgs() << "\n");
SDValue Res = SDValue();
// See if the target wants to custom split this node.
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
return false;
if (Res.getNode() == 0) {
switch (N->getOpcode()) {
default:

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -996,7 +996,7 @@ void X86TargetLowering::resetOperationActions() {
setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
}
if (Subtarget->hasSSE41()) {
if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
setOperationAction(ISD::FCEIL, MVT::f32, Legal);
setOperationAction(ISD::FTRUNC, MVT::f32, Legal);

30
test/CodeGen/NVPTX/vector-stores.ll Normal file
View File

@ -0,0 +1,30 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; CHECK: .visible .func foo1
; CHECK: st.v2.f32
define void @foo1(<2 x float> %val, <2 x float>* %ptr) {
store <2 x float> %val, <2 x float>* %ptr
ret void
}
; CHECK: .visible .func foo2
; CHECK: st.v4.f32
define void @foo2(<4 x float> %val, <4 x float>* %ptr) {
store <4 x float> %val, <4 x float>* %ptr
ret void
}
; CHECK: .visible .func foo3
; CHECK: st.v2.u32
define void @foo3(<2 x i32> %val, <2 x i32>* %ptr) {
store <2 x i32> %val, <2 x i32>* %ptr
ret void
}
; CHECK: .visible .func foo4
; CHECK: st.v4.u32
define void @foo4(<4 x i32> %val, <4 x i32>* %ptr) {
store <4 x i32> %val, <4 x i32>* %ptr
ret void
}

13
test/CodeGen/X86/floor-soft-float.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
target triple = "x86_64-unknown-linux-gnu"
declare float @llvm.floor.f32(float)
; CHECK-SOFT-FLOAT: callq floorf
; CHECK-HARD-FLOAT: roundss $1, %xmm0, %xmm0
define float @myfloor(float %a) {
%val = tail call float @llvm.floor.f32(float %a)
ret float %val
}