From d72698331eabc7a665ff53c32c4a938043fdc252 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Mon, 20 May 2013 15:02:24 +0000
Subject: [PATCH] R600/SI: Add pattern for rotr
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
---
 lib/Target/R600/SIInstructions.td |  2 ++
 test/CodeGen/R600/rotr.ll         | 28 +++++++++++++++++++---------
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index f557922c2c5..7c725ccec48 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -964,6 +964,8 @@ def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>;
 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>;
 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
+def : ROTRPattern <V_ALIGNBIT_B32>;
+
 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll
index 75232fee71a..8bb5eaec820 100644
--- a/test/CodeGen/R600/rotr.ll
+++ b/test/CodeGen/R600/rotr.ll
@@ -1,8 +1,13 @@
-; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=redwood -o - 2>&1 | FileCheck %s
+; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=redwood -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s
+; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=SI -o - 2>&1 | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: rotr
-; CHECK: @rotr
-; CHECK: BIT_ALIGN_INT
+; R600-CHECK: rotr
+; R600-CHECK: @rotr
+; R600-CHECK: BIT_ALIGN_INT
+
+; SI-CHECK: rotr
+; SI-CHECK: @rotr
+; SI-CHECK: V_ALIGNBIT_B32
 define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) {
 entry:
   %0 = sub i32 32, %y
@@ -13,11 +18,16 @@ entry:
   ret void
 }
 
-; CHECK: rotr
-; CHECK: @rotl
-; CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
-; CHECK-NEXT: 32
-; CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}}
+; R600-CHECK: rotr
+; R600-CHECK: @rotl
+; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
+; R600-CHECK-NEXT: 32
+; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}}
+
+; SI-CHECK: rotr
+; SI-CHECK: @rotl
+; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}}
+; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}, [[DST]]
 define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) {
 entry:
   %0 = shl i32 %x, %y