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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Split HVX vector pair loads/stores, expand unaligned loads
llvm-svn: 325169
This commit is contained in:
Krzysztof Parzyszek
parent
f687ed1ec6
commit
d760dbf10e
@ -1727,6 +1727,7 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
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case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
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case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
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case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
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case HexagonISD::OP_END: break;
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}
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return nullptr;
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@ -1821,6 +1822,16 @@ HexagonTargetLowering::getPreferredVectorAction(EVT VT) const {
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return TargetLoweringBase::TypeSplitVector;
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}
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std::pair<SDValue, int>
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HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
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if (Addr.getOpcode() == ISD::ADD) {
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SDValue Op1 = Addr.getOperand(1);
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if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
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return { Addr.getOperand(0), CN->getSExtValue() };
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}
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return { Addr, 0 };
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}
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// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
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// to select data from, V3 is the permutation.
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SDValue
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@ -79,6 +79,8 @@ namespace HexagonISD {
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VZERO,
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TYPECAST, // No-op that's used to convert between different legal
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// types in a register.
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VALIGNADDR, // Align vector address: Op & -HwLen, except when it is
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// an address in a vector load, then it's a no-op.
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OP_END
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};
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@ -299,6 +301,7 @@ namespace HexagonISD {
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private:
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void initializeHVXLowering();
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std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
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bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
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SelectionDAG &DAG,
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@ -415,8 +418,10 @@ namespace HexagonISD {
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SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
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SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
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SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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@ -10,9 +10,14 @@
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#include "HexagonISelLowering.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool> ExpandUnalignedLoads("hvx-expand-unaligned-loads",
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cl::Hidden, cl::init(true),
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cl::desc("Expand unaligned HVX loads into a pair of aligned loads"));
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static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
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static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
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static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
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@ -83,6 +88,7 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
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}
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setOperationAction(ISD::LOAD, T, Custom);
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setOperationAction(ISD::MUL, T, Custom);
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setOperationAction(ISD::MULHS, T, Custom);
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setOperationAction(ISD::MULHU, T, Custom);
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@ -151,6 +157,9 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
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setOperationAction(ISD::LOAD, T, Custom);
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setOperationAction(ISD::STORE, T, Custom);
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setOperationAction(ISD::ADD, T, Legal);
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setOperationAction(ISD::SUB, T, Legal);
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setOperationAction(ISD::MUL, T, Custom);
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@ -1286,6 +1295,59 @@ HexagonTargetLowering::LowerHvxShift(SDValue Op, SelectionDAG &DAG) const {
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return Op;
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}
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SDValue
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HexagonTargetLowering::LowerHvxUnalignedLoad(SDValue Op, SelectionDAG &DAG)
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const {
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LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
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unsigned HaveAlign = LN->getAlignment();
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MVT VecTy = ty(Op);
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Type *Ty = EVT(VecTy).getTypeForEVT(*DAG.getContext());
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const DataLayout &DL = DAG.getDataLayout();
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unsigned NeedAlign = DL.getABITypeAlignment(Ty);
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if (HaveAlign >= NeedAlign || !ExpandUnalignedLoads)
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return Op;
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unsigned HwLen = Subtarget.getVectorLength();
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SDValue Base = LN->getBasePtr();
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SDValue Chain = LN->getChain();
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auto BO = getBaseAndOffset(Base);
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unsigned BaseOpc = BO.first.getOpcode();
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if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % HwLen == 0)
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return Op;
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const SDLoc &dl(Op);
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if (BO.second % HwLen != 0) {
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BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
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DAG.getConstant(BO.second % HwLen, dl, MVT::i32));
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BO.second -= BO.second % HwLen;
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}
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SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
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? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first)
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: BO.first;
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SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
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SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+HwLen, dl);
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MachineMemOperand *WideMMO = nullptr;
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if (MachineMemOperand *MMO = LN->getMemOperand()) {
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MachineFunction &MF = DAG.getMachineFunction();
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WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
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2*HwLen, HwLen, MMO->getAAInfo(), MMO->getRanges(),
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MMO->getSyncScopeID(), MMO->getOrdering(),
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MMO->getFailureOrdering());
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}
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SDValue Load0 = DAG.getLoad(VecTy, dl, Chain, Base0, WideMMO);
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SDValue Load1 = DAG.getLoad(VecTy, dl, Chain, Base1, WideMMO);
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SDValue Aligned = getInstr(Hexagon::V6_valignb, dl, VecTy,
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{Load1, Load0, BaseNoOff.getOperand(0)}, DAG);
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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Load0.getValue(1), Load1.getValue(1));
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SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
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return M;
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}
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SDValue
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HexagonTargetLowering::SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const {
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assert(!Op.isMachineOpcode());
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@ -1319,6 +1381,49 @@ HexagonTargetLowering::SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const {
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return S;
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}
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SDValue
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HexagonTargetLowering::SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const {
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LSBaseSDNode *BN = cast<LSBaseSDNode>(Op.getNode());
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assert(BN->isUnindexed());
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MVT MemTy = BN->getMemoryVT().getSimpleVT();
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if (!isHvxPairTy(MemTy))
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return Op;
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const SDLoc &dl(Op);
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unsigned HwLen = Subtarget.getVectorLength();
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MVT SingleTy = typeSplit(MemTy).first;
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SDValue Chain = BN->getChain();
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SDValue Base0 = BN->getBasePtr();
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SDValue Base1 = DAG.getMemBasePlusOffset(Base0, HwLen, dl);
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MachineMemOperand *MOp0 = nullptr, *MOp1 = nullptr;
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if (MachineMemOperand *MMO = BN->getMemOperand()) {
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MachineFunction &MF = DAG.getMachineFunction();
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MOp0 = MF.getMachineMemOperand(MMO, 0, HwLen);
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MOp1 = MF.getMachineMemOperand(MMO, HwLen, HwLen);
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}
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unsigned MemOpc = BN->getOpcode();
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SDValue NewOp;
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if (MemOpc == ISD::LOAD) {
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SDValue Load0 = DAG.getLoad(SingleTy, dl, Chain, Base0, MOp0);
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SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1);
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NewOp = DAG.getMergeValues(
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{ DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1),
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DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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Load0.getValue(1), Load1.getValue(1)) }, dl);
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} else {
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assert(MemOpc == ISD::STORE);
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VectorPair Vals = opSplit(cast<StoreSDNode>(Op)->getValue(), dl, DAG);
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SDValue Store0 = DAG.getStore(Chain, dl, Vals.first, Base0, MOp0);
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SDValue Store1 = DAG.getStore(Chain, dl, Vals.second, Base1, MOp1);
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NewOp = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store0, Store1);
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}
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return NewOp;
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}
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SDValue
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HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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unsigned Opc = Op.getOpcode();
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@ -1331,6 +1436,9 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Opc) {
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default:
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break;
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case ISD::LOAD:
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case ISD::STORE:
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return SplitHvxMemOp(Op, DAG);
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case ISD::MUL:
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case ISD::MULHS:
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case ISD::MULHU:
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@ -1350,25 +1458,26 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Opc) {
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default:
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break;
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case ISD::BUILD_VECTOR: return LowerHvxBuildVector(Op, DAG);
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case ISD::CONCAT_VECTORS: return LowerHvxConcatVectors(Op, DAG);
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case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG);
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case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG);
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case ISD::BUILD_VECTOR: return LowerHvxBuildVector(Op, DAG);
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case ISD::CONCAT_VECTORS: return LowerHvxConcatVectors(Op, DAG);
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case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG);
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case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG);
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case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
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case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG);
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case ISD::LOAD: return LowerHvxUnalignedLoad(Op, DAG);
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case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
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case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG);
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case ISD::SRA:
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case ISD::SHL:
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case ISD::SRL: return LowerHvxShift(Op, DAG);
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case ISD::MUL: return LowerHvxMul(Op, DAG);
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case ISD::SRL: return LowerHvxShift(Op, DAG);
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case ISD::MUL: return LowerHvxMul(Op, DAG);
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case ISD::MULHS:
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case ISD::MULHU: return LowerHvxMulh(Op, DAG);
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case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG);
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case ISD::MULHU: return LowerHvxMulh(Op, DAG);
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case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG);
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case ISD::SETCC:
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case ISD::INTRINSIC_VOID: return Op;
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case ISD::INTRINSIC_VOID: return Op;
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}
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#ifndef NDEBUG
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Op.dumpr(&DAG);
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@ -109,16 +109,6 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
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return isOrEquivalentToAdd(N);
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}]>;
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def IsVecOff : PatLeaf<(i32 imm), [{
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int32_t V = N->getSExtValue();
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int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
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assert(isPowerOf2_32(VecSize));
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if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
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return false;
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int32_t L = Log2_32(VecSize);
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return isInt<4>(V >> L);
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}]>;
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def IsPow2_32: PatLeaf<(i32 imm), [{
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uint32_t V = N->getZExtValue();
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return isPowerOf2_32(V);
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@ -249,23 +239,6 @@ def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
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(PS_fi (i32 AddrFI:$Rs), imm:$off)>;
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def alignedload: PatFrag<(ops node:$a), (load $a), [{
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return isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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def unalignedload: PatFrag<(ops node:$a), (load $a), [{
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return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
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return isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
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return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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// Converters from unary/binary SDNode to PatFrag.
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class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>;
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class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>;
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@ -16,6 +16,12 @@ def HwLen2: SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
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}]>;
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def NHwLen: SDNodeXForm<imm, [{
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const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
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return CurDAG->getTargetConstant(-int(ST.getVectorLength()), SDLoc(N),
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MVT::i32);
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}]>;
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def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>;
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def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
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@ -32,10 +38,12 @@ def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),
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def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
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def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
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def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
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def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;
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def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
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def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
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def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
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def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;
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def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
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def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
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def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>;
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def vzero: PatFrag<(ops), (HexagonVZERO)>;
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def qtrue: PatFrag<(ops), (HexagonQTRUE)>;
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def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
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@ -43,6 +51,7 @@ def qcat: PatFrag<(ops node:$Qs, node:$Qt),
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(HexagonQCAT node:$Qs, node:$Qt)>;
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def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
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def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>;
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def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;
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def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;
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@ -62,41 +71,75 @@ def SplatH: SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
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}]>;
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def IsVecOff : PatLeaf<(i32 imm), [{
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int32_t V = N->getSExtValue();
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int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
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assert(isPowerOf2_32(VecSize));
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if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
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return false;
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int32_t L = Log2_32(VecSize);
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return isInt<4>(V >> L);
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}]>;
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def alignedload: PatFrag<(ops node:$a), (load $a), [{
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return isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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def unalignedload: PatFrag<(ops node:$a), (load $a), [{
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return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
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return isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
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return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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// HVX loads
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multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType VT,
|
||||
multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
|
||||
PatFrag ImmPred> {
|
||||
def: Pat<(VT (Load I32:$Rt)), (MI I32:$Rt, 0)>;
|
||||
def: Pat<(VT (Load (add I32:$Rt, ImmPred:$s))), (MI I32:$Rt, imm:$s)>;
|
||||
def: Pat<(ResType (Load I32:$Rt)),
|
||||
(MI I32:$Rt, 0)>;
|
||||
def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
|
||||
(MI I32:$Rt, imm:$s)>;
|
||||
// The HVX selection code for shuffles can generate vector constants.
|
||||
// Calling "Select" on the resulting loads from CP fails without these
|
||||
// patterns.
|
||||
def: Pat<(VT (Load (HexagonCP tconstpool:$A))), (MI (A2_tfrsi imm:$A), 0)>;
|
||||
def: Pat<(VT (Load (HexagonAtPcrel tconstpool:$A))),
|
||||
def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
|
||||
(MI (A2_tfrsi imm:$A), 0)>;
|
||||
def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
|
||||
(MI (C4_addipc imm:$A), 0)>;
|
||||
}
|
||||
|
||||
let Predicates = [UseHVX] in {
|
||||
multiclass HvxLdVs_pat<InstHexagon MI, PatFrag Load> {
|
||||
defm: HvxLd_pat<MI, Load, VecI8, IsVecOff>;
|
||||
defm: HvxLd_pat<MI, Load, VecI16, IsVecOff>;
|
||||
defm: HvxLd_pat<MI, Load, VecI32, IsVecOff>;
|
||||
multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
|
||||
PatFrag ImmPred> {
|
||||
let AddedComplexity = 50 in {
|
||||
def: Pat<(ResType (Load (valignaddr I32:$Rt))),
|
||||
(MI I32:$Rt, 0)>;
|
||||
def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
|
||||
(MI I32:$Rt, imm:$Off)>;
|
||||
}
|
||||
defm: HvxLdVs_pat<V6_vL32b_nt_ai, alignednontemporalload>;
|
||||
defm: HvxLdVs_pat<V6_vL32b_ai, alignedload>;
|
||||
defm: HvxLdVs_pat<V6_vL32Ub_ai, unalignedload>;
|
||||
|
||||
multiclass HvxLdWs_pat<InstHexagon MI, PatFrag Load> {
|
||||
defm: HvxLd_pat<MI, Load, VecPI8, IsVecOff>;
|
||||
defm: HvxLd_pat<MI, Load, VecPI16, IsVecOff>;
|
||||
defm: HvxLd_pat<MI, Load, VecPI32, IsVecOff>;
|
||||
}
|
||||
defm: HvxLdWs_pat<PS_vloadrw_nt_ai, alignednontemporalload>;
|
||||
defm: HvxLdWs_pat<PS_vloadrw_ai, alignedload>;
|
||||
defm: HvxLdWs_pat<PS_vloadrwu_ai, unalignedload>;
|
||||
defm: HvxLd_pat<MI, Load, ResType, ImmPred>;
|
||||
}
|
||||
|
||||
let Predicates = [UseHVX] in {
|
||||
defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>;
|
||||
defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;
|
||||
defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;
|
||||
|
||||
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
|
||||
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
|
||||
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
|
||||
|
||||
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
|
||||
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
|
||||
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
|
||||
}
|
||||
|
||||
// HVX stores
|
||||
|
||||
@ -109,23 +152,17 @@ multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
|
||||
}
|
||||
|
||||
let Predicates = [UseHVX] in {
|
||||
multiclass HvxStVs_pat<InstHexagon MI, PatFrag Store> {
|
||||
defm: HvxSt_pat<MI, Store, IsVecOff, HVI8>;
|
||||
defm: HvxSt_pat<MI, Store, IsVecOff, HVI16>;
|
||||
defm: HvxSt_pat<MI, Store, IsVecOff, HVI32>;
|
||||
}
|
||||
defm: HvxStVs_pat<V6_vS32b_nt_ai, alignednontemporalstore>;
|
||||
defm: HvxStVs_pat<V6_vS32b_ai, alignedstore>;
|
||||
defm: HvxStVs_pat<V6_vS32Ub_ai, unalignedstore>;
|
||||
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>;
|
||||
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>;
|
||||
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>;
|
||||
|
||||
multiclass HvxStWs_pat<InstHexagon MI, PatFrag Store> {
|
||||
defm: HvxSt_pat<MI, Store, IsVecOff, HWI8>;
|
||||
defm: HvxSt_pat<MI, Store, IsVecOff, HWI16>;
|
||||
defm: HvxSt_pat<MI, Store, IsVecOff, HWI32>;
|
||||
}
|
||||
defm: HvxStWs_pat<PS_vstorerw_nt_ai, alignednontemporalstore>;
|
||||
defm: HvxStWs_pat<PS_vstorerw_ai, alignedstore>;
|
||||
defm: HvxStWs_pat<PS_vstorerwu_ai, unalignedstore>;
|
||||
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>;
|
||||
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>;
|
||||
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>;
|
||||
|
||||
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>;
|
||||
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>;
|
||||
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>;
|
||||
}
|
||||
|
||||
|
||||
@ -138,6 +175,8 @@ let Predicates = [UseHVX] in {
|
||||
def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
|
||||
def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
|
||||
|
||||
def: Pat<(valignaddr I32:$Rs), (A2_andir I32:$Rs, (NHwLen (i32 0)))>;
|
||||
|
||||
def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
|
||||
(Combinev HvxVR:$Vt, HvxVR:$Vs)>;
|
||||
def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
|
||||
|
||||
26
test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll
Normal file
26
test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=hexagon -disable-packetizer < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: test_00:
|
||||
; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
|
||||
; CHECK-DAG: v[[V01:[0-9]+]] = vmem(r[[B00]]+#1)
|
||||
; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
||||
define void @test_00(<64 x i8>* %p, <64 x i8>* %q) #0 {
|
||||
%v0 = load <64 x i8>, <64 x i8>* %p, align 1
|
||||
store <64 x i8> %v0, <64 x i8>* %q, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_01:
|
||||
; CHECK-DAG: v[[V10:[0-9]+]] = vmem(r[[B01:[0-9]+]]+#0)
|
||||
; CHECK-DAG: v[[V11:[0-9]+]] = vmem(r[[B01]]+#1)
|
||||
; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2)
|
||||
; CHECK: }
|
||||
; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]])
|
||||
; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]])
|
||||
define void @test_01(<128 x i8>* %p, <128 x i8>* %q) #0 {
|
||||
%v0 = load <128 x i8>, <128 x i8>* %p, align 1
|
||||
store <128 x i8> %v0, <128 x i8>* %q, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
|
||||
@ -1,31 +1,31 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon -hvx-expand-unaligned-loads=0 < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: aligned_load:
|
||||
; CHECK: = vmem({{.*}})
|
||||
; CHECK-LABEL: aligned_store:
|
||||
; CHECK: vmem({{.*}}) =
|
||||
; CHECK-LABEL: unaligned_load:
|
||||
; CHECK: = vmemu({{.*}})
|
||||
; CHECK-LABEL: unaligned_store:
|
||||
; CHECK: vmemu({{.*}}) =
|
||||
|
||||
define <16 x i32> @aligned_load(<16 x i32>* %p, <16 x i32> %a) {
|
||||
define <16 x i32> @aligned_load(<16 x i32>* %p, <16 x i32> %a) #0 {
|
||||
%v = load <16 x i32>, <16 x i32>* %p, align 64
|
||||
ret <16 x i32> %v
|
||||
}
|
||||
|
||||
define void @aligned_store(<16 x i32>* %p, <16 x i32> %a) {
|
||||
; CHECK-LABEL: aligned_store:
|
||||
; CHECK: vmem({{.*}}) =
|
||||
define void @aligned_store(<16 x i32>* %p, <16 x i32> %a) #0 {
|
||||
store <16 x i32> %a, <16 x i32>* %p, align 64
|
||||
ret void
|
||||
}
|
||||
|
||||
define <16 x i32> @unaligned_load(<16 x i32>* %p, <16 x i32> %a) {
|
||||
; CHECK-LABEL: unaligned_load:
|
||||
; CHECK: = vmemu({{.*}})
|
||||
define <16 x i32> @unaligned_load(<16 x i32>* %p, <16 x i32> %a) #0 {
|
||||
%v = load <16 x i32>, <16 x i32>* %p, align 32
|
||||
ret <16 x i32> %v
|
||||
}
|
||||
|
||||
define void @unaligned_store(<16 x i32>* %p, <16 x i32> %a) {
|
||||
; CHECK-LABEL: unaligned_store:
|
||||
; CHECK: vmemu({{.*}}) =
|
||||
define void @unaligned_store(<16 x i32>* %p, <16 x i32> %a) #0 {
|
||||
store <16 x i32> %a, <16 x i32>* %p, align 32
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user