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[DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes
This is a cleanup patch -- we're now able to support all flavours of variable location in instruction referencing mode. This patch updates various tests for debug instructions to be broader: numerous code paths try to ignore debug isntructions, and they now have to ignore the additional DBG_PHI and DBG_INSTR_REFs that we can generate. A small amount of rework happens for LiveDebugVariables: as we don't need to track live intervals through regalloc any more, we can get away with unlinking debug instructions before regalloc, then re-inserting them after. Note that this isn't (yet) true of DBG_VALUE_LISTs, they still have to go through live interval tracking. In SelectionDAG, add a helper lambda that emits half-formed DBG_INSTR_REFs for arguments in instr-ref mode, DBG_VALUE otherwise. This is one of the final locations where DBG_VALUEs are emitted for vreg arguments. X86InstrInfo now un-sets the debug instr number on SUB instructions that get mutated into CMP instructions. As the instruction no longer computes a subtraction, we can't use it for variable locations. Differential Revision: https://reviews.llvm.org/D88898
This commit is contained in:
Jeremy Morse
parent
a3b5c3bb94
commit
d7cf7abb78
@ -38,9 +38,11 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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@ -56,6 +58,7 @@
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <algorithm>
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#include <cassert>
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#include <iterator>
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@ -535,10 +538,6 @@ class LDVImpl {
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LiveIntervals *LIS;
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const TargetRegisterInfo *TRI;
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using StashedInstrRef =
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std::tuple<unsigned, unsigned, const DILocalVariable *,
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const DIExpression *, DebugLoc>;
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/// Position and VReg of a PHI instruction during register allocation.
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struct PHIValPos {
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SlotIndex SI; /// Slot where this PHI occurs.
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@ -553,7 +552,17 @@ class LDVImpl {
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/// at different positions.
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DenseMap<Register, std::vector<unsigned>> RegToPHIIdx;
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std::map<SlotIndex, std::vector<StashedInstrRef>> StashedInstrReferences;
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/// Record for any debug instructions unlinked from their blocks during
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/// regalloc. Stores the instr and it's location, so that they can be
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/// re-inserted after regalloc is over.
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struct InstrPos {
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MachineInstr *MI; ///< Debug instruction, unlinked from it's block.
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SlotIndex Idx; ///< Slot position where MI should be re-inserted.
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MachineBasicBlock *MBB; ///< Block that MI was in.
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};
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/// Collection of stored debug instructions, preserved until after regalloc.
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SmallVector<InstrPos, 32> StashedDebugInstrs;
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/// Whether emitDebugValues is called.
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bool EmitDone = false;
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@ -591,15 +600,18 @@ class LDVImpl {
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/// \returns True if the DBG_VALUE instruction should be deleted.
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bool handleDebugValue(MachineInstr &MI, SlotIndex Idx);
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/// Track a DBG_INSTR_REF. This needs to be removed from the MachineFunction
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/// during regalloc -- but there's no need to maintain live ranges, as we
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/// refer to a value rather than a location.
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/// Track variable location debug instructions while using the instruction
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/// referencing implementation. Such debug instructions do not need to be
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/// updated during regalloc because they identify instructions rather than
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/// register locations. However, they needs to be removed from the
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/// MachineFunction during regalloc, then re-inserted later, to avoid
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/// disrupting the allocator.
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///
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/// \param MI DBG_INSTR_REF instruction
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/// \param MI Any DBG_VALUE / DBG_INSTR_REF / DBG_PHI instruction
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/// \param Idx Last valid SlotIndex before instruction
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///
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/// \returns True if the DBG_VALUE instruction should be deleted.
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bool handleDebugInstrRef(MachineInstr &MI, SlotIndex Idx);
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/// \returns Iterator to continue processing from after unlinking.
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MachineBasicBlock::iterator handleDebugInstr(MachineInstr &MI, SlotIndex Idx);
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/// Add DBG_LABEL instruction to UserLabel.
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///
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@ -613,9 +625,11 @@ class LDVImpl {
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/// for each instruction.
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///
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/// \param mf MachineFunction to be scanned.
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/// \param InstrRef Whether to operate in instruction referencing mode. If
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/// true, most of LiveDebugVariables doesn't run.
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///
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/// \returns True if any debug values were found.
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bool collectDebugValues(MachineFunction &mf);
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bool collectDebugValues(MachineFunction &mf, bool InstrRef);
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/// Compute the live intervals of all user values after collecting all
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/// their def points.
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@ -624,14 +638,14 @@ class LDVImpl {
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public:
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LDVImpl(LiveDebugVariables *ps) : pass(*ps) {}
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bool runOnMachineFunction(MachineFunction &mf);
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bool runOnMachineFunction(MachineFunction &mf, bool InstrRef);
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/// Release all memory.
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void clear() {
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MF = nullptr;
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PHIValToPos.clear();
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RegToPHIIdx.clear();
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StashedInstrReferences.clear();
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StashedDebugInstrs.clear();
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userValues.clear();
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userLabels.clear();
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virtRegToEqClass.clear();
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@ -864,17 +878,21 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
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return true;
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}
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bool LDVImpl::handleDebugInstrRef(MachineInstr &MI, SlotIndex Idx) {
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assert(MI.isDebugRef());
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unsigned InstrNum = MI.getOperand(0).getImm();
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unsigned OperandNum = MI.getOperand(1).getImm();
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auto *Var = MI.getDebugVariable();
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auto *Expr = MI.getDebugExpression();
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auto &DL = MI.getDebugLoc();
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StashedInstrRef Stashed =
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std::make_tuple(InstrNum, OperandNum, Var, Expr, DL);
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StashedInstrReferences[Idx].push_back(Stashed);
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return true;
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MachineBasicBlock::iterator LDVImpl::handleDebugInstr(MachineInstr &MI,
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SlotIndex Idx) {
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assert(MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI());
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// In instruction referencing mode, there should be no DBG_VALUE instructions
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// that refer to virtual registers. They might still refer to constants.
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if (MI.isDebugValue())
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assert(!MI.getOperand(0).isReg() || !MI.getOperand(0).getReg().isVirtual());
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// Unlink the instruction, store it in the debug instructions collection.
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auto NextInst = std::next(MI.getIterator());
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auto *MBB = MI.getParent();
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MI.removeFromParent();
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StashedDebugInstrs.push_back({&MI, Idx, MBB});
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return NextInst;
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}
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bool LDVImpl::handleDebugLabel(MachineInstr &MI, SlotIndex Idx) {
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@ -900,7 +918,7 @@ bool LDVImpl::handleDebugLabel(MachineInstr &MI, SlotIndex Idx) {
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return true;
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}
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bool LDVImpl::collectDebugValues(MachineFunction &mf) {
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bool LDVImpl::collectDebugValues(MachineFunction &mf, bool InstrRef) {
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bool Changed = false;
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for (MachineBasicBlock &MBB : mf) {
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for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end();
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@ -919,11 +937,17 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
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: LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
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// Handle consecutive debug instructions with the same slot index.
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do {
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// Only handle DBG_VALUE in handleDebugValue(). Skip all other
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// kinds of debug instructions.
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if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
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(MBBI->isDebugRef() && handleDebugInstrRef(*MBBI, Idx)) ||
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(MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Idx))) {
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// In instruction referencing mode, pass each instr to handleDebugInstr
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// to be unlinked. Ignore DBG_VALUE_LISTs -- they refer to vregs, and
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// need to go through the normal live interval splitting process.
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if (InstrRef && (MBBI->isNonListDebugValue() || MBBI->isDebugPHI() ||
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MBBI->isDebugRef())) {
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MBBI = handleDebugInstr(*MBBI, Idx);
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Changed = true;
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// In normal debug mode, use the dedicated DBG_VALUE / DBG_LABEL handler
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// to track things through register allocation, and erase the instr.
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} else if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
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(MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Idx))) {
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MBBI = MBB.erase(MBBI);
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Changed = true;
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} else
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@ -1238,7 +1262,7 @@ void LDVImpl::computeIntervals() {
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}
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}
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bool LDVImpl::runOnMachineFunction(MachineFunction &mf) {
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bool LDVImpl::runOnMachineFunction(MachineFunction &mf, bool InstrRef) {
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clear();
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MF = &mf;
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LIS = &pass.getAnalysis<LiveIntervals>();
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@ -1246,7 +1270,7 @@ bool LDVImpl::runOnMachineFunction(MachineFunction &mf) {
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LLVM_DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
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<< mf.getName() << " **********\n");
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bool Changed = collectDebugValues(mf);
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bool Changed = collectDebugValues(mf, InstrRef);
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computeIntervals();
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LLVM_DEBUG(print(dbgs()));
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@ -1287,9 +1311,19 @@ bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
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removeDebugInstrs(mf);
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return false;
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}
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// Have we been asked to track variable locations using instruction
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// referencing?
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bool InstrRef = false;
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auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
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if (TPC) {
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auto &TM = TPC->getTM<TargetMachine>();
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InstrRef = TM.Options.ValueTrackingVariableLocations;
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}
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if (!pImpl)
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pImpl = new LDVImpl(this);
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return static_cast<LDVImpl*>(pImpl)->runOnMachineFunction(mf);
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return static_cast<LDVImpl *>(pImpl)->runOnMachineFunction(mf, InstrRef);
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}
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void LiveDebugVariables::releaseMemory() {
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@ -1850,22 +1884,45 @@ void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
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LLVM_DEBUG(dbgs() << "********** EMITTING INSTR REFERENCES **********\n");
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// Re-insert any DBG_INSTR_REFs back in the position they were. Ordering
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// is preserved by vector.
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const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
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for (auto &P : StashedInstrReferences) {
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const SlotIndex &Idx = P.first;
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auto *MBB = Slots->getMBBFromIndex(Idx);
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MachineBasicBlock::iterator insertPos =
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findInsertLocation(MBB, Idx, *LIS, BBSkipInstsMap);
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for (auto &Stashed : P.second) {
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auto MIB = BuildMI(*MF, std::get<4>(Stashed), RefII);
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MIB.addImm(std::get<0>(Stashed));
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MIB.addImm(std::get<1>(Stashed));
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MIB.addMetadata(std::get<2>(Stashed));
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MIB.addMetadata(std::get<3>(Stashed));
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MachineInstr *New = MIB;
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MBB->insert(insertPos, New);
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// Re-insert any debug instrs back in the position they were. Ordering
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// is preserved by vector. We must re-insert in the same order to ensure that
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// debug instructions don't swap, which could re-order assignments.
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for (auto &P : StashedDebugInstrs) {
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SlotIndex Idx = P.Idx;
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// Start block index: find the first non-debug instr in the block, and
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// insert before it.
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if (Idx == Slots->getMBBStartIdx(P.MBB)) {
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MachineBasicBlock::iterator InsertPos =
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findInsertLocation(P.MBB, Idx, *LIS, BBSkipInstsMap);
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P.MBB->insert(InsertPos, P.MI);
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continue;
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}
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if (MachineInstr *Pos = Slots->getInstructionFromIndex(Idx)) {
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// Insert at the end of any debug instructions.
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auto PostDebug = std::next(Pos->getIterator());
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PostDebug = skipDebugInstructionsForward(PostDebug, P.MBB->instr_end());
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P.MBB->insert(PostDebug, P.MI);
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} else {
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// Insert position disappeared; walk forwards through slots until we
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// find a new one.
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SlotIndex End = Slots->getMBBEndIdx(P.MBB);
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for (; Idx < End; Idx = Slots->getNextNonNullIndex(Idx)) {
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Pos = Slots->getInstructionFromIndex(Idx);
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if (Pos) {
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P.MBB->insert(Pos->getIterator(), P.MI);
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break;
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}
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}
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// We have reached the end of the block and didn't find anywhere to
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// insert! It's not safe to discard any debug instructions; place them
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// in front of the first terminator, or in front of end().
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if (Idx >= End) {
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auto TermIt = P.MBB->getFirstTerminator();
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P.MBB->insert(TermIt, P.MI);
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}
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}
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}
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@ -475,7 +475,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
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// Visit all instructions reading li->reg().
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Register Reg = li->reg();
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for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
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if (UseMI.isDebugValue() || !UseMI.readsVirtualRegister(Reg))
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if (UseMI.isDebugInstr() || !UseMI.readsVirtualRegister(Reg))
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continue;
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SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
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LiveQueryResult LRQ = li->Query(Idx);
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@ -718,7 +718,7 @@ MachineSinking::getBBRegisterPressure(MachineBasicBlock &MBB) {
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MIE = MBB.instr_begin();
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MII != MIE; --MII) {
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MachineInstr &MI = *std::prev(MII);
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if (MI.isDebugValue() || MI.isDebugLabel() || MI.isPseudoProbe())
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if (MI.isDebugInstr() || MI.isPseudoProbe())
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continue;
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RegisterOperands RegOpers;
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RegOpers.collect(MI, *TRI, *MRI, false, false);
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@ -928,7 +928,7 @@ RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
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if (UseMO.isUndef())
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continue;
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MachineInstr *UseMI = UseMO.getParent();
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if (UseMI->isDebugValue()) {
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if (UseMI->isDebugInstr()) {
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// FIXME These don't have an instruction index. Not clear we have enough
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// info to decide whether to do this replacement or not. For now do it.
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UseMO.setReg(NewReg);
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@ -1561,7 +1561,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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UI != MRI->use_end();) {
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MachineOperand &UseMO = *UI++;
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MachineInstr *UseMI = UseMO.getParent();
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if (UseMI->isDebugValue()) {
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if (UseMI->isDebugInstr()) {
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if (Register::isPhysicalRegister(DstReg))
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UseMO.substPhysReg(DstReg, *TRI);
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else
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@ -1742,7 +1742,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
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if (SubReg == 0 || MO.isUndef())
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continue;
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MachineInstr &MI = *MO.getParent();
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if (MI.isDebugValue())
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if (MI.isDebugInstr())
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continue;
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SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true);
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addUndefFlag(*DstInt, UseIdx, MO, SubReg);
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@ -1769,7 +1769,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
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// If SrcReg wasn't read, it may still be the case that DstReg is live-in
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// because SrcReg is a sub-register.
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if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
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if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr())
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Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
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// Replace SrcReg with DstReg in all UseMI operands.
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@ -1799,7 +1799,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
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// unused lanes. This may happen with rematerialization.
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DstInt->createSubRange(Allocator, UnusedLanes);
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}
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SlotIndex MIIdx = UseMI->isDebugValue()
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SlotIndex MIIdx = UseMI->isDebugInstr()
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? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
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: LIS->getInstructionIndex(*UseMI);
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SlotIndex UseIdx = MIIdx.getRegSlot(true);
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@ -1815,7 +1815,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
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LLVM_DEBUG({
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dbgs() << "\t\tupdated: ";
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if (!UseMI->isDebugValue())
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if (!UseMI->isDebugInstr())
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dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
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dbgs() << *UseMI;
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});
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@ -873,7 +873,7 @@ void RegPressureTracker::recedeSkipDebugValues() {
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void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
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recedeSkipDebugValues();
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if (CurrPos->isDebugValue() || CurrPos->isPseudoProbe()) {
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if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
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// It's possible to only have debug_value and pseudo probe instructions and
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// hit the start of the block.
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assert(CurrPos == MBB->begin());
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@ -807,7 +807,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
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DbgMI = nullptr;
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}
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if (MI.isDebugValue() || MI.isDebugRef()) {
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if (MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI()) {
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DbgMI = &MI;
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continue;
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}
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@ -5503,6 +5503,35 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
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if (!Arg)
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return false;
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MachineFunction &MF = DAG.getMachineFunction();
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const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
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// Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind
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// we've been asked to pursue.
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auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr,
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bool Indirect) {
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if (Reg.isVirtual() && TM.Options.ValueTrackingVariableLocations) {
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// For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
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// pointing at the VReg, which will be patched up later.
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auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF);
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auto MIB = BuildMI(MF, DL, Inst);
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MIB.addReg(Reg, RegState::Debug);
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MIB.addImm(0);
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MIB.addMetadata(Variable);
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auto *NewDIExpr = FragExpr;
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// We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
|
||||
// the DIExpression.
|
||||
if (Indirect)
|
||||
NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore);
|
||||
MIB.addMetadata(NewDIExpr);
|
||||
return MIB;
|
||||
} else {
|
||||
// Create a completely standard DBG_VALUE.
|
||||
auto &Inst = TII->get(TargetOpcode::DBG_VALUE);
|
||||
return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr);
|
||||
}
|
||||
};
|
||||
|
||||
if (!IsDbgDeclare) {
|
||||
// ArgDbgValues are hoisted to the beginning of the entry block. So we
|
||||
// should only emit as ArgDbgValue if the dbg.value intrinsic is found in
|
||||
@ -5568,9 +5597,6 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
|
||||
}
|
||||
}
|
||||
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
|
||||
|
||||
bool IsIndirect = false;
|
||||
Optional<MachineOperand> Op;
|
||||
// Some arguments' frame index is recorded during argument lowering.
|
||||
@ -5640,9 +5666,9 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
|
||||
DAG.AddDbgValue(SDV, false);
|
||||
continue;
|
||||
}
|
||||
FuncInfo.ArgDbgValues.push_back(
|
||||
BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
|
||||
RegAndSize.first, Variable, *FragmentExpr));
|
||||
MachineInstr *NewMI =
|
||||
MakeVRegDbgValue(RegAndSize.first, *FragmentExpr, IsDbgDeclare);
|
||||
FuncInfo.ArgDbgValues.push_back(NewMI);
|
||||
}
|
||||
};
|
||||
|
||||
@ -5673,11 +5699,15 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
|
||||
|
||||
assert(Variable->isValidLocationForIntrinsic(DL) &&
|
||||
"Expected inlined-at fields to agree");
|
||||
IsIndirect = (Op->isReg()) ? IsIndirect : true;
|
||||
FuncInfo.ArgDbgValues.push_back(
|
||||
BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
|
||||
*Op, Variable, Expr));
|
||||
MachineInstr *NewMI = nullptr;
|
||||
|
||||
if (Op->isReg())
|
||||
NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect);
|
||||
else
|
||||
NewMI = BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), true, *Op,
|
||||
Variable, Expr);
|
||||
|
||||
FuncInfo.ArgDbgValues.push_back(NewMI);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@ -4182,6 +4182,8 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
|
||||
}
|
||||
CmpInstr.setDesc(get(NewOpcode));
|
||||
CmpInstr.RemoveOperand(0);
|
||||
// Mutating this instruction invalidates any debug data associated with it.
|
||||
CmpInstr.setDebugInstrNum(0);
|
||||
// Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
|
||||
if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
|
||||
NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
|
||||
|
||||
@ -106,8 +106,6 @@ body: |
|
||||
%3:gr32 = COPY $edi
|
||||
%6:gr16 = COPY %4.sub_16bit
|
||||
%5:gr16 = COPY %3.sub_16bit
|
||||
DBG_VALUE %5, $noreg, !12, !DIExpression(), debug-location !13
|
||||
DBG_VALUE %6, $noreg, !14, !DIExpression(), debug-location !13
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
%15:gr32 = MOVSX32rr16 %5, debug-location !13
|
||||
$edi = COPY %15, debug-location !13
|
||||
@ -116,7 +114,6 @@ body: |
|
||||
%14:gr32 = MOVSX32rr16 %5, debug-location !13
|
||||
%13:gr32 = ADD32ri8 killed %14, 12, implicit-def $eflags, debug-location !13
|
||||
%11:gr16 = COPY killed %13.sub_16bit, debug-location !13
|
||||
DBG_VALUE %11, $noreg, !12, !DIExpression(), debug-location !13
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
%9:gr32 = MOVSX32rr16 %11, debug-location !13
|
||||
$edi = COPY %9, debug-location !13
|
||||
@ -135,14 +132,12 @@ body: |
|
||||
%20:gr32 = MOVSX32rr16 %11, debug-location !13
|
||||
%19:gr32 = ADD32ri8 killed %20, 1, implicit-def $eflags, debug-location !13
|
||||
%17:gr16 = COPY killed %19.sub_16bit, debug-location !13
|
||||
DBG_VALUE %17, $noreg, !12, !DIExpression(), debug-location !13
|
||||
|
||||
; Verify that vreg 17 is coalesced into gr32.
|
||||
; Verify that vreg 17 is coalesced into a gr32, and not copied any further.
|
||||
; DOESCOALESCE: %{{[0-9]+}}:gr32 = ADD32ri8
|
||||
; DOESCOALESCE-NEXT: DBG_VALUE %{{[0-9]+}}.sub_16bit,
|
||||
; DOESCOALESCE-NOT: COPY
|
||||
; Verify those registers land in $bx
|
||||
; CHECK: renamable $ebp = ADD32ri8
|
||||
; CHECK-NEXT: DBG_VALUE $bp
|
||||
|
||||
; DOESCOALESCE-LABEL: bb.2.if.end:
|
||||
; CHECK-LABEL: bb.2.if.end:
|
||||
@ -154,7 +149,6 @@ body: |
|
||||
%30:gr32 = MOVSX32rr16 killed %2, debug-location !13
|
||||
%29:gr32 = ADD32rr killed %30, killed %31, implicit-def $eflags, debug-location !13
|
||||
%26:gr16 = COPY killed %29.sub_16bit, debug-location !13
|
||||
DBG_VALUE %26, $noreg, !12, !DIExpression(), debug-location !13
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
%24:gr32 = MOVSX32rr16 %26, debug-location !13
|
||||
$edi = COPY %24, debug-location !13
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
#
|
||||
# Original C code, the PHI is of the value of 'bar' after the control flow.
|
||||
# Compiled at -O0, applied -mem2reg, llc -O0, then manually added the PHI
|
||||
# instruction label.
|
||||
# instruction label. Additional variable locations removed.
|
||||
#
|
||||
# void ext(long);
|
||||
# long getlong(void);
|
||||
@ -115,14 +115,11 @@ body: |
|
||||
%3:gr64 = COPY $rdi
|
||||
%4:gr64 = COPY killed %3
|
||||
%6:gr64 = COPY killed %5
|
||||
DBG_VALUE %4, $noreg, !12, !DIExpression(), debug-location !13
|
||||
DBG_VALUE %6, $noreg, !14, !DIExpression(), debug-location !13
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
$rdi = COPY %4, debug-location !13
|
||||
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
|
||||
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
%9:gr64 = ADD64ri32 %4, 12, implicit-def $eflags, debug-location !13
|
||||
DBG_VALUE %9, $noreg, !12, !DIExpression(), debug-location !13
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
$rdi = COPY %9, debug-location !13
|
||||
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
|
||||
@ -138,7 +135,6 @@ body: |
|
||||
; CHECK-LABEL: bb.1.if.then:
|
||||
bb.1.if.then:
|
||||
%10:gr64 = ADD64ri32 %9, 1, implicit-def $eflags, debug-location !13
|
||||
DBG_VALUE %10, $noreg, !12, !DIExpression(), debug-location !13
|
||||
|
||||
; Verify that the vreg is different immediately after register coalescing.
|
||||
; DOESCOALESCE-NOT: %10:gr64 ADD64ri32
|
||||
@ -153,7 +149,6 @@ body: |
|
||||
; CHECK: DBG_PHI $rbx, 1
|
||||
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
|
||||
%14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
|
||||
DBG_VALUE %14, $noreg, !12, !DIExpression(), debug-location !13
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
|
||||
$rdi = COPY %14, debug-location !13
|
||||
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
|
||||
|
||||
@ -77,10 +77,7 @@ body: |
|
||||
DBG_VALUE $edi, $noreg, !11, !DIExpression(), debug-location !12
|
||||
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !12
|
||||
%2:gr32 = COPY killed $esi
|
||||
DBG_VALUE %2, $noreg, !13, !DIExpression(), debug-location !12
|
||||
%1:gr32 = COPY killed $edi
|
||||
DBG_VALUE %1, $noreg, !11, !DIExpression(), debug-location !12
|
||||
DBG_VALUE 0, $noreg, !14, !DIExpression(), debug-location !12
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !15
|
||||
%3:gr32 = MOV32r0 implicit-def dead $eflags
|
||||
$edi = COPY killed %3, debug-location !15
|
||||
@ -107,7 +104,6 @@ body: |
|
||||
JMP_1 %bb.1, debug-location !17
|
||||
|
||||
bb.1:
|
||||
DBG_VALUE %2, $noreg, !14, !DIExpression(), debug-location !12
|
||||
%30:gr32 = MOV32ri 0
|
||||
%31:gr32 = MOV32ri 1
|
||||
%32:gr32 = MOV32ri 2
|
||||
|
||||
@ -103,9 +103,7 @@ body: |
|
||||
DBG_VALUE $edi, $noreg, !11, !DIExpression(), debug-location !12
|
||||
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !12
|
||||
%2:gr32 = COPY killed $esi
|
||||
DBG_VALUE %2, $noreg, !13, !DIExpression(), debug-location !12
|
||||
%1:gr32 = COPY killed $edi
|
||||
DBG_VALUE %1, $noreg, !11, !DIExpression(), debug-location !12
|
||||
DBG_VALUE 0, $noreg, !14, !DIExpression(), debug-location !12
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !15
|
||||
%3:gr32 = MOV32r0 implicit-def dead $eflags
|
||||
@ -118,7 +116,6 @@ body: |
|
||||
JMP_1 %bb.1, debug-location !17
|
||||
|
||||
bb.1.if.else:
|
||||
DBG_VALUE %2, $noreg, !14, !DIExpression(), debug-location !12
|
||||
|
||||
; CHECK-LABEL: bb.2.if.end:
|
||||
bb.2.if.end:
|
||||
|
||||
95
test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
Normal file
95
test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
Normal file
@ -0,0 +1,95 @@
|
||||
# RUN: llc %s -o - -experimental-debug-variable-locations -run-pass=peephole-opt | FileCheck %s
|
||||
#
|
||||
# X86 initially produces subtract operations to perform comparisons, and then
|
||||
# downgrades them into cmp instructions if nothing uses the result. It does this
|
||||
# by calling setDesc on the instruction, mutating it from one sort to another,
|
||||
# which makes any debug instruction numbers attached to the number invalid.
|
||||
# This test tests that the relevant instruction number is dropped.
|
||||
#
|
||||
# CHECK-NOT: debug-instr-number
|
||||
# CHECK: CMP32rm
|
||||
# CHECK-NOT: debug-instr-number
|
||||
#
|
||||
--- |
|
||||
; ModuleID = '/fast/fs/build34llvm4/reduced.ll'
|
||||
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
%"class.std::vector.534" = type { %"struct.std::_Vector_base.535" }
|
||||
%"struct.std::_Vector_base.535" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
|
||||
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { i8*, i8*, i8* }
|
||||
|
||||
; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
|
||||
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
|
||||
|
||||
define hidden fastcc void @soup() unnamed_addr !dbg !3 {
|
||||
_ZN4llvm11raw_ostreamlsEPKc.exit2752:
|
||||
%0 = load %"class.std::vector.534"*, %"class.std::vector.534"** undef, align 8, !dbg !7
|
||||
%1 = load i8*, i8** undef, align 8, !dbg !7
|
||||
%_M_start.i2756 = getelementptr inbounds %"class.std::vector.534", %"class.std::vector.534"* %0, i64 undef, i32 0, i32 0, i32 0, !dbg !7
|
||||
%2 = load i8*, i8** %_M_start.i2756, align 8, !dbg !7
|
||||
%sub.ptr.lhs.cast.i2757 = ptrtoint i8* %1 to i64, !dbg !7
|
||||
%sub.ptr.rhs.cast.i2758 = ptrtoint i8* %2 to i64, !dbg !7
|
||||
%sub.ptr.sub.i2759 = sub i64 %sub.ptr.lhs.cast.i2757, %sub.ptr.rhs.cast.i2758, !dbg !7
|
||||
%conv373 = trunc i64 %sub.ptr.sub.i2759 to i32, !dbg !7
|
||||
call void @llvm.dbg.value(metadata i32 %conv373, metadata !8, metadata !DIExpression()), !dbg !7
|
||||
%cmp375.not2842 = icmp eq i32 %conv373, 0, !dbg !7
|
||||
br i1 %cmp375.not2842, label %for.cond.cleanup376, label %for.body377, !dbg !7
|
||||
|
||||
for.cond.cleanup376: ; preds = %_ZN4llvm11raw_ostreamlsEPKc.exit2752
|
||||
ret void
|
||||
|
||||
for.body377: ; preds = %_ZN4llvm11raw_ostreamlsEPKc.exit2752
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
|
||||
declare void @llvm.dbg.value(metadata, metadata, metadata) #0
|
||||
|
||||
attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }
|
||||
|
||||
!llvm.module.flags = !{!0}
|
||||
!llvm.dbg.cu = !{!1}
|
||||
|
||||
!0 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!1 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !2, producer: "beards", isOptimized: true, runtimeVersion: 4, emissionKind: FullDebug)
|
||||
!2 = !DIFile(filename: "bees.cpp", directory: "")
|
||||
!3 = distinct !DISubprogram(name: "nope", scope: !2, file: !2, line: 1, type: !4, spFlags: DISPFlagDefinition, unit: !1)
|
||||
!4 = !DISubroutineType(types: !5)
|
||||
!5 = !{!6}
|
||||
!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
|
||||
!7 = !DILocation(line: 1, scope: !3)
|
||||
!8 = !DILocalVariable(name: "flannel", scope: !3)
|
||||
|
||||
...
|
||||
---
|
||||
name: soup
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gr64 }
|
||||
- { id: 1, class: gr64 }
|
||||
- { id: 2, class: gr32 }
|
||||
- { id: 3, class: gr32 }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0._ZN4llvm11raw_ostreamlsEPKc.exit2752:
|
||||
successors: %bb.1(0x30000000), %bb.2(0x50000000)
|
||||
|
||||
%1:gr64 = IMPLICIT_DEF
|
||||
%0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`)
|
||||
%2:gr32 = COPY %0.sub_32bit, debug-location !7
|
||||
%3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8)
|
||||
DBG_INSTR_REF 1, 0, !8, !DIExpression(), debug-location !7
|
||||
JCC_1 %bb.2, 5, implicit $eflags, debug-location !7
|
||||
JMP_1 %bb.1, debug-location !7
|
||||
|
||||
bb.1.for.cond.cleanup376:
|
||||
RET 0
|
||||
|
||||
bb.2.for.body377:
|
||||
RET 0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user