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Better codegen of binary integer ops with 32 bit immediate operands.

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This transformation fires a few dozen times across the testsuite.

For example, int test2(int X) { return X ^ 0x0FF00FF0; }
Old:
_test2:
        lis r2, 4080
        ori r2, r2, 4080
        xor r3, r3, r2
        blr

New:
_test2:
        xoris r3, r3, 4080
        xori r3, r3, 4080
        blr

llvm-svn: 17004
This commit is contained in:
Nate Begeman 2004-10-15 00:50:19 +00:00
parent e05e5f0655
commit d8183bd297
1 changed files with 22 additions and 2 deletions
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24
lib/Target/PowerPC/PPC32ISelSimple.cpp
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@ -32,7 +32,7 @@
using namespace llvm;
namespace {
Statistic<> NumClear("ppc-codegen", "Number of AND turned into mask");
Statistic<> NumHiAndLo("ppc-codegen", "Number of 32b imms not loaded");
/// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
/// PPC Representation.
@ -2128,13 +2128,19 @@ void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
if (Opcode == 2) {
unsigned MB, ME, mask = CI->getRawValue();
if (isRunOfOnes(mask, MB, ME)) {
++NumClear;
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(0)
.addImm(MB).addImm(ME);
return;
}
}
// PowerPC 16 bit signed immediates are sign extended before use by the
// instruction. Therefore, we can only split up an add of a reg with a 32 bit
// immediate into addis and addi if the sign bit of the low 16 bits is cleared
// so that for register A, const imm X, we don't end up with
// A + XXXX0000 + FFFFXXXX.
bool WontSignExtend = (0 == (Op1->getRawValue() & 0x8000));
// For Add, Sub, and SubF the instruction takes a signed immediate. For And,
// Or, and Xor, the instruction takes an unsigned immediate. There is no
// shifted immediate form of SubF so disallow its opcode for those constants.
@ -2152,6 +2158,20 @@ void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
else
BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, DestReg).addReg(Op0Reg)
.addZImm(Op1->getRawValue() >> 16);
} else if ((Opcode < 2 && WontSignExtend) || Opcode == 3 || Opcode == 4) {
unsigned TmpReg = makeAnotherReg(Op1->getType());
++NumHiAndLo;
if (Opcode < 2) {
BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, TmpReg).addReg(Op0Reg)
.addSImm(Op1->getRawValue() >> 16);
BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(TmpReg)
.addSImm(Op1->getRawValue());
} else {
BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, TmpReg).addReg(Op0Reg)
.addZImm(Op1->getRawValue() >> 16);
BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(TmpReg)
.addZImm(Op1->getRawValue());
}
} else {
unsigned Op1Reg = getReg(Op1, MBB, IP);
BuildMI(*MBB, IP, OpTab[Opcode], 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);