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[AArch64][GlobalISel] Make G_VECREDUCE_ADD of <2 x s32> legal.

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This commit is contained in:
Amara Emerson 2021-02-19 14:27:08 -08:00
parent ff60cc1168
commit d83de2e66b
2 changed files with 23 additions and 1 deletions
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3
lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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@ -692,7 +692,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.lower();
getActionDefinitionsBuilder(G_VECREDUCE_ADD)
.legalFor({{s8, v16s8}, {s16, v8s16}, {s32, v4s32}, {s64, v2s64}})
.legalFor(
{{s8, v16s8}, {s16, v8s16}, {s32, v4s32}, {s32, v2s32}, {s64, v2s64}})
.lower();
computeTables();

21
test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
View File

@ -88,3 +88,24 @@ body: |
RET_ReallyLR implicit $x0
...
---
name: add_v2s32
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: add_v2s32
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8)
%2:_(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...