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[AArch64][GlobalISel] Support sibling calls with outgoing arguments
This adds support for lowering sibling calls with outgoing arguments. e.g ``` define void @foo(i32 %a) ``` Support is ported from AArch64ISelLowering's `isEligibleForTailCallOptimization`. The only thing that is missing is a full port of `TargetLowering::parametersInCSRMatch`. So, if we're using swiftself, we'll never tail call. - Rename `analyzeCallResult` to `analyzeArgInfo`, since the function is now used for both outgoing and incoming arguments - Teach `OutgoingArgHandler` about tail calls. Tail calls use frame indices for stack arguments. - Teach `lowerFormalArguments` to set the bytes in the caller's stack argument area. This is used later to check if the tail call's parameters will fit on the caller's stack. - Add `areCalleeOutgoingArgsTailCallable` to perform the eligibility check on the callee's outgoing arguments. For testing: - Update call-translator-tail-call to verify that we can now tail call with outgoing arguments, use G_FRAME_INDEX for stack arguments, and respect the size of the caller's stack - Remove GISel-specific check lines from speculation-hardening.ll, since GISel now tail calls like the other selectors - Add a GISel test line to tailcall-string-rvo.ll since we can tail call in that test now - Add a GISel test line to tailcall_misched_graph.ll since we tail call there now. Add specific check lines for GISel, since the debug output from the machine-scheduler differs with GlobalISel. The dependency still holds, but the output comes out in a different order. Differential Revision: https://reviews.llvm.org/D67471 llvm-svn: 371780
This commit is contained in:
Jessica Paquette
parent
862ec62f6f
commit
d84c7b0582
@ -211,10 +211,12 @@ protected:
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SmallVectorImpl<ArgInfo> &Args,
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ValueHandler &Handler) const;
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/// Analyze the return values of a call, incorporating info about the passed
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/// values into \p CCState.
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bool analyzeCallResult(CCState &CCState, SmallVectorImpl<ArgInfo> &Args,
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CCAssignFn &Fn) const;
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/// Analyze passed or returned values from a call, supplied in \p ArgInfo,
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/// incorporating info about the passed values into \p CCState.
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///
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/// Used to check if arguments are suitable for tail call lowering.
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bool analyzeArgInfo(CCState &CCState, SmallVectorImpl<ArgInfo> &Args,
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CCAssignFn &Fn) const;
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/// \returns True if the calling convention for a callee and its caller pass
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/// results in the same way. Typically used for tail call eligibility checks.
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@ -378,7 +378,7 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
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return true;
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}
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bool CallLowering::analyzeCallResult(CCState &CCState,
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bool CallLowering::analyzeArgInfo(CCState &CCState,
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SmallVectorImpl<ArgInfo> &Args,
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CCAssignFn &Fn) const {
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for (unsigned i = 0, e = Args.size(); i < e; ++i) {
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@ -407,12 +407,12 @@ bool CallLowering::resultsCompatible(CallLoweringInfo &Info,
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SmallVector<CCValAssign, 16> ArgLocs1;
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CCState CCInfo1(CalleeCC, false, MF, ArgLocs1, F.getContext());
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if (!analyzeCallResult(CCInfo1, InArgs, CalleeAssignFn))
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if (!analyzeArgInfo(CCInfo1, InArgs, CalleeAssignFn))
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return false;
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SmallVector<CCValAssign, 16> ArgLocs2;
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CCState CCInfo2(CallerCC, false, MF, ArgLocs2, F.getContext());
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if (!analyzeCallResult(CCInfo2, InArgs, CallerAssignFn))
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if (!analyzeArgInfo(CCInfo2, InArgs, CallerAssignFn))
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return false;
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// We need the argument locations to match up exactly. If there's more in
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@ -130,14 +130,26 @@ struct CallReturnHandler : public IncomingArgHandler {
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struct OutgoingArgHandler : public CallLowering::ValueHandler {
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OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB, CCAssignFn *AssignFn,
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CCAssignFn *AssignFnVarArg)
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CCAssignFn *AssignFnVarArg, bool IsTailCall = false)
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: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
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AssignFnVarArg(AssignFnVarArg), StackSize(0) {}
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AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), StackSize(0) {}
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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MachineFunction &MF = MIRBuilder.getMF();
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LLT p0 = LLT::pointer(0, 64);
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LLT s64 = LLT::scalar(64);
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if (IsTailCall) {
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// TODO: For -tailcallopt tail calls, Offset will need FPDiff like in
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// ISelLowering.
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int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
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Register FIReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildFrameIndex(FIReg, FI);
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MPO = MachinePointerInfo::getFixedStack(MF, FI);
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return FIReg;
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}
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Register SPReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
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@ -147,7 +159,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
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Register AddrReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
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MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
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MPO = MachinePointerInfo::getStack(MF, Offset);
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return AddrReg;
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}
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@ -188,6 +200,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
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MachineInstrBuilder MIB;
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CCAssignFn *AssignFnVarArg;
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bool IsTailCall;
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uint64_t StackSize;
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};
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} // namespace
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@ -378,6 +391,8 @@ bool AArch64CallLowering::lowerFormalArguments(
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if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
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return false;
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AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
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uint64_t StackOffset = Handler.StackUsed;
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if (F.isVarArg()) {
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auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
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if (!Subtarget.isTargetDarwin()) {
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@ -387,14 +402,20 @@ bool AArch64CallLowering::lowerFormalArguments(
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}
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// We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
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uint64_t StackOffset =
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alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8);
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StackOffset = alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8);
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
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FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
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}
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// TODO: Port checks for stack to restore for -tailcallopt from ISelLowering.
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// We need to keep track of the size of function stacks for tail call
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// optimization. When we tail call, we need to check if the callee's arguments
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// will fit on the caller's stack. So, whenever we lower formal arguments,
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// we should keep track of this information, since we might lower a tail call
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// in this function later.
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FuncInfo->setBytesInStackArgArea(StackOffset);
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auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
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if (Subtarget.hasCustomCallingConv())
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Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
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@ -454,9 +475,67 @@ bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
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return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
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}
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bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
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CallLoweringInfo &Info, MachineFunction &MF,
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SmallVectorImpl<ArgInfo> &OutArgs) const {
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// If there are no outgoing arguments, then we are done.
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if (OutArgs.empty())
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return true;
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const Function &CallerF = MF.getFunction();
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CallingConv::ID CalleeCC = Info.CallConv;
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CallingConv::ID CallerCC = CallerF.getCallingConv();
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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// We have outgoing arguments. Make sure that we can tail call with them.
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SmallVector<CCValAssign, 16> OutLocs;
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CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
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if (!analyzeArgInfo(OutInfo, OutArgs,
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*TLI.CCAssignFnForCall(CalleeCC, Info.IsVarArg))) {
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LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
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return false;
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}
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// Make sure that they can fit on the caller's stack.
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const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
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if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
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LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
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return false;
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}
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// Verify that the parameters in callee-saved registers match.
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// TODO: Port this over to CallLowering as general code once swiftself is
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// supported.
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auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
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const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
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for (auto &ArgLoc : OutLocs) {
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// If it's not a register, it's fine.
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if (!ArgLoc.isRegLoc())
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continue;
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Register Reg = ArgLoc.getLocReg();
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// Only look at callee-saved registers.
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if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
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continue;
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// TODO: Port the remainder of this check from TargetLowering to support
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// tail calling swiftself.
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LLVM_DEBUG(
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dbgs()
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<< "... Cannot handle callee-saved registers in outgoing args yet.\n");
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return false;
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}
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return true;
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}
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bool AArch64CallLowering::isEligibleForTailCallOptimization(
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MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
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SmallVectorImpl<ArgInfo> &InArgs) const {
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SmallVectorImpl<ArgInfo> &InArgs,
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SmallVectorImpl<ArgInfo> &OutArgs) const {
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CallingConv::ID CalleeCC = Info.CallConv;
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &CallerF = MF.getFunction();
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@ -535,7 +614,8 @@ bool AArch64CallLowering::isEligibleForTailCallOptimization(
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assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
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"Unexpected variadic calling convention");
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// Look at the incoming values.
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// Verify that the incoming and outgoing arguments from the callee are
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// safe to tail call.
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if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
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LLVM_DEBUG(
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dbgs()
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@ -543,13 +623,8 @@ bool AArch64CallLowering::isEligibleForTailCallOptimization(
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return false;
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}
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// For now, only handle callees that take no arguments.
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if (!Info.OrigArgs.empty()) {
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LLVM_DEBUG(
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dbgs()
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<< "... Cannot tail call callees with outgoing arguments yet.\n");
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if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
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return false;
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}
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LLVM_DEBUG(
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dbgs() << "... Call is eligible for tail call optimization.\n");
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@ -592,20 +667,20 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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return false;
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}
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SmallVector<ArgInfo, 8> SplitArgs;
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SmallVector<ArgInfo, 8> OutArgs;
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for (auto &OrigArg : Info.OrigArgs) {
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splitToValueTypes(OrigArg, SplitArgs, DL, MRI, Info.CallConv);
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splitToValueTypes(OrigArg, OutArgs, DL, MRI, Info.CallConv);
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// AAPCS requires that we zero-extend i1 to 8 bits by the caller.
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if (OrigArg.Ty->isIntegerTy(1))
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SplitArgs.back().Flags[0].setZExt();
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OutArgs.back().Flags[0].setZExt();
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}
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SmallVector<ArgInfo, 8> InArgs;
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if (!Info.OrigRet.Ty->isVoidTy())
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splitToValueTypes(Info.OrigRet, InArgs, DL, MRI, F.getCallingConv());
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bool IsSibCall = Info.IsTailCall &&
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isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs);
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bool IsSibCall = Info.IsTailCall && isEligibleForTailCallOptimization(
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MIRBuilder, Info, InArgs, OutArgs);
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if (IsSibCall)
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MF.getFrameInfo().setHasTailCall();
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@ -655,8 +730,8 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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// Do the actual argument marshalling.
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SmallVector<unsigned, 8> PhysRegs;
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OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
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AssignFnVarArg);
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if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
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AssignFnVarArg, IsSibCall);
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if (!handleAssignments(MIRBuilder, OutArgs, Handler))
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return false;
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// Now we can add the actual call instruction to the correct basic block.
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@ -47,7 +47,8 @@ public:
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bool
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isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info,
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SmallVectorImpl<ArgInfo> &InArgs) const;
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SmallVectorImpl<ArgInfo> &InArgs,
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SmallVectorImpl<ArgInfo> &OutArgs) const;
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bool supportSwiftError() const override { return true; }
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@ -67,6 +68,10 @@ private:
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doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info,
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MachineFunction &MF,
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SmallVectorImpl<ArgInfo> &InArgs) const;
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bool
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areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF,
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SmallVectorImpl<ArgInfo> &OutArgs) const;
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};
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} // end namespace llvm
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@ -24,22 +24,45 @@ define void @indirect_tail_call(void()* %func) {
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}
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declare void @outgoing_args_fn(i32)
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; Right now, callees with outgoing arguments should not be tail called.
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; TODO: Support this.
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define void @test_outgoing_args(i32 %a) {
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; COMMON-LABEL: name: test_outgoing_args
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; COMMON: bb.1 (%ir-block.0):
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; COMMON: liveins: $w0
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; COMMON: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; COMMON: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; COMMON: $w0 = COPY [[COPY]](s32)
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; COMMON: BL @outgoing_args_fn, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
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; COMMON: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; COMMON: RET_ReallyLR
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; COMMON: TCRETURNdi @outgoing_args_fn, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0
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tail call void @outgoing_args_fn(i32 %a)
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ret void
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}
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; Verify that we create frame indices for memory arguments in tail calls.
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; We get a bunch of copies here which are unused and thus eliminated. So, let's
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; just focus on what matters, which is that we get a G_FRAME_INDEX.
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declare void @outgoing_stack_args_fn(<4 x half>)
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define void @test_outgoing_stack_args([8 x <2 x double>], <4 x half> %arg) {
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; COMMON-LABEL: name: test_outgoing_stack_args
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; COMMON: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; COMMON: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.0, align 1)
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; COMMON: $d0 = COPY [[LOAD]](<4 x s16>)
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; COMMON: TCRETURNdi @outgoing_stack_args_fn, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
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tail call void @outgoing_stack_args_fn(<4 x half> %arg)
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ret void
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}
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; Verify that we don't tail call when we cannot fit arguments on the caller's
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; stack.
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declare i32 @too_big_stack(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, i8 %c, i16 %s)
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define i32 @test_too_big_stack() {
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; COMMON-LABEL: name: test_too_big_stack
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; COMMON-NOT: TCRETURNdi
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; COMMON-NOT: TCRETURNri
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; COMMON: BL @too_big_stack
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; COMMON-DAG: RET_ReallyLR
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entry:
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%call = tail call i32 @too_big_stack(i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i8 8, i16 9)
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ret i32 %call
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}
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; Right now, we don't want to tail call callees with nonvoid return types, since
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; call lowering will insert COPYs after the call.
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; TODO: Support this.
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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; RUN: llc -global-isel < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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@t = weak global i32 ()* null
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@x = external global i32, align 4
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@ -1,9 +1,9 @@
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,SLH,NOGISELSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,NOSLH,NOGISELNOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,SLH,GISELSLH --dump-input-on-failure
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; RUN sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,NOSLH,GISELNOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -fast-isel | FileCheck %s --check-prefixes=CHECK,SLH,NOGISELSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -fast-isel | FileCheck %s --check-prefixes=CHECK,NOSLH,NOGISELNOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,SLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,NOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,SLH --dump-input-on-failure
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; RUN sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,NOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -fast-isel | FileCheck %s --check-prefixes=CHECK,SLH --dump-input-on-failure
|
||||
; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -fast-isel | FileCheck %s --check-prefixes=CHECK,NOSLH --dump-input-on-failure
|
||||
|
||||
define i32 @f(i8* nocapture readonly %p, i32 %i, i32 %N) local_unnamed_addr SLHATTR {
|
||||
; CHECK-LABEL: f
|
||||
@ -54,24 +54,13 @@ return: ; preds = %entry, %if.then
|
||||
; Make sure that for a tail call, taint doesn't get put into SP twice.
|
||||
define i32 @tail_caller(i32 %a) local_unnamed_addr SLHATTR {
|
||||
; CHECK-LABEL: tail_caller:
|
||||
; NOGISELSLH: mov [[TMPREG:x[0-9]+]], sp
|
||||
; NOGISELSLH: and [[TMPREG]], [[TMPREG]], x16
|
||||
; NOGISELSLH: mov sp, [[TMPREG]]
|
||||
; NOGISELNOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
|
||||
; NOGISELNOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
|
||||
; NOGISELNOSLH-NOT: mov sp, [[TMPREG]]
|
||||
; GISELSLH: mov [[TMPREG:x[0-9]+]], sp
|
||||
; GISELSLH: and [[TMPREG]], [[TMPREG]], x16
|
||||
; GISELSLH: mov sp, [[TMPREG]]
|
||||
; GISELNOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
|
||||
; GISELNOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
|
||||
; GISELNOSLH-NOT: mov sp, [[TMPREG]]
|
||||
; GlobalISel doesn't optimize tail calls (yet?), so only check that
|
||||
; cross-call taint register setup code is missing if a tail call was
|
||||
; actually produced.
|
||||
; NOGISELSLH: b tail_callee
|
||||
; GISELSLH: bl tail_callee
|
||||
; GISELSLH: cmp sp, #0
|
||||
; SLH: mov [[TMPREG:x[0-9]+]], sp
|
||||
; SLH: and [[TMPREG]], [[TMPREG]], x16
|
||||
; SLH: mov sp, [[TMPREG]]
|
||||
; NOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
|
||||
; NOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
|
||||
; NOSLH-NOT: mov sp, [[TMPREG]]
|
||||
; SLH: b tail_callee
|
||||
; SLH-NOT: cmp sp, #0
|
||||
%call = tail call i32 @tail_callee(i32 %a)
|
||||
ret i32 %call
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -relocation-model=static -verify-machineinstrs -O2 < %s | FileCheck %s
|
||||
; RUN: llc -relocation-model=static -verify-machineinstrs -global-isel -O2 < %s | FileCheck %s
|
||||
|
||||
; The call to function TestBar should be a tail call, when in C++ the string
|
||||
; `ret` is RVO returned.
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -mcpu=cyclone -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s
|
||||
; RUN: llc -mcpu=cyclone -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s --check-prefixes=COMMON,SDAG
|
||||
; RUN: llc -mcpu=cyclone -global-isel -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s --check-prefixes=COMMON,GISEL
|
||||
|
||||
; REQUIRES: asserts
|
||||
|
||||
@ -20,25 +21,34 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*,
|
||||
; PR23459 has a test case that we where miscompiling because of this at the
|
||||
; time.
|
||||
|
||||
; CHECK: Frame Objects
|
||||
; CHECK: fi#-4: {{.*}} fixed, at location [SP+8]
|
||||
; CHECK: fi#-3: {{.*}} fixed, at location [SP]
|
||||
; CHECK: fi#-2: {{.*}} fixed, at location [SP+8]
|
||||
; CHECK: fi#-1: {{.*}} fixed, at location [SP]
|
||||
; COMMON: Frame Objects
|
||||
; COMMON: fi#-4: {{.*}} fixed, at location [SP+8]
|
||||
; COMMON: fi#-3: {{.*}} fixed, at location [SP]
|
||||
; COMMON: fi#-2: {{.*}} fixed, at location [SP+8]
|
||||
; COMMON: fi#-1: {{.*}} fixed, at location [SP]
|
||||
|
||||
; CHECK: [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
|
||||
; CHECK: [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
|
||||
; CHECK: STRXui %{{.*}}, %fixed-stack.0
|
||||
; CHECK: STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
|
||||
; The order that these appear in differes in GISel than SDAG, but the
|
||||
; dependency relationship still holds.
|
||||
; COMMON: [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
|
||||
; COMMON: [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
|
||||
; SDAG: STRXui %{{.*}}, %fixed-stack.0
|
||||
; SDAG: STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
|
||||
; GISEL: STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
|
||||
; GISEL: STRXui %{{.*}}, %fixed-stack.0
|
||||
|
||||
; Make sure that there is an dependence edge between fi#-2 and fi#-4.
|
||||
; Without this edge the scheduler would be free to move the store accross the load.
|
||||
|
||||
; CHECK: SU({{.*}}): [[VRB]]:gpr64 = LDRXui %fixed-stack.2
|
||||
; CHECK-NOT: SU
|
||||
; CHECK: Successors:
|
||||
; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0
|
||||
; CHECK: SU([[DEPSTOREA:.*]]): Ord Latency=0
|
||||
; COMMON: SU({{.*}}): [[VRB]]:gpr64 = LDRXui %fixed-stack.2
|
||||
; COMMON-NOT: SU
|
||||
; COMMON: Successors:
|
||||
; COMMON: SU([[DEPSTOREB:.*]]): Ord Latency=0
|
||||
; COMMON: SU([[DEPSTOREA:.*]]): Ord Latency=0
|
||||
|
||||
; CHECK: SU([[DEPSTOREA]]): STRXui %{{.*}}, %fixed-stack.0
|
||||
; CHECK: SU([[DEPSTOREB]]): STRXui %{{.*}}, %fixed-stack.1
|
||||
; GlobalISel outputs DEPSTOREB before DEPSTOREA, but the dependency relationship
|
||||
; still holds.
|
||||
; SDAG: SU([[DEPSTOREA]]): STRXui %{{.*}}, %fixed-stack.0
|
||||
; SDAG: SU([[DEPSTOREB]]): STRXui %{{.*}}, %fixed-stack.1
|
||||
|
||||
; GISEL: SU([[DEPSTOREB]]): STRXui %{{.*}}, %fixed-stack.0
|
||||
; GISEL: SU([[DEPSTOREA]]): STRXui %{{.*}}, %fixed-stack.1
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user