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Add support for several vector shifts operations while in AVX mode. Fix PR10581
llvm-svn: 137067
This commit is contained in:
Bruno Cardoso Lopes
parent
ffac5ceead
commit
d8534855ff
@ -883,7 +883,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
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}
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if (Subtarget->hasSSE41()) {
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if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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@ -922,10 +922,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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}
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if (Subtarget->hasSSE2()) {
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if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
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setOperationAction(ISD::SRL, MVT::v2i64, Custom);
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setOperationAction(ISD::SRL, MVT::v4i32, Custom);
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setOperationAction(ISD::SRL, MVT::v16i8, Custom);
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setOperationAction(ISD::SRL, MVT::v8i16, Custom);
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setOperationAction(ISD::SHL, MVT::v2i64, Custom);
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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@ -935,7 +936,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SRA, MVT::v8i16, Custom);
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}
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if (Subtarget->hasSSE42())
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if (Subtarget->hasSSE42() || Subtarget->hasAVX())
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setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
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if (!UseSoftFloat && Subtarget->hasAVX()) {
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@ -975,6 +976,19 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
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setOperationAction(ISD::SRL, MVT::v4i64, Custom);
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setOperationAction(ISD::SRL, MVT::v8i32, Custom);
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setOperationAction(ISD::SRL, MVT::v16i16, Custom);
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setOperationAction(ISD::SRL, MVT::v32i8, Custom);
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setOperationAction(ISD::SHL, MVT::v4i64, Custom);
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setOperationAction(ISD::SHL, MVT::v8i32, Custom);
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setOperationAction(ISD::SHL, MVT::v16i16, Custom);
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setOperationAction(ISD::SHL, MVT::v32i8, Custom);
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v16i16, Custom);
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// Custom lower several nodes for 256-bit types.
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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@ -9195,11 +9209,42 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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SDValue R = Op.getOperand(0);
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SDValue Amt = Op.getOperand(1);
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LLVMContext *Context = DAG.getContext();
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// Must have SSE2.
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if (!Subtarget->hasSSE2()) return SDValue();
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if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
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return SDValue();
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// Decompose 256-bit shifts into smaller 128-bit shifts.
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if (VT.getSizeInBits() == 256) {
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int NumElems = VT.getVectorNumElements();
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MVT EltVT = VT.getVectorElementType().getSimpleVT();
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EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
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// Extract the two vectors
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SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
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SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
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DAG, dl);
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// Recreate the shift amount vectors
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SmallVector<SDValue, 4> Amt1Csts;
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SmallVector<SDValue, 4> Amt2Csts;
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for (int i = 0; i < NumElems/2; ++i)
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Amt1Csts.push_back(Amt->getOperand(i));
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for (int i = NumElems/2; i < NumElems; ++i)
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Amt2Csts.push_back(Amt->getOperand(i));
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SDValue Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
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&Amt1Csts[0], NumElems/2);
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SDValue Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
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&Amt2Csts[0], NumElems/2);
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// Issue new vector shifts for the smaller types
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V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
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V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
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// Concatenate the result back
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
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}
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// Optimize shl/srl/sra with constant shift amount.
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if (isSplatVector(Amt.getNode())) {
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@ -9250,9 +9295,6 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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}
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// Lower SHL with variable shift amount.
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// Cannot lower SHL without SSE2 or later.
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if (!Subtarget->hasSSE2()) return SDValue();
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if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
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Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
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@ -12099,7 +12141,7 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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// all elements are shifted by the same amount. We can't do this in legalize
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// because the a constant vector is typically transformed to a constant pool
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// so we have no knowledge of the shift amount.
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if (!Subtarget->hasSSE2())
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if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
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return SDValue();
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if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
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64
test/CodeGen/X86/avx-shift.ll
Normal file
64
test/CodeGen/X86/avx-shift.ll
Normal file
@ -0,0 +1,64 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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;;; Shift left
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; CHECK: vpslld
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; CHECK: vpslld
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define <8 x i32> @vshift00(<8 x i32> %a) nounwind readnone {
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%s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsllw
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; CHECK: vpsllw
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define <16 x i16> @vshift01(<16 x i16> %a) nounwind readnone {
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%s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsllq
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; CHECK: vpsllq
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define <4 x i64> @vshift02(<4 x i64> %a) nounwind readnone {
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%s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %s
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}
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;;; Logical Shift right
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; CHECK: vpsrld
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; CHECK: vpsrld
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define <8 x i32> @vshift03(<8 x i32> %a) nounwind readnone {
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%s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsrlw
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; CHECK: vpsrlw
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define <16 x i16> @vshift04(<16 x i16> %a) nounwind readnone {
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%s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsrlq
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; CHECK: vpsrlq
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define <4 x i64> @vshift05(<4 x i64> %a) nounwind readnone {
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%s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %s
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}
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;;; Arithmetic Shift right
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; CHECK: vpsrad
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; CHECK: vpsrad
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define <8 x i32> @vshift06(<8 x i32> %a) nounwind readnone {
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%s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsraw
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; CHECK: vpsraw
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define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
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%s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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