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[APInt] Rename getSignBit to getSignMask

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getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask.

Differential Revision: https://reviews.llvm.org/D32108

llvm-svn: 300856
This commit is contained in:
Craig Topper 2017-04-20 16:56:25 +00:00
parent bfd4f2473f
commit d8d347a0e2
18 changed files with 102 additions and 102 deletions
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12
include/llvm/ADT/APInt.h
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@ -416,10 +416,10 @@ public:
return countPopulationSlowCase() == 1; return countPopulationSlowCase() == 1;
} }
/// \brief Check if the APInt's value is returned by getSignBit. /// \brief Check if the APInt's value is returned by getSignMask.
/// ///
/// \returns true if this is the value returned by getSignBit. /// \returns true if this is the value returned by getSignMask.
bool isSignBit() const { return isMinSignedValue(); } bool isSignMask() const { return isMinSignedValue(); }
/// \brief Convert APInt to a boolean value. /// \brief Convert APInt to a boolean value.
/// ///
@ -497,11 +497,11 @@ public:
return API; return API;
} }
/// \brief Get the SignBit for a specific bit width. /// \brief Get the SignMask for a specific bit width.
/// ///
/// This is just a wrapper function of getSignedMinValue(), and it helps code /// This is just a wrapper function of getSignedMinValue(), and it helps code
/// readability when we want to get a SignBit. /// readability when we want to get a SignMask.
static APInt getSignBit(unsigned BitWidth) { static APInt getSignMask(unsigned BitWidth) {
return getSignedMinValue(BitWidth); return getSignedMinValue(BitWidth);
} }

10
include/llvm/IR/PatternMatch.h
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@ -267,15 +267,15 @@ inline cst_pred_ty<is_all_ones> m_AllOnes() {
} }
inline api_pred_ty<is_all_ones> m_AllOnes(const APInt *&V) { return V; } inline api_pred_ty<is_all_ones> m_AllOnes(const APInt *&V) { return V; }
struct is_sign_bit { struct is_sign_mask {
bool isValue(const APInt &C) { return C.isSignBit(); } bool isValue(const APInt &C) { return C.isSignMask(); }
}; };
/// \brief Match an integer or vector with only the sign bit(s) set. /// \brief Match an integer or vector with only the sign bit(s) set.
inline cst_pred_ty<is_sign_bit> m_SignBit() { inline cst_pred_ty<is_sign_mask> m_SignMask() {
return cst_pred_ty<is_sign_bit>(); return cst_pred_ty<is_sign_mask>();
} }
inline api_pred_ty<is_sign_bit> m_SignBit(const APInt *&V) { return V; } inline api_pred_ty<is_sign_mask> m_SignMask(const APInt *&V) { return V; }
struct is_power2 { struct is_power2 {
bool isValue(const APInt &C) { return C.isPowerOf2(); } bool isValue(const APInt &C) { return C.isPowerOf2(); }

8
lib/Analysis/InstructionSimplify.cpp
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@ -568,11 +568,11 @@ static Value *SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
match(Op1, m_Not(m_Specific(Op0)))) match(Op1, m_Not(m_Specific(Op0))))
return Constant::getAllOnesValue(Ty); return Constant::getAllOnesValue(Ty);
// add nsw/nuw (xor Y, signbit), signbit --> Y // add nsw/nuw (xor Y, signmask), signmask --> Y
// The no-wrapping add guarantees that the top bit will be set by the add. // The no-wrapping add guarantees that the top bit will be set by the add.
// Therefore, the xor must be clearing the already set sign bit of Y. // Therefore, the xor must be clearing the already set sign bit of Y.
if ((isNSW || isNUW) && match(Op1, m_SignBit()) && if ((isNSW || isNUW) && match(Op1, m_SignMask()) &&
match(Op0, m_Xor(m_Value(Y), m_SignBit()))) match(Op0, m_Xor(m_Value(Y), m_SignMask())))
return Y; return Y;
/// i1 add -> xor. /// i1 add -> xor.
@ -2819,7 +2819,7 @@ static Value *simplifyICmpWithBinOp(CmpInst::Predicate Pred, Value *LHS,
return ConstantInt::getTrue(RHS->getContext()); return ConstantInt::getTrue(RHS->getContext());
} }
} }
if (CIVal->isSignBit() && *CI2Val == 1) { if (CIVal->isSignMask() && *CI2Val == 1) {
if (Pred == ICmpInst::ICMP_UGT) if (Pred == ICmpInst::ICMP_UGT)
return ConstantInt::getFalse(RHS->getContext()); return ConstantInt::getFalse(RHS->getContext());
if (Pred == ICmpInst::ICMP_ULE) if (Pred == ICmpInst::ICMP_ULE)

8
lib/Analysis/ScalarEvolution.cpp
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@ -4007,9 +4007,9 @@ static Optional<BinaryOp> MatchBinaryOp(Value *V, DominatorTree &DT) {
case Instruction::Xor: case Instruction::Xor:
if (auto *RHSC = dyn_cast<ConstantInt>(Op->getOperand(1))) if (auto *RHSC = dyn_cast<ConstantInt>(Op->getOperand(1)))
// If the RHS of the xor is a signbit, then this is just an add. // If the RHS of the xor is a signmask, then this is just an add.
// Instcombine turns add of signbit into xor as a strength reduction step. // Instcombine turns add of signmask into xor as a strength reduction step.
if (RHSC->getValue().isSignBit()) if (RHSC->getValue().isSignMask())
return BinaryOp(Instruction::Add, Op->getOperand(0), Op->getOperand(1)); return BinaryOp(Instruction::Add, Op->getOperand(0), Op->getOperand(1));
return BinaryOp(Op); return BinaryOp(Op);
@ -5369,7 +5369,7 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
// using an add, which is equivalent, and re-apply the zext. // using an add, which is equivalent, and re-apply the zext.
APInt Trunc = CI->getValue().trunc(Z0TySize); APInt Trunc = CI->getValue().trunc(Z0TySize);
if (Trunc.zext(getTypeSizeInBits(UTy)) == CI->getValue() && if (Trunc.zext(getTypeSizeInBits(UTy)) == CI->getValue() &&
Trunc.isSignBit()) Trunc.isSignMask())
return getZeroExtendExpr(getAddExpr(Z0, getConstant(Trunc)), return getZeroExtendExpr(getAddExpr(Z0, getConstant(Trunc)),
UTy); UTy);
} }

6
lib/Analysis/ValueTracking.cpp
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@ -1640,9 +1640,9 @@ bool isKnownToBeAPowerOfTwo(const Value *V, bool OrZero, unsigned Depth,
if (match(V, m_Shl(m_One(), m_Value()))) if (match(V, m_Shl(m_One(), m_Value())))
return true; return true;
// (signbit) >>l X is clearly a power of two if the one is not shifted off the // (signmask) >>l X is clearly a power of two if the one is not shifted off
// bottom. If it is shifted off the bottom then the result is undefined. // the bottom. If it is shifted off the bottom then the result is undefined.
if (match(V, m_LShr(m_SignBit(), m_Value()))) if (match(V, m_LShr(m_SignMask(), m_Value())))
return true; return true;
// The remaining tests are all recursive, so bail out if we hit the limit. // The remaining tests are all recursive, so bail out if we hit the limit.

22
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2146,7 +2146,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
if (N->getFlags()->hasNoUnsignedWrap()) if (N->getFlags()->hasNoUnsignedWrap())
return N0; return N0;
if (DAG.MaskedValueIsZero(N1, ~APInt::getSignBit(BitWidth))) { if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
// N1 is either 0 or the minimum signed value. If the sub is NSW, then // N1 is either 0 or the minimum signed value. If the sub is NSW, then
// N1 must be 0 because negating the minimum signed value is undefined. // N1 must be 0 because negating the minimum signed value is undefined.
if (N->getFlags()->hasNoSignedWrap()) if (N->getFlags()->hasNoSignedWrap())
@ -8298,11 +8298,11 @@ static SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG,
switch (N0.getOpcode()) { switch (N0.getOpcode()) {
case ISD::AND: case ISD::AND:
FPOpcode = ISD::FABS; FPOpcode = ISD::FABS;
SignMask = ~APInt::getSignBit(SourceVT.getSizeInBits()); SignMask = ~APInt::getSignMask(SourceVT.getSizeInBits());
break; break;
case ISD::XOR: case ISD::XOR:
FPOpcode = ISD::FNEG; FPOpcode = ISD::FNEG;
SignMask = APInt::getSignBit(SourceVT.getSizeInBits()); SignMask = APInt::getSignMask(SourceVT.getSizeInBits());
break; break;
// TODO: ISD::OR --> ISD::FNABS? // TODO: ISD::OR --> ISD::FNABS?
default: default:
@ -8413,7 +8413,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
assert(VT.getSizeInBits() == 128); assert(VT.getSizeInBits() == 128);
SDValue SignBit = DAG.getConstant( SDValue SignBit = DAG.getConstant(
APInt::getSignBit(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64); APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64);
SDValue FlipBit; SDValue FlipBit;
if (N0.getOpcode() == ISD::FNEG) { if (N0.getOpcode() == ISD::FNEG) {
FlipBit = SignBit; FlipBit = SignBit;
@ -8433,7 +8433,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
AddToWorklist(FlipBits.getNode()); AddToWorklist(FlipBits.getNode());
return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits); return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits);
} }
APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); APInt SignBit = APInt::getSignMask(VT.getSizeInBits());
if (N0.getOpcode() == ISD::FNEG) if (N0.getOpcode() == ISD::FNEG)
return DAG.getNode(ISD::XOR, DL, VT, return DAG.getNode(ISD::XOR, DL, VT,
NewConv, DAG.getConstant(SignBit, DL, VT)); NewConv, DAG.getConstant(SignBit, DL, VT));
@ -8481,7 +8481,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
} }
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
APInt SignBit = APInt::getSignBit(VT.getSizeInBits() / 2); APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2);
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));
AddToWorklist(Cst.getNode()); AddToWorklist(Cst.getNode());
SDValue X = DAG.getBitcast(VT, N0.getOperand(1)); SDValue X = DAG.getBitcast(VT, N0.getOperand(1));
@ -8502,7 +8502,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
AddToWorklist(FlipBits.getNode()); AddToWorklist(FlipBits.getNode());
return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits); return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits);
} }
APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); APInt SignBit = APInt::getSignMask(VT.getSizeInBits());
X = DAG.getNode(ISD::AND, SDLoc(X), VT, X = DAG.getNode(ISD::AND, SDLoc(X), VT,
X, DAG.getConstant(SignBit, SDLoc(X), VT)); X, DAG.getConstant(SignBit, SDLoc(X), VT));
AddToWorklist(X.getNode()); AddToWorklist(X.getNode());
@ -10313,11 +10313,11 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
if (N0.getValueType().isVector()) { if (N0.getValueType().isVector()) {
// For a vector, get a mask such as 0x80... per scalar element // For a vector, get a mask such as 0x80... per scalar element
// and splat it. // and splat it.
SignMask = APInt::getSignBit(N0.getScalarValueSizeInBits()); SignMask = APInt::getSignMask(N0.getScalarValueSizeInBits());
SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
} else { } else {
// For a scalar, just generate 0x80... // For a scalar, just generate 0x80...
SignMask = APInt::getSignBit(IntVT.getSizeInBits()); SignMask = APInt::getSignMask(IntVT.getSizeInBits());
} }
SDLoc DL0(N0); SDLoc DL0(N0);
Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int, Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int,
@ -10418,11 +10418,11 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
if (N0.getValueType().isVector()) { if (N0.getValueType().isVector()) {
// For a vector, get a mask such as 0x7f... per scalar element // For a vector, get a mask such as 0x7f... per scalar element
// and splat it. // and splat it.
SignMask = ~APInt::getSignBit(N0.getScalarValueSizeInBits()); SignMask = ~APInt::getSignMask(N0.getScalarValueSizeInBits());
SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
} else { } else {
// For a scalar, just generate 0x7f... // For a scalar, just generate 0x7f...
SignMask = ~APInt::getSignBit(IntVT.getSizeInBits()); SignMask = ~APInt::getSignMask(IntVT.getSizeInBits());
} }
SDLoc DL(N0); SDLoc DL(N0);
Int = DAG.getNode(ISD::AND, DL, IntVT, Int, Int = DAG.getNode(ISD::AND, DL, IntVT, Int,

4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1343,7 +1343,7 @@ void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
// Convert to an integer of the same size. // Convert to an integer of the same size.
if (TLI.isTypeLegal(IVT)) { if (TLI.isTypeLegal(IVT)) {
State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value); State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
State.SignMask = APInt::getSignBit(NumBits); State.SignMask = APInt::getSignMask(NumBits);
State.SignBit = NumBits - 1; State.SignBit = NumBits - 1;
return; return;
} }
@ -2984,7 +2984,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
EVT NVT = Node->getValueType(0); EVT NVT = Node->getValueType(0);
APFloat apf(DAG.EVTToAPFloatSemantics(VT), APFloat apf(DAG.EVTToAPFloatSemantics(VT),
APInt::getNullValue(VT.getSizeInBits())); APInt::getNullValue(VT.getSizeInBits()));
APInt x = APInt::getSignBit(NVT.getSizeInBits()); APInt x = APInt::getSignMask(NVT.getSizeInBits());
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
Tmp1 = DAG.getConstantFP(apf, dl, VT); Tmp1 = DAG.getConstantFP(apf, dl, VT);
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),

24
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1955,7 +1955,7 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
/// use this predicate to simplify operations downstream. /// use this predicate to simplify operations downstream.
bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
unsigned BitWidth = Op.getScalarValueSizeInBits(); unsigned BitWidth = Op.getScalarValueSizeInBits();
return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); return MaskedValueIsZero(Op, APInt::getSignMask(BitWidth), Depth);
} }
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
@ -2344,11 +2344,11 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
KnownOne.lshrInPlace(*ShAmt); KnownOne.lshrInPlace(*ShAmt);
// If we know the value of the sign bit, then we know it is copied across // If we know the value of the sign bit, then we know it is copied across
// the high bits by the shift amount. // the high bits by the shift amount.
APInt SignBit = APInt::getSignBit(BitWidth); APInt SignMask = APInt::getSignMask(BitWidth);
SignBit.lshrInPlace(*ShAmt); // Adjust to where it is now in the mask. SignMask.lshrInPlace(*ShAmt); // Adjust to where it is now in the mask.
if (KnownZero.intersects(SignBit)) { if (KnownZero.intersects(SignMask)) {
KnownZero.setHighBits(ShAmt->getZExtValue());// New bits are known zero. KnownZero.setHighBits(ShAmt->getZExtValue());// New bits are known zero.
} else if (KnownOne.intersects(SignBit)) { } else if (KnownOne.intersects(SignMask)) {
KnownOne.setHighBits(ShAmt->getZExtValue()); // New bits are known one. KnownOne.setHighBits(ShAmt->getZExtValue()); // New bits are known one.
} }
} }
@ -2361,14 +2361,14 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// present in the input. // present in the input.
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits);
APInt InSignBit = APInt::getSignBit(EBits); APInt InSignMask = APInt::getSignMask(EBits);
APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, EBits); APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, EBits);
// If the sign extended bits are demanded, we know that the sign // If the sign extended bits are demanded, we know that the sign
// bit is demanded. // bit is demanded.
InSignBit = InSignBit.zext(BitWidth); InSignMask = InSignMask.zext(BitWidth);
if (NewBits.getBoolValue()) if (NewBits.getBoolValue())
InputDemandedBits |= InSignBit; InputDemandedBits |= InSignMask;
computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts, computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
Depth + 1); Depth + 1);
@ -2377,10 +2377,10 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// If the sign bit of the input is known set or clear, then we know the // If the sign bit of the input is known set or clear, then we know the
// top bits of the result. // top bits of the result.
if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear if (KnownZero.intersects(InSignMask)) { // Input sign bit known clear
KnownZero |= NewBits; KnownZero |= NewBits;
KnownOne &= ~NewBits; KnownOne &= ~NewBits;
} else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set } else if (KnownOne.intersects(InSignMask)) { // Input sign bit known set
KnownOne |= NewBits; KnownOne |= NewBits;
KnownZero &= ~NewBits; KnownZero &= ~NewBits;
} else { // Input sign bit unknown } else { // Input sign bit unknown
@ -2745,7 +2745,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// a set bit that isn't the sign bit (otherwise it could be INT_MIN). // a set bit that isn't the sign bit (otherwise it could be INT_MIN).
KnownOne2.clearBit(BitWidth - 1); KnownOne2.clearBit(BitWidth - 1);
if (KnownOne2.getBoolValue()) { if (KnownOne2.getBoolValue()) {
KnownZero = APInt::getSignBit(BitWidth); KnownZero = APInt::getSignMask(BitWidth);
break; break;
} }
break; break;
@ -2874,7 +2874,7 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val) const {
// one bit set. // one bit set.
if (Val.getOpcode() == ISD::SRL) { if (Val.getOpcode() == ISD::SRL) {
auto *C = dyn_cast<ConstantSDNode>(Val.getOperand(0)); auto *C = dyn_cast<ConstantSDNode>(Val.getOperand(0));
if (C && C->getAPIntValue().isSignBit()) if (C && C->getAPIntValue().isSignMask())
return true; return true;
} }

16
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -778,7 +778,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If (1) we only need the sign-bit, (2) the setcc operands are the same // If (1) we only need the sign-bit, (2) the setcc operands are the same
// width as the setcc result, and (3) the result of a setcc conforms to 0 or // width as the setcc result, and (3) the result of a setcc conforms to 0 or
// -1, we may be able to bypass the setcc. // -1, we may be able to bypass the setcc.
if (NewMask.isSignBit() && Op0.getScalarValueSizeInBits() == BitWidth && if (NewMask.isSignMask() && Op0.getScalarValueSizeInBits() == BitWidth &&
getBooleanContents(Op.getValueType()) == getBooleanContents(Op.getValueType()) ==
BooleanContent::ZeroOrNegativeOneBooleanContent) { BooleanContent::ZeroOrNegativeOneBooleanContent) {
// If we're testing X < 0, then this compare isn't needed - just use X! // If we're testing X < 0, then this compare isn't needed - just use X!
@ -964,7 +964,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// demand the input sign bit. // demand the input sign bit.
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
if (HighBits.intersects(NewMask)) if (HighBits.intersects(NewMask))
InDemandedMask |= APInt::getSignBit(VT.getScalarSizeInBits()); InDemandedMask |= APInt::getSignMask(VT.getScalarSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
KnownZero, KnownOne, TLO, Depth+1)) KnownZero, KnownOne, TLO, Depth+1))
@ -974,11 +974,11 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
KnownOne.lshrInPlace(ShAmt); KnownOne.lshrInPlace(ShAmt);
// Handle the sign bit, adjusted to where it is now in the mask. // Handle the sign bit, adjusted to where it is now in the mask.
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); APInt SignMask = APInt::getSignMask(BitWidth).lshr(ShAmt);
// If the input sign bit is known to be zero, or if none of the top bits // If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right. // are demanded, turn this into an unsigned shift right.
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { if (KnownZero.intersects(SignMask) || (HighBits & ~NewMask) == HighBits) {
SDNodeFlags Flags; SDNodeFlags Flags;
Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact()); Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
return TLO.CombineTo(Op, return TLO.CombineTo(Op,
@ -996,7 +996,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Op.getOperand(0), NewSA)); Op.getOperand(0), NewSA));
} }
if (KnownOne.intersects(SignBit)) if (KnownOne.intersects(SignMask))
// New bits are known one. // New bits are known one.
KnownOne |= HighBits; KnownOne |= HighBits;
} }
@ -1040,7 +1040,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
return TLO.CombineTo(Op, Op.getOperand(0)); return TLO.CombineTo(Op, Op.getOperand(0));
APInt InSignBit = APInt InSignBit =
APInt::getSignBit(ExVT.getScalarSizeInBits()).zext(BitWidth); APInt::getSignMask(ExVT.getScalarSizeInBits()).zext(BitWidth);
APInt InputDemandedBits = APInt InputDemandedBits =
APInt::getLowBitsSet(BitWidth, APInt::getLowBitsSet(BitWidth,
ExVT.getScalarSizeInBits()) & ExVT.getScalarSizeInBits()) &
@ -1250,7 +1250,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (!TLO.LegalOperations() && if (!TLO.LegalOperations() &&
!Op.getValueType().isVector() && !Op.getValueType().isVector() &&
!Op.getOperand(0).getValueType().isVector() && !Op.getOperand(0).getValueType().isVector() &&
NewMask == APInt::getSignBit(Op.getValueSizeInBits()) && NewMask == APInt::getSignMask(Op.getValueSizeInBits()) &&
Op.getOperand(0).getValueType().isFloatingPoint()) { Op.getOperand(0).getValueType().isFloatingPoint()) {
bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
@ -3356,7 +3356,7 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
SDValue Bias = DAG.getConstant(127, dl, IntVT); SDValue Bias = DAG.getConstant(127, dl, IntVT);
SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl, SDValue SignMask = DAG.getConstant(APInt::getSignMask(VT.getSizeInBits()), dl,
IntVT); IntVT);
SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);

32
lib/Target/X86/X86ISelLowering.cpp
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@ -16069,7 +16069,7 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
unsigned EltBits = EltVT.getSizeInBits(); unsigned EltBits = EltVT.getSizeInBits();
// For FABS, mask is 0x7f...; for FNEG, mask is 0x80... // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
APInt MaskElt = APInt MaskElt =
IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits); IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignMask(EltBits);
const fltSemantics &Sem = const fltSemantics &Sem =
EltVT == MVT::f64 ? APFloat::IEEEdouble() : EltVT == MVT::f64 ? APFloat::IEEEdouble() :
(IsF128 ? APFloat::IEEEquad() : APFloat::IEEEsingle()); (IsF128 ? APFloat::IEEEquad() : APFloat::IEEEsingle());
@ -16132,9 +16132,9 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
// The mask constants are automatically splatted for vector types. // The mask constants are automatically splatted for vector types.
unsigned EltSizeInBits = VT.getScalarSizeInBits(); unsigned EltSizeInBits = VT.getScalarSizeInBits();
SDValue SignMask = DAG.getConstantFP( SDValue SignMask = DAG.getConstantFP(
APFloat(Sem, APInt::getSignBit(EltSizeInBits)), dl, LogicVT); APFloat(Sem, APInt::getSignMask(EltSizeInBits)), dl, LogicVT);
SDValue MagMask = DAG.getConstantFP( SDValue MagMask = DAG.getConstantFP(
APFloat(Sem, ~APInt::getSignBit(EltSizeInBits)), dl, LogicVT); APFloat(Sem, ~APInt::getSignMask(EltSizeInBits)), dl, LogicVT);
// First, clear all bits but the sign bit from the second operand (sign). // First, clear all bits but the sign bit from the second operand (sign).
if (IsFakeVector) if (IsFakeVector)
@ -17344,10 +17344,10 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
// bits of the inputs before performing those operations. // bits of the inputs before performing those operations.
if (FlipSigns) { if (FlipSigns) {
MVT EltVT = VT.getVectorElementType(); MVT EltVT = VT.getVectorElementType();
SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl, SDValue SM = DAG.getConstant(APInt::getSignMask(EltVT.getSizeInBits()), dl,
VT); VT);
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB); Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SM);
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB); Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SM);
} }
SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
@ -22111,11 +22111,11 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
} }
// i64 vector arithmetic shift can be emulated with the transform: // i64 vector arithmetic shift can be emulated with the transform:
// M = lshr(SIGN_BIT, Amt) // M = lshr(SIGN_MASK, Amt)
// ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M) // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) && if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) &&
Op.getOpcode() == ISD::SRA) { Op.getOpcode() == ISD::SRA) {
SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT); SDValue S = DAG.getConstant(APInt::getSignMask(64), dl, VT);
SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt); SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
R = DAG.getNode(ISD::SRL, dl, VT, R, Amt); R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
R = DAG.getNode(ISD::XOR, dl, VT, R, M); R = DAG.getNode(ISD::XOR, dl, VT, R, M);
@ -30152,7 +30152,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// x s< 0 ? x^C : 0 --> subus x, C // x s< 0 ? x^C : 0 --> subus x, C
if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR && if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
ISD::isBuildVectorAllZeros(CondRHS.getNode()) && ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
OpRHSConst->getAPIntValue().isSignBit()) OpRHSConst->getAPIntValue().isSignMask())
// Note that we have to rebuild the RHS constant here to ensure we // Note that we have to rebuild the RHS constant here to ensure we
// don't rely on particular values of undef lanes. // don't rely on particular values of undef lanes.
return DAG.getNode( return DAG.getNode(
@ -30203,7 +30203,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
return SDValue(); return SDValue();
assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
APInt DemandedMask(APInt::getSignBit(BitWidth)); APInt DemandedMask(APInt::getSignMask(BitWidth));
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
DCI.isBeforeLegalizeOps()); DCI.isBeforeLegalizeOps());
@ -33428,8 +33428,8 @@ static SDValue isFNEG(SDNode *N) {
SDValue Op0 = peekThroughBitcasts(Op.getOperand(0)); SDValue Op0 = peekThroughBitcasts(Op.getOperand(0));
unsigned EltBits = Op1.getScalarValueSizeInBits(); unsigned EltBits = Op1.getScalarValueSizeInBits();
auto isSignBitValue = [&](const ConstantFP *C) { auto isSignMask = [&](const ConstantFP *C) {
return C->getValueAPF().bitcastToAPInt() == APInt::getSignBit(EltBits); return C->getValueAPF().bitcastToAPInt() == APInt::getSignMask(EltBits);
}; };
// There is more than one way to represent the same constant on // There is more than one way to represent the same constant on
@ -33440,21 +33440,21 @@ static SDValue isFNEG(SDNode *N) {
// We check all variants here. // We check all variants here.
if (Op1.getOpcode() == X86ISD::VBROADCAST) { if (Op1.getOpcode() == X86ISD::VBROADCAST) {
if (auto *C = getTargetConstantFromNode(Op1.getOperand(0))) if (auto *C = getTargetConstantFromNode(Op1.getOperand(0)))
if (isSignBitValue(cast<ConstantFP>(C))) if (isSignMask(cast<ConstantFP>(C)))
return Op0; return Op0;
} else if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1)) { } else if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1)) {
if (ConstantFPSDNode *CN = BV->getConstantFPSplatNode()) if (ConstantFPSDNode *CN = BV->getConstantFPSplatNode())
if (isSignBitValue(CN->getConstantFPValue())) if (isSignMask(CN->getConstantFPValue()))
return Op0; return Op0;
} else if (auto *C = getTargetConstantFromNode(Op1)) { } else if (auto *C = getTargetConstantFromNode(Op1)) {
if (C->getType()->isVectorTy()) { if (C->getType()->isVectorTy()) {
if (auto *SplatV = C->getSplatValue()) if (auto *SplatV = C->getSplatValue())
if (isSignBitValue(cast<ConstantFP>(SplatV))) if (isSignMask(cast<ConstantFP>(SplatV)))
return Op0; return Op0;
} else if (auto *FPConst = dyn_cast<ConstantFP>(C)) } else if (auto *FPConst = dyn_cast<ConstantFP>(C))
if (isSignBitValue(FPConst)) if (isSignMask(FPConst))
return Op0; return Op0;
} }
return SDValue(); return SDValue();

12
lib/Transforms/InstCombine/InstCombineAddSub.cpp
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@ -1044,14 +1044,14 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
const APInt *RHSC; const APInt *RHSC;
if (match(RHS, m_APInt(RHSC))) { if (match(RHS, m_APInt(RHSC))) {
if (RHSC->isSignBit()) { if (RHSC->isSignMask()) {
// If wrapping is not allowed, then the addition must set the sign bit: // If wrapping is not allowed, then the addition must set the sign bit:
// X + (signbit) --> X | signbit // X + (signmask) --> X | signmask
if (I.hasNoSignedWrap() || I.hasNoUnsignedWrap()) if (I.hasNoSignedWrap() || I.hasNoUnsignedWrap())
return BinaryOperator::CreateOr(LHS, RHS); return BinaryOperator::CreateOr(LHS, RHS);
// If wrapping is allowed, then the addition flips the sign bit of LHS: // If wrapping is allowed, then the addition flips the sign bit of LHS:
// X + (signbit) --> X ^ signbit // X + (signmask) --> X ^ signmask
return BinaryOperator::CreateXor(LHS, RHS); return BinaryOperator::CreateXor(LHS, RHS);
} }
@ -1120,9 +1120,9 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI), return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI),
XorLHS); XorLHS);
} }
// (X + signbit) + C could have gotten canonicalized to (X ^ signbit) + C, // (X + signmask) + C could have gotten canonicalized to (X^signmask) + C,
// transform them into (X + (signbit ^ C)) // transform them into (X + (signmask ^ C))
if (XorRHS->getValue().isSignBit()) if (XorRHS->getValue().isSignMask())
return BinaryOperator::CreateAdd(XorLHS, return BinaryOperator::CreateAdd(XorLHS,
ConstantExpr::getXor(XorRHS, CI)); ConstantExpr::getXor(XorRHS, CI));
} }

4
lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
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@ -2480,8 +2480,8 @@ Instruction *InstCombiner::visitXor(BinaryOperator &I) {
Constant *NegOp0CI = ConstantExpr::getNeg(Op0CI); Constant *NegOp0CI = ConstantExpr::getNeg(Op0CI);
return BinaryOperator::CreateSub(SubOne(NegOp0CI), return BinaryOperator::CreateSub(SubOne(NegOp0CI),
Op0I->getOperand(0)); Op0I->getOperand(0));
} else if (RHSC->getValue().isSignBit()) { } else if (RHSC->getValue().isSignMask()) {
// (X + C) ^ signbit -> (X + C + signbit) // (X + C) ^ signmask -> (X + C + signmask)
Constant *C = Builder->getInt(RHSC->getValue() + Op0CI->getValue()); Constant *C = Builder->getInt(RHSC->getValue() + Op0CI->getValue());
return BinaryOperator::CreateAdd(Op0I->getOperand(0), C); return BinaryOperator::CreateAdd(Op0I->getOperand(0), C);

20
lib/Transforms/InstCombine/InstCombineCompares.cpp
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@ -140,7 +140,7 @@ static bool isSignBitCheck(ICmpInst::Predicate Pred, const APInt &RHS,
case ICmpInst::ICMP_UGE: case ICmpInst::ICMP_UGE:
// True if LHS u>= RHS and RHS == high-bit-mask (2^7, 2^15, 2^31, etc) // True if LHS u>= RHS and RHS == high-bit-mask (2^7, 2^15, 2^31, etc)
TrueIfSigned = true; TrueIfSigned = true;
return RHS.isSignBit(); return RHS.isSignMask();
default: default:
return false; return false;
} }
@ -1532,14 +1532,14 @@ Instruction *InstCombiner::foldICmpXorConstant(ICmpInst &Cmp,
} }
if (Xor->hasOneUse()) { if (Xor->hasOneUse()) {
// (icmp u/s (xor X SignBit), C) -> (icmp s/u X, (xor C SignBit)) // (icmp u/s (xor X SignMask), C) -> (icmp s/u X, (xor C SignMask))
if (!Cmp.isEquality() && XorC->isSignBit()) { if (!Cmp.isEquality() && XorC->isSignMask()) {
Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate() Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate()
: Cmp.getSignedPredicate(); : Cmp.getSignedPredicate();
return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), *C ^ *XorC)); return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), *C ^ *XorC));
} }
// (icmp u/s (xor X ~SignBit), C) -> (icmp s/u X, (xor C ~SignBit)) // (icmp u/s (xor X ~SignMask), C) -> (icmp s/u X, (xor C ~SignMask))
if (!Cmp.isEquality() && XorC->isMaxSignedValue()) { if (!Cmp.isEquality() && XorC->isMaxSignedValue()) {
Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate() Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate()
: Cmp.getSignedPredicate(); : Cmp.getSignedPredicate();
@ -2402,9 +2402,9 @@ Instruction *InstCombiner::foldICmpAddConstant(ICmpInst &Cmp,
const APInt &Upper = CR.getUpper(); const APInt &Upper = CR.getUpper();
const APInt &Lower = CR.getLower(); const APInt &Lower = CR.getLower();
if (Cmp.isSigned()) { if (Cmp.isSigned()) {
if (Lower.isSignBit()) if (Lower.isSignMask())
return new ICmpInst(ICmpInst::ICMP_SLT, X, ConstantInt::get(Ty, Upper)); return new ICmpInst(ICmpInst::ICMP_SLT, X, ConstantInt::get(Ty, Upper));
if (Upper.isSignBit()) if (Upper.isSignMask())
return new ICmpInst(ICmpInst::ICMP_SGE, X, ConstantInt::get(Ty, Lower)); return new ICmpInst(ICmpInst::ICMP_SGE, X, ConstantInt::get(Ty, Lower));
} else { } else {
if (Lower.isMinValue()) if (Lower.isMinValue())
@ -2604,7 +2604,7 @@ Instruction *InstCombiner::foldICmpBinOpEqualityWithConstant(ICmpInst &Cmp,
break; break;
// Replace (and X, (1 << size(X)-1) != 0) with x s< 0 // Replace (and X, (1 << size(X)-1) != 0) with x s< 0
if (BOC->isSignBit()) { if (BOC->isSignMask()) {
Constant *Zero = Constant::getNullValue(BOp0->getType()); Constant *Zero = Constant::getNullValue(BOp0->getType());
auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE; auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE;
return new ICmpInst(NewPred, BOp0, Zero); return new ICmpInst(NewPred, BOp0, Zero);
@ -3032,9 +3032,9 @@ Instruction *InstCombiner::foldICmpBinOp(ICmpInst &I) {
if (I.isEquality()) // a+x icmp eq/ne b+x --> a icmp b if (I.isEquality()) // a+x icmp eq/ne b+x --> a icmp b
return new ICmpInst(I.getPredicate(), BO0->getOperand(0), return new ICmpInst(I.getPredicate(), BO0->getOperand(0),
BO1->getOperand(0)); BO1->getOperand(0));
// icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b // icmp u/s (a ^ signmask), (b ^ signmask) --> icmp s/u a, b
if (ConstantInt *CI = dyn_cast<ConstantInt>(BO0->getOperand(1))) { if (ConstantInt *CI = dyn_cast<ConstantInt>(BO0->getOperand(1))) {
if (CI->getValue().isSignBit()) { if (CI->getValue().isSignMask()) {
ICmpInst::Predicate Pred = ICmpInst::Predicate Pred =
I.isSigned() ? I.getUnsignedPredicate() : I.getSignedPredicate(); I.isSigned() ? I.getUnsignedPredicate() : I.getSignedPredicate();
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0)); return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
@ -3797,7 +3797,7 @@ static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal,
static APInt getDemandedBitsLHSMask(ICmpInst &I, unsigned BitWidth, static APInt getDemandedBitsLHSMask(ICmpInst &I, unsigned BitWidth,
bool isSignCheck) { bool isSignCheck) {
if (isSignCheck) if (isSignCheck)
return APInt::getSignBit(BitWidth); return APInt::getSignMask(BitWidth);
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
if (!CI) return APInt::getAllOnesValue(BitWidth); if (!CI) return APInt::getAllOnesValue(BitWidth);

4
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
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@ -1237,7 +1237,7 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
// If the sign bits of both operands are zero (i.e. we can prove they are // If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a udiv. // unsigned inputs), turn this into a udiv.
APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits())); APInt Mask(APInt::getSignMask(I.getType()->getScalarSizeInBits()));
if (MaskedValueIsZero(Op0, Mask, 0, &I)) { if (MaskedValueIsZero(Op0, Mask, 0, &I)) {
if (MaskedValueIsZero(Op1, Mask, 0, &I)) { if (MaskedValueIsZero(Op1, Mask, 0, &I)) {
// X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
@ -1543,7 +1543,7 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
// If the sign bits of both operands are zero (i.e. we can prove they are // If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a urem. // unsigned inputs), turn this into a urem.
APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits())); APInt Mask(APInt::getSignMask(I.getType()->getScalarSizeInBits()));
if (MaskedValueIsZero(Op1, Mask, 0, &I) && if (MaskedValueIsZero(Op1, Mask, 0, &I) &&
MaskedValueIsZero(Op0, Mask, 0, &I)) { MaskedValueIsZero(Op0, Mask, 0, &I)) {
// X srem Y -> X urem Y, iff X and Y don't have sign bit set // X srem Y -> X urem Y, iff X and Y don't have sign bit set

2
lib/Transforms/InstCombine/InstCombineSelect.cpp
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@ -618,7 +618,7 @@ Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI,
{ {
unsigned BitWidth = unsigned BitWidth =
DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); DL.getTypeSizeInBits(TrueVal->getType()->getScalarType());
APInt MinSignedValue = APInt::getSignBit(BitWidth); APInt MinSignedValue = APInt::getSignedMinValue(BitWidth);
Value *X; Value *X;
const APInt *Y, *C; const APInt *Y, *C;
bool TrueWhenUnset; bool TrueWhenUnset;

2
lib/Transforms/InstCombine/InstCombineShifts.cpp
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@ -760,7 +760,7 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) {
} }
// See if we can turn a signed shr into an unsigned shr. // See if we can turn a signed shr into an unsigned shr.
if (MaskedValueIsZero(Op0, APInt::getSignBit(BitWidth), 0, &I)) if (MaskedValueIsZero(Op0, APInt::getSignMask(BitWidth), 0, &I))
return BinaryOperator::CreateLShr(Op0, Op1); return BinaryOperator::CreateLShr(Op0, Op1);
return nullptr; return nullptr;

10
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -555,7 +555,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If the sign bit is the only bit demanded by this ashr, then there is no // If the sign bit is the only bit demanded by this ashr, then there is no
// need to do it, the shift doesn't change the high bit. // need to do it, the shift doesn't change the high bit.
if (DemandedMask.isSignBit()) if (DemandedMask.isSignMask())
return I->getOperand(0); return I->getOperand(0);
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
@ -583,9 +583,9 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
KnownOne.lshrInPlace(ShiftAmt); KnownOne.lshrInPlace(ShiftAmt);
// Handle the sign bits. // Handle the sign bits.
APInt SignBit(APInt::getSignBit(BitWidth)); APInt SignMask(APInt::getSignMask(BitWidth));
// Adjust to where it is now in the mask. // Adjust to where it is now in the mask.
SignBit.lshrInPlace(ShiftAmt); SignMask.lshrInPlace(ShiftAmt);
// If the input sign bit is known to be zero, or if none of the top bits // If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right. // are demanded, turn this into an unsigned shift right.
@ -596,7 +596,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
SA, I->getName()); SA, I->getName());
NewVal->setIsExact(cast<BinaryOperator>(I)->isExact()); NewVal->setIsExact(cast<BinaryOperator>(I)->isExact());
return InsertNewInstWith(NewVal, *I); return InsertNewInstWith(NewVal, *I);
} else if ((KnownOne & SignBit) != 0) { // New bits are known one. } else if ((KnownOne & SignMask) != 0) { // New bits are known one.
KnownOne |= HighBits; KnownOne |= HighBits;
} }
} }
@ -613,7 +613,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
return I->getOperand(0); return I->getOperand(0);
APInt LowBits = RA - 1; APInt LowBits = RA - 1;
APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); APInt Mask2 = LowBits | APInt::getSignMask(BitWidth);
if (SimplifyDemandedBits(I, 0, Mask2, LHSKnownZero, LHSKnownOne, if (SimplifyDemandedBits(I, 0, Mask2, LHSKnownZero, LHSKnownOne,
Depth + 1)) Depth + 1))
return I; return I;

8
lib/Transforms/Utils/CmpInstAnalysis.cpp
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@ -73,17 +73,17 @@ bool llvm::decomposeBitTestICmp(const ICmpInst *I, CmpInst::Predicate &Pred,
default: default:
return false; return false;
case ICmpInst::ICMP_SLT: case ICmpInst::ICMP_SLT:
// X < 0 is equivalent to (X & SignBit) != 0. // X < 0 is equivalent to (X & SignMask) != 0.
if (!C->isZero()) if (!C->isZero())
return false; return false;
Y = ConstantInt::get(I->getContext(), APInt::getSignBit(C->getBitWidth())); Y = ConstantInt::get(I->getContext(), APInt::getSignMask(C->getBitWidth()));
Pred = ICmpInst::ICMP_NE; Pred = ICmpInst::ICMP_NE;
break; break;
case ICmpInst::ICMP_SGT: case ICmpInst::ICMP_SGT:
// X > -1 is equivalent to (X & SignBit) == 0. // X > -1 is equivalent to (X & SignMask) == 0.
if (!C->isAllOnesValue()) if (!C->isAllOnesValue())
return false; return false;
Y = ConstantInt::get(I->getContext(), APInt::getSignBit(C->getBitWidth())); Y = ConstantInt::get(I->getContext(), APInt::getSignMask(C->getBitWidth()));
Pred = ICmpInst::ICMP_EQ; Pred = ICmpInst::ICMP_EQ;
break; break;
case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_ULT: