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[APInt] Rename getSignBit to getSignMask
getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask. Differential Revision: https://reviews.llvm.org/D32108 llvm-svn: 300856
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@ -416,10 +416,10 @@ public:
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return countPopulationSlowCase() == 1;
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}
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/// \brief Check if the APInt's value is returned by getSignBit.
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/// \brief Check if the APInt's value is returned by getSignMask.
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///
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/// \returns true if this is the value returned by getSignBit.
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bool isSignBit() const { return isMinSignedValue(); }
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/// \returns true if this is the value returned by getSignMask.
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bool isSignMask() const { return isMinSignedValue(); }
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/// \brief Convert APInt to a boolean value.
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///
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@ -497,11 +497,11 @@ public:
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return API;
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}
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/// \brief Get the SignBit for a specific bit width.
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/// \brief Get the SignMask for a specific bit width.
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///
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/// This is just a wrapper function of getSignedMinValue(), and it helps code
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/// readability when we want to get a SignBit.
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static APInt getSignBit(unsigned BitWidth) {
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/// readability when we want to get a SignMask.
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static APInt getSignMask(unsigned BitWidth) {
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return getSignedMinValue(BitWidth);
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}
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@ -267,15 +267,15 @@ inline cst_pred_ty<is_all_ones> m_AllOnes() {
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}
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inline api_pred_ty<is_all_ones> m_AllOnes(const APInt *&V) { return V; }
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struct is_sign_bit {
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bool isValue(const APInt &C) { return C.isSignBit(); }
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struct is_sign_mask {
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bool isValue(const APInt &C) { return C.isSignMask(); }
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};
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/// \brief Match an integer or vector with only the sign bit(s) set.
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inline cst_pred_ty<is_sign_bit> m_SignBit() {
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return cst_pred_ty<is_sign_bit>();
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inline cst_pred_ty<is_sign_mask> m_SignMask() {
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return cst_pred_ty<is_sign_mask>();
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}
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inline api_pred_ty<is_sign_bit> m_SignBit(const APInt *&V) { return V; }
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inline api_pred_ty<is_sign_mask> m_SignMask(const APInt *&V) { return V; }
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struct is_power2 {
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bool isValue(const APInt &C) { return C.isPowerOf2(); }
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@ -568,11 +568,11 @@ static Value *SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
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match(Op1, m_Not(m_Specific(Op0))))
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return Constant::getAllOnesValue(Ty);
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// add nsw/nuw (xor Y, signbit), signbit --> Y
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// add nsw/nuw (xor Y, signmask), signmask --> Y
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// The no-wrapping add guarantees that the top bit will be set by the add.
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// Therefore, the xor must be clearing the already set sign bit of Y.
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if ((isNSW || isNUW) && match(Op1, m_SignBit()) &&
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match(Op0, m_Xor(m_Value(Y), m_SignBit())))
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if ((isNSW || isNUW) && match(Op1, m_SignMask()) &&
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match(Op0, m_Xor(m_Value(Y), m_SignMask())))
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return Y;
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/// i1 add -> xor.
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@ -2819,7 +2819,7 @@ static Value *simplifyICmpWithBinOp(CmpInst::Predicate Pred, Value *LHS,
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return ConstantInt::getTrue(RHS->getContext());
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}
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}
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if (CIVal->isSignBit() && *CI2Val == 1) {
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if (CIVal->isSignMask() && *CI2Val == 1) {
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if (Pred == ICmpInst::ICMP_UGT)
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return ConstantInt::getFalse(RHS->getContext());
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if (Pred == ICmpInst::ICMP_ULE)
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@ -4007,9 +4007,9 @@ static Optional<BinaryOp> MatchBinaryOp(Value *V, DominatorTree &DT) {
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case Instruction::Xor:
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if (auto *RHSC = dyn_cast<ConstantInt>(Op->getOperand(1)))
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// If the RHS of the xor is a signbit, then this is just an add.
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// Instcombine turns add of signbit into xor as a strength reduction step.
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if (RHSC->getValue().isSignBit())
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// If the RHS of the xor is a signmask, then this is just an add.
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// Instcombine turns add of signmask into xor as a strength reduction step.
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if (RHSC->getValue().isSignMask())
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return BinaryOp(Instruction::Add, Op->getOperand(0), Op->getOperand(1));
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return BinaryOp(Op);
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@ -5369,7 +5369,7 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
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// using an add, which is equivalent, and re-apply the zext.
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APInt Trunc = CI->getValue().trunc(Z0TySize);
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if (Trunc.zext(getTypeSizeInBits(UTy)) == CI->getValue() &&
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Trunc.isSignBit())
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Trunc.isSignMask())
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return getZeroExtendExpr(getAddExpr(Z0, getConstant(Trunc)),
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UTy);
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}
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@ -1640,9 +1640,9 @@ bool isKnownToBeAPowerOfTwo(const Value *V, bool OrZero, unsigned Depth,
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if (match(V, m_Shl(m_One(), m_Value())))
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return true;
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// (signbit) >>l X is clearly a power of two if the one is not shifted off the
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// bottom. If it is shifted off the bottom then the result is undefined.
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if (match(V, m_LShr(m_SignBit(), m_Value())))
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// (signmask) >>l X is clearly a power of two if the one is not shifted off
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// the bottom. If it is shifted off the bottom then the result is undefined.
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if (match(V, m_LShr(m_SignMask(), m_Value())))
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return true;
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// The remaining tests are all recursive, so bail out if we hit the limit.
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@ -2146,7 +2146,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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if (N->getFlags()->hasNoUnsignedWrap())
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return N0;
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if (DAG.MaskedValueIsZero(N1, ~APInt::getSignBit(BitWidth))) {
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if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
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// N1 is either 0 or the minimum signed value. If the sub is NSW, then
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// N1 must be 0 because negating the minimum signed value is undefined.
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if (N->getFlags()->hasNoSignedWrap())
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@ -8298,11 +8298,11 @@ static SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG,
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switch (N0.getOpcode()) {
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case ISD::AND:
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FPOpcode = ISD::FABS;
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SignMask = ~APInt::getSignBit(SourceVT.getSizeInBits());
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SignMask = ~APInt::getSignMask(SourceVT.getSizeInBits());
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break;
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case ISD::XOR:
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FPOpcode = ISD::FNEG;
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SignMask = APInt::getSignBit(SourceVT.getSizeInBits());
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SignMask = APInt::getSignMask(SourceVT.getSizeInBits());
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break;
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// TODO: ISD::OR --> ISD::FNABS?
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default:
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@ -8413,7 +8413,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
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assert(VT.getSizeInBits() == 128);
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SDValue SignBit = DAG.getConstant(
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APInt::getSignBit(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64);
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APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64);
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SDValue FlipBit;
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if (N0.getOpcode() == ISD::FNEG) {
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FlipBit = SignBit;
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@ -8433,7 +8433,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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AddToWorklist(FlipBits.getNode());
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return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits);
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}
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
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APInt SignBit = APInt::getSignMask(VT.getSizeInBits());
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if (N0.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::XOR, DL, VT,
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NewConv, DAG.getConstant(SignBit, DL, VT));
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@ -8481,7 +8481,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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}
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if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits() / 2);
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APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2);
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SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));
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AddToWorklist(Cst.getNode());
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SDValue X = DAG.getBitcast(VT, N0.getOperand(1));
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@ -8502,7 +8502,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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AddToWorklist(FlipBits.getNode());
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return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits);
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}
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
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APInt SignBit = APInt::getSignMask(VT.getSizeInBits());
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X = DAG.getNode(ISD::AND, SDLoc(X), VT,
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X, DAG.getConstant(SignBit, SDLoc(X), VT));
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AddToWorklist(X.getNode());
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@ -10313,11 +10313,11 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
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if (N0.getValueType().isVector()) {
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// For a vector, get a mask such as 0x80... per scalar element
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// and splat it.
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SignMask = APInt::getSignBit(N0.getScalarValueSizeInBits());
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SignMask = APInt::getSignMask(N0.getScalarValueSizeInBits());
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SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
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} else {
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// For a scalar, just generate 0x80...
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SignMask = APInt::getSignBit(IntVT.getSizeInBits());
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SignMask = APInt::getSignMask(IntVT.getSizeInBits());
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}
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SDLoc DL0(N0);
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Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int,
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@ -10418,11 +10418,11 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
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if (N0.getValueType().isVector()) {
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// For a vector, get a mask such as 0x7f... per scalar element
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// and splat it.
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SignMask = ~APInt::getSignBit(N0.getScalarValueSizeInBits());
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SignMask = ~APInt::getSignMask(N0.getScalarValueSizeInBits());
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SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
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} else {
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// For a scalar, just generate 0x7f...
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SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
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SignMask = ~APInt::getSignMask(IntVT.getSizeInBits());
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}
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SDLoc DL(N0);
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Int = DAG.getNode(ISD::AND, DL, IntVT, Int,
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@ -1343,7 +1343,7 @@ void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
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// Convert to an integer of the same size.
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if (TLI.isTypeLegal(IVT)) {
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State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
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State.SignMask = APInt::getSignBit(NumBits);
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State.SignMask = APInt::getSignMask(NumBits);
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State.SignBit = NumBits - 1;
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return;
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}
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@ -2984,7 +2984,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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EVT NVT = Node->getValueType(0);
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APFloat apf(DAG.EVTToAPFloatSemantics(VT),
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APInt::getNullValue(VT.getSizeInBits()));
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APInt x = APInt::getSignBit(NVT.getSizeInBits());
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APInt x = APInt::getSignMask(NVT.getSizeInBits());
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(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
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Tmp1 = DAG.getConstantFP(apf, dl, VT);
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Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
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@ -1955,7 +1955,7 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
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/// use this predicate to simplify operations downstream.
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bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
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unsigned BitWidth = Op.getScalarValueSizeInBits();
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return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
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return MaskedValueIsZero(Op, APInt::getSignMask(BitWidth), Depth);
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}
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/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
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@ -2344,11 +2344,11 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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KnownOne.lshrInPlace(*ShAmt);
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// If we know the value of the sign bit, then we know it is copied across
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// the high bits by the shift amount.
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APInt SignBit = APInt::getSignBit(BitWidth);
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SignBit.lshrInPlace(*ShAmt); // Adjust to where it is now in the mask.
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if (KnownZero.intersects(SignBit)) {
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APInt SignMask = APInt::getSignMask(BitWidth);
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SignMask.lshrInPlace(*ShAmt); // Adjust to where it is now in the mask.
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if (KnownZero.intersects(SignMask)) {
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KnownZero.setHighBits(ShAmt->getZExtValue());// New bits are known zero.
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} else if (KnownOne.intersects(SignBit)) {
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} else if (KnownOne.intersects(SignMask)) {
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KnownOne.setHighBits(ShAmt->getZExtValue()); // New bits are known one.
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}
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}
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@ -2361,14 +2361,14 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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// present in the input.
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APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits);
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APInt InSignBit = APInt::getSignBit(EBits);
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APInt InSignMask = APInt::getSignMask(EBits);
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APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, EBits);
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// If the sign extended bits are demanded, we know that the sign
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// bit is demanded.
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InSignBit = InSignBit.zext(BitWidth);
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InSignMask = InSignMask.zext(BitWidth);
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if (NewBits.getBoolValue())
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InputDemandedBits |= InSignBit;
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InputDemandedBits |= InSignMask;
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computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
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Depth + 1);
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@ -2377,10 +2377,10 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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// If the sign bit of the input is known set or clear, then we know the
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// top bits of the result.
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if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear
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if (KnownZero.intersects(InSignMask)) { // Input sign bit known clear
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KnownZero |= NewBits;
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KnownOne &= ~NewBits;
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} else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
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} else if (KnownOne.intersects(InSignMask)) { // Input sign bit known set
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KnownOne |= NewBits;
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KnownZero &= ~NewBits;
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} else { // Input sign bit unknown
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@ -2745,7 +2745,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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// a set bit that isn't the sign bit (otherwise it could be INT_MIN).
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KnownOne2.clearBit(BitWidth - 1);
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if (KnownOne2.getBoolValue()) {
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KnownZero = APInt::getSignBit(BitWidth);
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KnownZero = APInt::getSignMask(BitWidth);
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break;
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}
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break;
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@ -2874,7 +2874,7 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val) const {
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// one bit set.
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if (Val.getOpcode() == ISD::SRL) {
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auto *C = dyn_cast<ConstantSDNode>(Val.getOperand(0));
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if (C && C->getAPIntValue().isSignBit())
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if (C && C->getAPIntValue().isSignMask())
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return true;
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}
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@ -778,7 +778,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// If (1) we only need the sign-bit, (2) the setcc operands are the same
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// width as the setcc result, and (3) the result of a setcc conforms to 0 or
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// -1, we may be able to bypass the setcc.
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if (NewMask.isSignBit() && Op0.getScalarValueSizeInBits() == BitWidth &&
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if (NewMask.isSignMask() && Op0.getScalarValueSizeInBits() == BitWidth &&
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getBooleanContents(Op.getValueType()) ==
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BooleanContent::ZeroOrNegativeOneBooleanContent) {
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// If we're testing X < 0, then this compare isn't needed - just use X!
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@ -964,7 +964,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// demand the input sign bit.
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APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
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if (HighBits.intersects(NewMask))
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InDemandedMask |= APInt::getSignBit(VT.getScalarSizeInBits());
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InDemandedMask |= APInt::getSignMask(VT.getScalarSizeInBits());
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if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
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KnownZero, KnownOne, TLO, Depth+1))
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@ -974,11 +974,11 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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KnownOne.lshrInPlace(ShAmt);
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// Handle the sign bit, adjusted to where it is now in the mask.
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APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
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APInt SignMask = APInt::getSignMask(BitWidth).lshr(ShAmt);
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// If the input sign bit is known to be zero, or if none of the top bits
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// are demanded, turn this into an unsigned shift right.
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if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
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if (KnownZero.intersects(SignMask) || (HighBits & ~NewMask) == HighBits) {
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SDNodeFlags Flags;
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Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
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return TLO.CombineTo(Op,
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@ -996,7 +996,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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Op.getOperand(0), NewSA));
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}
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if (KnownOne.intersects(SignBit))
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if (KnownOne.intersects(SignMask))
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// New bits are known one.
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KnownOne |= HighBits;
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}
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@ -1040,7 +1040,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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return TLO.CombineTo(Op, Op.getOperand(0));
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APInt InSignBit =
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APInt::getSignBit(ExVT.getScalarSizeInBits()).zext(BitWidth);
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APInt::getSignMask(ExVT.getScalarSizeInBits()).zext(BitWidth);
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APInt InputDemandedBits =
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APInt::getLowBitsSet(BitWidth,
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ExVT.getScalarSizeInBits()) &
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@ -1250,7 +1250,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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if (!TLO.LegalOperations() &&
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!Op.getValueType().isVector() &&
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!Op.getOperand(0).getValueType().isVector() &&
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NewMask == APInt::getSignBit(Op.getValueSizeInBits()) &&
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NewMask == APInt::getSignMask(Op.getValueSizeInBits()) &&
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Op.getOperand(0).getValueType().isFloatingPoint()) {
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bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
|
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bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
|
||||
@ -3356,7 +3356,7 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
|
||||
SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
|
||||
SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
|
||||
SDValue Bias = DAG.getConstant(127, dl, IntVT);
|
||||
SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
|
||||
SDValue SignMask = DAG.getConstant(APInt::getSignMask(VT.getSizeInBits()), dl,
|
||||
IntVT);
|
||||
SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
|
||||
SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
|
||||
|
@ -16069,7 +16069,7 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
|
||||
unsigned EltBits = EltVT.getSizeInBits();
|
||||
// For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
|
||||
APInt MaskElt =
|
||||
IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
|
||||
IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignMask(EltBits);
|
||||
const fltSemantics &Sem =
|
||||
EltVT == MVT::f64 ? APFloat::IEEEdouble() :
|
||||
(IsF128 ? APFloat::IEEEquad() : APFloat::IEEEsingle());
|
||||
@ -16132,9 +16132,9 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
|
||||
// The mask constants are automatically splatted for vector types.
|
||||
unsigned EltSizeInBits = VT.getScalarSizeInBits();
|
||||
SDValue SignMask = DAG.getConstantFP(
|
||||
APFloat(Sem, APInt::getSignBit(EltSizeInBits)), dl, LogicVT);
|
||||
APFloat(Sem, APInt::getSignMask(EltSizeInBits)), dl, LogicVT);
|
||||
SDValue MagMask = DAG.getConstantFP(
|
||||
APFloat(Sem, ~APInt::getSignBit(EltSizeInBits)), dl, LogicVT);
|
||||
APFloat(Sem, ~APInt::getSignMask(EltSizeInBits)), dl, LogicVT);
|
||||
|
||||
// First, clear all bits but the sign bit from the second operand (sign).
|
||||
if (IsFakeVector)
|
||||
@ -17344,10 +17344,10 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
|
||||
// bits of the inputs before performing those operations.
|
||||
if (FlipSigns) {
|
||||
MVT EltVT = VT.getVectorElementType();
|
||||
SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
|
||||
SDValue SM = DAG.getConstant(APInt::getSignMask(EltVT.getSizeInBits()), dl,
|
||||
VT);
|
||||
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
|
||||
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
|
||||
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SM);
|
||||
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SM);
|
||||
}
|
||||
|
||||
SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
|
||||
@ -22111,11 +22111,11 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
|
||||
}
|
||||
|
||||
// i64 vector arithmetic shift can be emulated with the transform:
|
||||
// M = lshr(SIGN_BIT, Amt)
|
||||
// M = lshr(SIGN_MASK, Amt)
|
||||
// ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
|
||||
if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) &&
|
||||
Op.getOpcode() == ISD::SRA) {
|
||||
SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
|
||||
SDValue S = DAG.getConstant(APInt::getSignMask(64), dl, VT);
|
||||
SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
|
||||
R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
|
||||
R = DAG.getNode(ISD::XOR, dl, VT, R, M);
|
||||
@ -30152,7 +30152,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
|
||||
// x s< 0 ? x^C : 0 --> subus x, C
|
||||
if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
|
||||
ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
|
||||
OpRHSConst->getAPIntValue().isSignBit())
|
||||
OpRHSConst->getAPIntValue().isSignMask())
|
||||
// Note that we have to rebuild the RHS constant here to ensure we
|
||||
// don't rely on particular values of undef lanes.
|
||||
return DAG.getNode(
|
||||
@ -30203,7 +30203,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
|
||||
assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
|
||||
APInt DemandedMask(APInt::getSignBit(BitWidth));
|
||||
APInt DemandedMask(APInt::getSignMask(BitWidth));
|
||||
APInt KnownZero, KnownOne;
|
||||
TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
|
||||
DCI.isBeforeLegalizeOps());
|
||||
@ -33428,8 +33428,8 @@ static SDValue isFNEG(SDNode *N) {
|
||||
SDValue Op0 = peekThroughBitcasts(Op.getOperand(0));
|
||||
|
||||
unsigned EltBits = Op1.getScalarValueSizeInBits();
|
||||
auto isSignBitValue = [&](const ConstantFP *C) {
|
||||
return C->getValueAPF().bitcastToAPInt() == APInt::getSignBit(EltBits);
|
||||
auto isSignMask = [&](const ConstantFP *C) {
|
||||
return C->getValueAPF().bitcastToAPInt() == APInt::getSignMask(EltBits);
|
||||
};
|
||||
|
||||
// There is more than one way to represent the same constant on
|
||||
@ -33440,21 +33440,21 @@ static SDValue isFNEG(SDNode *N) {
|
||||
// We check all variants here.
|
||||
if (Op1.getOpcode() == X86ISD::VBROADCAST) {
|
||||
if (auto *C = getTargetConstantFromNode(Op1.getOperand(0)))
|
||||
if (isSignBitValue(cast<ConstantFP>(C)))
|
||||
if (isSignMask(cast<ConstantFP>(C)))
|
||||
return Op0;
|
||||
|
||||
} else if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1)) {
|
||||
if (ConstantFPSDNode *CN = BV->getConstantFPSplatNode())
|
||||
if (isSignBitValue(CN->getConstantFPValue()))
|
||||
if (isSignMask(CN->getConstantFPValue()))
|
||||
return Op0;
|
||||
|
||||
} else if (auto *C = getTargetConstantFromNode(Op1)) {
|
||||
if (C->getType()->isVectorTy()) {
|
||||
if (auto *SplatV = C->getSplatValue())
|
||||
if (isSignBitValue(cast<ConstantFP>(SplatV)))
|
||||
if (isSignMask(cast<ConstantFP>(SplatV)))
|
||||
return Op0;
|
||||
} else if (auto *FPConst = dyn_cast<ConstantFP>(C))
|
||||
if (isSignBitValue(FPConst))
|
||||
if (isSignMask(FPConst))
|
||||
return Op0;
|
||||
}
|
||||
return SDValue();
|
||||
|
@ -1044,14 +1044,14 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
|
||||
|
||||
const APInt *RHSC;
|
||||
if (match(RHS, m_APInt(RHSC))) {
|
||||
if (RHSC->isSignBit()) {
|
||||
if (RHSC->isSignMask()) {
|
||||
// If wrapping is not allowed, then the addition must set the sign bit:
|
||||
// X + (signbit) --> X | signbit
|
||||
// X + (signmask) --> X | signmask
|
||||
if (I.hasNoSignedWrap() || I.hasNoUnsignedWrap())
|
||||
return BinaryOperator::CreateOr(LHS, RHS);
|
||||
|
||||
// If wrapping is allowed, then the addition flips the sign bit of LHS:
|
||||
// X + (signbit) --> X ^ signbit
|
||||
// X + (signmask) --> X ^ signmask
|
||||
return BinaryOperator::CreateXor(LHS, RHS);
|
||||
}
|
||||
|
||||
@ -1120,9 +1120,9 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
|
||||
return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI),
|
||||
XorLHS);
|
||||
}
|
||||
// (X + signbit) + C could have gotten canonicalized to (X ^ signbit) + C,
|
||||
// transform them into (X + (signbit ^ C))
|
||||
if (XorRHS->getValue().isSignBit())
|
||||
// (X + signmask) + C could have gotten canonicalized to (X^signmask) + C,
|
||||
// transform them into (X + (signmask ^ C))
|
||||
if (XorRHS->getValue().isSignMask())
|
||||
return BinaryOperator::CreateAdd(XorLHS,
|
||||
ConstantExpr::getXor(XorRHS, CI));
|
||||
}
|
||||
|
@ -2480,8 +2480,8 @@ Instruction *InstCombiner::visitXor(BinaryOperator &I) {
|
||||
Constant *NegOp0CI = ConstantExpr::getNeg(Op0CI);
|
||||
return BinaryOperator::CreateSub(SubOne(NegOp0CI),
|
||||
Op0I->getOperand(0));
|
||||
} else if (RHSC->getValue().isSignBit()) {
|
||||
// (X + C) ^ signbit -> (X + C + signbit)
|
||||
} else if (RHSC->getValue().isSignMask()) {
|
||||
// (X + C) ^ signmask -> (X + C + signmask)
|
||||
Constant *C = Builder->getInt(RHSC->getValue() + Op0CI->getValue());
|
||||
return BinaryOperator::CreateAdd(Op0I->getOperand(0), C);
|
||||
|
||||
|
@ -140,7 +140,7 @@ static bool isSignBitCheck(ICmpInst::Predicate Pred, const APInt &RHS,
|
||||
case ICmpInst::ICMP_UGE:
|
||||
// True if LHS u>= RHS and RHS == high-bit-mask (2^7, 2^15, 2^31, etc)
|
||||
TrueIfSigned = true;
|
||||
return RHS.isSignBit();
|
||||
return RHS.isSignMask();
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
@ -1532,14 +1532,14 @@ Instruction *InstCombiner::foldICmpXorConstant(ICmpInst &Cmp,
|
||||
}
|
||||
|
||||
if (Xor->hasOneUse()) {
|
||||
// (icmp u/s (xor X SignBit), C) -> (icmp s/u X, (xor C SignBit))
|
||||
if (!Cmp.isEquality() && XorC->isSignBit()) {
|
||||
// (icmp u/s (xor X SignMask), C) -> (icmp s/u X, (xor C SignMask))
|
||||
if (!Cmp.isEquality() && XorC->isSignMask()) {
|
||||
Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate()
|
||||
: Cmp.getSignedPredicate();
|
||||
return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), *C ^ *XorC));
|
||||
}
|
||||
|
||||
// (icmp u/s (xor X ~SignBit), C) -> (icmp s/u X, (xor C ~SignBit))
|
||||
// (icmp u/s (xor X ~SignMask), C) -> (icmp s/u X, (xor C ~SignMask))
|
||||
if (!Cmp.isEquality() && XorC->isMaxSignedValue()) {
|
||||
Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate()
|
||||
: Cmp.getSignedPredicate();
|
||||
@ -2402,9 +2402,9 @@ Instruction *InstCombiner::foldICmpAddConstant(ICmpInst &Cmp,
|
||||
const APInt &Upper = CR.getUpper();
|
||||
const APInt &Lower = CR.getLower();
|
||||
if (Cmp.isSigned()) {
|
||||
if (Lower.isSignBit())
|
||||
if (Lower.isSignMask())
|
||||
return new ICmpInst(ICmpInst::ICMP_SLT, X, ConstantInt::get(Ty, Upper));
|
||||
if (Upper.isSignBit())
|
||||
if (Upper.isSignMask())
|
||||
return new ICmpInst(ICmpInst::ICMP_SGE, X, ConstantInt::get(Ty, Lower));
|
||||
} else {
|
||||
if (Lower.isMinValue())
|
||||
@ -2604,7 +2604,7 @@ Instruction *InstCombiner::foldICmpBinOpEqualityWithConstant(ICmpInst &Cmp,
|
||||
break;
|
||||
|
||||
// Replace (and X, (1 << size(X)-1) != 0) with x s< 0
|
||||
if (BOC->isSignBit()) {
|
||||
if (BOC->isSignMask()) {
|
||||
Constant *Zero = Constant::getNullValue(BOp0->getType());
|
||||
auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE;
|
||||
return new ICmpInst(NewPred, BOp0, Zero);
|
||||
@ -3032,9 +3032,9 @@ Instruction *InstCombiner::foldICmpBinOp(ICmpInst &I) {
|
||||
if (I.isEquality()) // a+x icmp eq/ne b+x --> a icmp b
|
||||
return new ICmpInst(I.getPredicate(), BO0->getOperand(0),
|
||||
BO1->getOperand(0));
|
||||
// icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b
|
||||
// icmp u/s (a ^ signmask), (b ^ signmask) --> icmp s/u a, b
|
||||
if (ConstantInt *CI = dyn_cast<ConstantInt>(BO0->getOperand(1))) {
|
||||
if (CI->getValue().isSignBit()) {
|
||||
if (CI->getValue().isSignMask()) {
|
||||
ICmpInst::Predicate Pred =
|
||||
I.isSigned() ? I.getUnsignedPredicate() : I.getSignedPredicate();
|
||||
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
|
||||
@ -3797,7 +3797,7 @@ static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal,
|
||||
static APInt getDemandedBitsLHSMask(ICmpInst &I, unsigned BitWidth,
|
||||
bool isSignCheck) {
|
||||
if (isSignCheck)
|
||||
return APInt::getSignBit(BitWidth);
|
||||
return APInt::getSignMask(BitWidth);
|
||||
|
||||
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
|
||||
if (!CI) return APInt::getAllOnesValue(BitWidth);
|
||||
|
@ -1237,7 +1237,7 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
|
||||
|
||||
// If the sign bits of both operands are zero (i.e. we can prove they are
|
||||
// unsigned inputs), turn this into a udiv.
|
||||
APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits()));
|
||||
APInt Mask(APInt::getSignMask(I.getType()->getScalarSizeInBits()));
|
||||
if (MaskedValueIsZero(Op0, Mask, 0, &I)) {
|
||||
if (MaskedValueIsZero(Op1, Mask, 0, &I)) {
|
||||
// X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
|
||||
@ -1543,7 +1543,7 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
|
||||
|
||||
// If the sign bits of both operands are zero (i.e. we can prove they are
|
||||
// unsigned inputs), turn this into a urem.
|
||||
APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits()));
|
||||
APInt Mask(APInt::getSignMask(I.getType()->getScalarSizeInBits()));
|
||||
if (MaskedValueIsZero(Op1, Mask, 0, &I) &&
|
||||
MaskedValueIsZero(Op0, Mask, 0, &I)) {
|
||||
// X srem Y -> X urem Y, iff X and Y don't have sign bit set
|
||||
|
@ -618,7 +618,7 @@ Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI,
|
||||
{
|
||||
unsigned BitWidth =
|
||||
DL.getTypeSizeInBits(TrueVal->getType()->getScalarType());
|
||||
APInt MinSignedValue = APInt::getSignBit(BitWidth);
|
||||
APInt MinSignedValue = APInt::getSignedMinValue(BitWidth);
|
||||
Value *X;
|
||||
const APInt *Y, *C;
|
||||
bool TrueWhenUnset;
|
||||
|
@ -760,7 +760,7 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) {
|
||||
}
|
||||
|
||||
// See if we can turn a signed shr into an unsigned shr.
|
||||
if (MaskedValueIsZero(Op0, APInt::getSignBit(BitWidth), 0, &I))
|
||||
if (MaskedValueIsZero(Op0, APInt::getSignMask(BitWidth), 0, &I))
|
||||
return BinaryOperator::CreateLShr(Op0, Op1);
|
||||
|
||||
return nullptr;
|
||||
|
@ -555,7 +555,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
|
||||
|
||||
// If the sign bit is the only bit demanded by this ashr, then there is no
|
||||
// need to do it, the shift doesn't change the high bit.
|
||||
if (DemandedMask.isSignBit())
|
||||
if (DemandedMask.isSignMask())
|
||||
return I->getOperand(0);
|
||||
|
||||
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
|
||||
@ -583,9 +583,9 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
|
||||
KnownOne.lshrInPlace(ShiftAmt);
|
||||
|
||||
// Handle the sign bits.
|
||||
APInt SignBit(APInt::getSignBit(BitWidth));
|
||||
APInt SignMask(APInt::getSignMask(BitWidth));
|
||||
// Adjust to where it is now in the mask.
|
||||
SignBit.lshrInPlace(ShiftAmt);
|
||||
SignMask.lshrInPlace(ShiftAmt);
|
||||
|
||||
// If the input sign bit is known to be zero, or if none of the top bits
|
||||
// are demanded, turn this into an unsigned shift right.
|
||||
@ -596,7 +596,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
|
||||
SA, I->getName());
|
||||
NewVal->setIsExact(cast<BinaryOperator>(I)->isExact());
|
||||
return InsertNewInstWith(NewVal, *I);
|
||||
} else if ((KnownOne & SignBit) != 0) { // New bits are known one.
|
||||
} else if ((KnownOne & SignMask) != 0) { // New bits are known one.
|
||||
KnownOne |= HighBits;
|
||||
}
|
||||
}
|
||||
@ -613,7 +613,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
|
||||
return I->getOperand(0);
|
||||
|
||||
APInt LowBits = RA - 1;
|
||||
APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
|
||||
APInt Mask2 = LowBits | APInt::getSignMask(BitWidth);
|
||||
if (SimplifyDemandedBits(I, 0, Mask2, LHSKnownZero, LHSKnownOne,
|
||||
Depth + 1))
|
||||
return I;
|
||||
|
@ -73,17 +73,17 @@ bool llvm::decomposeBitTestICmp(const ICmpInst *I, CmpInst::Predicate &Pred,
|
||||
default:
|
||||
return false;
|
||||
case ICmpInst::ICMP_SLT:
|
||||
// X < 0 is equivalent to (X & SignBit) != 0.
|
||||
// X < 0 is equivalent to (X & SignMask) != 0.
|
||||
if (!C->isZero())
|
||||
return false;
|
||||
Y = ConstantInt::get(I->getContext(), APInt::getSignBit(C->getBitWidth()));
|
||||
Y = ConstantInt::get(I->getContext(), APInt::getSignMask(C->getBitWidth()));
|
||||
Pred = ICmpInst::ICMP_NE;
|
||||
break;
|
||||
case ICmpInst::ICMP_SGT:
|
||||
// X > -1 is equivalent to (X & SignBit) == 0.
|
||||
// X > -1 is equivalent to (X & SignMask) == 0.
|
||||
if (!C->isAllOnesValue())
|
||||
return false;
|
||||
Y = ConstantInt::get(I->getContext(), APInt::getSignBit(C->getBitWidth()));
|
||||
Y = ConstantInt::get(I->getContext(), APInt::getSignMask(C->getBitWidth()));
|
||||
Pred = ICmpInst::ICMP_EQ;
|
||||
break;
|
||||
case ICmpInst::ICMP_ULT:
|
||||
|
Loading…
Reference in New Issue
Block a user