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Add correct NEON encoding for vpadal.
llvm-svn: 117380
This commit is contained in:
Owen Anderson
parent
adaf2ea5c6
commit
d8e5d26a56
@ -1659,17 +1659,17 @@ class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
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(outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
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OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
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[(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
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(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
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OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
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[(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
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class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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bits<2> op17_16, bits<5> op11_7, bit op4,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
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(outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
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OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
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[(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
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(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
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OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
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[(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
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// Shift by immediate,
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// both double- and quad-register.
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@ -153,3 +153,127 @@ define <2 x i64> @vpaddlu_4xi32(<4 x i32>* %A) nounwind {
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
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; CHECK: vpadals_8xi8
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define <4 x i16> @vpadals_8xi8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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; CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xf3]
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
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ret <4 x i16> %tmp3
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}
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; CHECK: vpadals_4xi16
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define <2 x i32> @vpadals_4xi16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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; CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xf3]
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
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ret <2 x i32> %tmp3
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}
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; CHECK: vpadals_2xi32
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define <1 x i64> @vpadals_2xi32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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; CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xf3]
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%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
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ret <1 x i64> %tmp3
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}
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declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
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; CHECK: vpadalu_8xi8
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define <4 x i16> @vpadalu_8xi8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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; CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xf3]
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
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ret <4 x i16> %tmp3
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}
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; CHECK: vpadalu_4xi16
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define <2 x i32> @vpadalu_4xi16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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; CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xf3]
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
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ret <2 x i32> %tmp3
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}
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; CHECK: vpadalu_2xi32
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define <1 x i64> @vpadalu_2xi32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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; CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xf3]
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%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
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ret <1 x i64> %tmp3
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}
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declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
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; CHECK: vpadals_16xi8
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define <8 x i16> @vpadals_16xi8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <16 x i8>* %B
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; CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xf3]
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%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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; CHECK: vpadals_8xi16
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define <4 x i32> @vpadals_8xi16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <8 x i16>* %B
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; CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xf3]
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%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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; CHECK: vpadals_4xi32
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define <2 x i64> @vpadals_4xi32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <4 x i32>* %B
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; CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xf3]
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%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
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; CHECK: vpadalu_16xi8
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define <8 x i16> @vpadalu_16xi8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <16 x i8>* %B
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; CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xf3]
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%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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; CHECK: vpadalu_8xi16
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define <4 x i32> @vpadalu_8xi16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <8 x i16>* %B
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; CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xf3]
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%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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; CHECK: vpadalu_4xi32
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define <2 x i64> @vpadalu_4xi32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <4 x i32>* %B
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; CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xf3]
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%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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