RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Code Issues Projects Releases Wiki Activity

[Hexagon] Adding packhl instruction.

Browse Source 
llvm-svn: 223664
This commit is contained in:
Colin LeMahieu 2014-12-08 17:01:18 +00:00
parent c4ec7823fb
commit d90979b168
2 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -204,6 +204,12 @@ def: BinOp32_pat<or, A2_or, i32>;
def: BinOp32_pat<sub, A2_sub, i32>;
def: BinOp32_pat<xor, A2_xor, i32>;
// A few special cases producing register pairs:
let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
isCodeGenOnly = 0 in {
def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
}
let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
: ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),

2
test/MC/Disassembler/Hexagon/alu32_perm.txt
View File

@ -22,3 +22,5 @@
# CHECK: r17 = aslh(r21)
0x11 0xc0 0x35 0x70
# CHECK: r17 = asrh(r21)
0x10 0xdf 0x95 0xf5
# CHECK: r17:16 = packhl(r21, r31)