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PostRA Machine Sink should take care of COPY defining register that is a sub-register by another COPY source operand

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Differential Revision: https://reviews.llvm.org/D71132
This commit is contained in:
alex-t 2019-12-17 15:20:32 +03:00
parent b3c0f220c7
commit d91d119f17
4 changed files with 46 additions and 11 deletions
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10
lib/CodeGen/MachineSink.cpp
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@ -1215,10 +1215,14 @@ static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
SuccBB->removeLiveIn(*S);
for (auto U : UsedOpsInCopy) {
Register Reg = MI->getOperand(U).getReg();
if (!SuccBB->isLiveIn(Reg))
SuccBB->addLiveIn(Reg);
Register SrcReg = MI->getOperand(U).getReg();
LaneBitmask Mask;
for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) {
Mask |= (*S).second;
}
SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());
}
SuccBB->sortUniqueLiveIns();
}
static bool hasRegisterDependency(MachineInstr *MI,

2
test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
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@ -9,7 +9,7 @@
# RUN-POSTRA: bb.0:
# RUN-POSTRA-NOT: $w19 = COPY killed $w0
# RUN-POSTRA: bb.1:
# RUN-POSTRA: liveins: $w1, $w0
# RUN-POSTRA: liveins: $w0, $w1
# RUN-POSTRA: renamable $w19 = COPY killed $w0
# Make sure the pass it not run.

14
test/CodeGen/AArch64/post-ra-machine-sink.mir
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@ -6,7 +6,7 @@
# CHECK-LABEL: bb.0:
# CHECK-NOT: $w19 = COPY killed $w0
# CHECK-LABEL: bb.1:
# CHECK: liveins: $w1, $w0
# CHECK: liveins: $w0, $w1
# CHECK: renamable $w19 = COPY killed $w0
name: sinkcopy1
@ -35,7 +35,7 @@ body: |
# CHECK-LABEL: bb.0:
# CHECK-NOT: renamable $w19 = COPY killed $w0
# CHECK-LABEL: bb.2:
# CHECK: liveins: $w1, $w0
# CHECK: liveins: $w0, $w1
# CHECK: renamable $w19 = COPY killed $w0
name: sinkcopy2
tracksRegLiveness: true
@ -63,7 +63,7 @@ body: |
# CHECK-LABEL: bb.0:
# CHECK-NOT: renamable $w19 = COPY killed $w0
# CHECK-LABEL: bb.1:
# CHECK: liveins: $w1, $w0
# CHECK: liveins: $w0, $w1
# CHECK: renamable $w19 = COPY killed $w0
# CHECK: renamable $w20 = COPY killed $w1
name: sinkcopy3
@ -89,7 +89,7 @@ body: |
# CHECK-NOT: renamable $w19 = COPY killed $w0
# CHECK-NOT: renamable $w20 = COPY killed $w1
# CHECK-LABEL: bb.1:
# CHECK: liveins: $w1, $w0
# CHECK: liveins: $w0, $w1
# CHECK: renamable $w19 = COPY killed $w0
# CHECK-LABEL: bb.2:
# CHECK: liveins: $w0, $w1
@ -123,7 +123,7 @@ body: |
# CHECK-LABEL: bb.2:
# CHECK: $w1 = ADDWrr $w1, $w0
# CHECK-LABEL: bb.3:
# CHECK: liveins: $w1, $w0
# CHECK: liveins: $w0, $w1
# CHECK: renamable $w19 = COPY killed $w0
name: sinkcopy5
tracksRegLiveness: true
@ -155,7 +155,7 @@ body: |
# CHECK-NOT: renamable $w19 = COPY $w0
# CHECK-NOT: renamable $w20 = COPY $w0
# CHECK-LABEL: bb.2:
# CHECK: liveins: $w1, $w0
# CHECK: liveins: $w0, $w1
# CHECK: renamable $w19 = COPY $w0
# CHECK: renamable $w20 = COPY $w19
name: sinkcopy6
@ -213,7 +213,7 @@ body: |
# CHECK-LABEL: bb.2:
# CHECK: $w1 = ADDWrr $w1, $w0, implicit $x0
# CHECK-LABEL: bb.3:
# CHECK: liveins: $x1, $w0
# CHECK: liveins: $w0, $x1
# CHECK: renamable $w19 = COPY killed $w0, implicit-def $x19
name: sinkcopy8
tracksRegLiveness: true

31
test/CodeGen/AMDGPU/postra-machine-sink.mir Normal file
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@ -0,0 +1,31 @@
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
# Don't sink copy that writes sub-register of another copy source register
# CHECK-LABEL: name: donotsinkcopy
# CHECK-LABEL: bb.0:
# CHECK: renamable $sgpr1 = COPY renamable $sgpr2
# CHECK-LABEL: bb.1:
# CHECK: liveins: $sgpr0_sgpr1:0x00000003
# CHECK: renamable $vgpr1_vgpr2 = COPY renamable $sgpr0_sgpr1
---
name: donotsinkcopy
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0, $sgpr2, $vgpr3
S_CMP_LT_U32 renamable $sgpr2, target-flags(amdgpu-gotprel32-lo) 2, implicit-def $scc
renamable $sgpr1 = COPY renamable $sgpr2
renamable $vgpr1_vgpr2 = COPY renamable $sgpr0_sgpr1
S_CBRANCH_SCC0 %bb.2, implicit $scc
bb.1:
liveins: $vgpr2, $sgpr0_sgpr1:0x00000001
S_BRANCH %bb.4
bb.2:
liveins: $sgpr1
bb.4:
S_ENDPGM 0
...