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[DAGCombine] Preserve shuffles when one of the vector operands is constant
Summary:
Do *not* perform combines such as:
vector_shuffle<4,1,2,3>(build_vector(Ud, C0, C1 C2), scalar_to_vector(X))
->
build_vector(X, C0, C1, C2)
Keeping the shuffle allows lowering the constant build_vector to a materialized
constant vector (such as a vector-load from the constant-pool or some other idiom).
Reviewers: delena, igorb, spatel, mkuper, andreadb, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25524
llvm-svn: 285063
This commit is contained in:
Zvi Rackover
parent
f8f8e59cdd
commit
d92eb1132c
@ -834,6 +834,13 @@ static bool isAllOnesConstantOrAllOnesSplatConstant(SDValue N) {
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return false;
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}
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// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
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// undef's.
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static bool isAnyConstantBuildVector(const SDNode *N) {
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return ISD::isBuildVectorOfConstantSDNodes(N) ||
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ISD::isBuildVectorOfConstantFPSDNodes(N);
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}
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SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
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SDValue N1) {
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EVT VT = N0.getValueType();
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@ -13744,6 +13751,71 @@ static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
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return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
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}
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// Attempt to combine a shuffle of 2 inputs of 'scalar sources' -
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// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR.
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// This combine is done in the following cases:
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// 1. Both N0,N1 are BUILD_VECTOR's composed of constants or undefs.
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// 2. Only one of N0,N1 is a BUILD_VECTOR composed of constants or undefs -
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// Combine iff that node is ALL_ZEROS. We prefer not to combine a
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// BUILD_VECTOR of all constants to allow efficient materialization of
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// constant vectors, but the ALL_ZEROS is an exception because
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// zero-extension matching seems to rely on having BUILD_VECTOR nodes with
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// zero padding between elements. FIXME: Eliminate this exception for
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// ALL_ZEROS constant vectors.
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// 3. Neither N0,N1 are composed of only constants.
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static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN,
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SelectionDAG &DAG,
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const TargetLowering &TLI) {
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EVT VT = SVN->getValueType(0);
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unsigned NumElts = VT.getVectorNumElements();
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SDValue N0 = SVN->getOperand(0);
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SDValue N1 = SVN->getOperand(1);
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if (!N0->hasOneUse() || !N1->hasOneUse())
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return SDValue();
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// If only one of N1,N2 is constant, bail out if it is not ALL_ZEROS as
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// discussed above.
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if (!N1.isUndef()) {
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bool N0AnyConst = isAnyConstantBuildVector(N0.getNode());
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bool N1AnyConst = isAnyConstantBuildVector(N1.getNode());
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if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode()))
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return SDValue();
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if (!N0AnyConst && N1AnyConst && !ISD::isBuildVectorAllZeros(N1.getNode()))
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return SDValue();
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}
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SmallVector<SDValue, 8> Ops;
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for (int M : SVN->getMask()) {
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SDValue Op = DAG.getUNDEF(VT.getScalarType());
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if (M >= 0) {
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int Idx = M < (int)NumElts ? M : M - NumElts;
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SDValue &S = (M < (int)NumElts ? N0 : N1);
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if (S.getOpcode() == ISD::BUILD_VECTOR) {
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Op = S.getOperand(Idx);
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} else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) {
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if (Idx == 0)
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Op = S.getOperand(0);
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} else {
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// Operand can't be combined - bail out.
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return SDValue();
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}
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}
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Ops.push_back(Op);
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}
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// BUILD_VECTOR requires all inputs to be of the same type, find the
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// maximum type and extend them all.
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EVT SVT = VT.getScalarType();
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if (SVT.isInteger())
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for (SDValue &Op : Ops)
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SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
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if (SVT != VT.getScalarType())
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for (SDValue &Op : Ops)
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Op = TLI.isZExtFree(Op.getValueType(), SVT)
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? DAG.getZExtOrTrunc(Op, SDLoc(SVN), SVT)
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: DAG.getSExtOrTrunc(Op, SDLoc(SVN), SVT);
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return DAG.getBuildVector(VT, SDLoc(SVN), Ops);
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}
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SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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EVT VT = N->getValueType(0);
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unsigned NumElts = VT.getVectorNumElements();
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@ -13859,40 +13931,9 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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// Attempt to combine a shuffle of 2 inputs of 'scalar sources' -
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// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR.
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if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) {
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SmallVector<SDValue, 8> Ops;
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for (int M : SVN->getMask()) {
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SDValue Op = DAG.getUNDEF(VT.getScalarType());
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if (M >= 0) {
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int Idx = M % NumElts;
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SDValue &S = (M < (int)NumElts ? N0 : N1);
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if (S.getOpcode() == ISD::BUILD_VECTOR && S.hasOneUse()) {
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Op = S.getOperand(Idx);
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} else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR && S.hasOneUse()) {
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if (Idx == 0)
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Op = S.getOperand(0);
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} else {
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// Operand can't be combined - bail out.
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break;
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}
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}
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Ops.push_back(Op);
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}
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if (Ops.size() == VT.getVectorNumElements()) {
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// BUILD_VECTOR requires all inputs to be of the same type, find the
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// maximum type and extend them all.
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EVT SVT = VT.getScalarType();
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if (SVT.isInteger())
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for (SDValue &Op : Ops)
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SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
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if (SVT != VT.getScalarType())
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for (SDValue &Op : Ops)
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Op = TLI.isZExtFree(Op.getValueType(), SVT)
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? DAG.getZExtOrTrunc(Op, SDLoc(N), SVT)
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: DAG.getSExtOrTrunc(Op, SDLoc(N), SVT);
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return DAG.getBuildVector(VT, SDLoc(N), Ops);
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}
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}
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if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT))
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if (SDValue Res = combineShuffleOfScalars(SVN, DAG, TLI))
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return Res;
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// If this shuffle only has a single input that is a bitcasted shuffle,
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// attempt to merge the 2 shuffles and suitably bitcast the inputs/output
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@ -2839,36 +2839,26 @@ define void @combine_scalar_load_with_blend_with_zero(double* %a0, <4 x float>*
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define <4 x float> @combine_constant_insertion_v4f32(float %f) {
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; SSE2-LABEL: combine_constant_insertion_v4f32:
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; SSE2: # BB#0:
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; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE2-NEXT: movaps {{.*#+}} xmm1 = <u,4,5,3>
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; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_constant_insertion_v4f32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; SSSE3-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSSE3-NEXT: movaps {{.*#+}} xmm1 = <u,4,5,3>
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; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_constant_insertion_v4f32:
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; SSE41: # BB#0:
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; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
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; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_constant_insertion_v4f32:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]
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; AVX-NEXT: retq
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%a0 = insertelement <4 x float> undef, float %f, i32 0
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%ret = shufflevector <4 x float> %a0, <4 x float> <float undef, float 4.0, float 5.0, float 3.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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@ -2878,53 +2868,35 @@ define <4 x float> @combine_constant_insertion_v4f32(float %f) {
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define <4 x i32> @combine_constant_insertion_v4i32(i32 %f) {
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; SSE2-LABEL: combine_constant_insertion_v4i32:
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; SSE2: # BB#0:
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; SSE2-NEXT: movl $30, %eax
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; SSE2-NEXT: movd %eax, %xmm0
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; SSE2-NEXT: movl $4, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; SSE2-NEXT: movl $5, %eax
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; SSE2-NEXT: movd %eax, %xmm2
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: movaps {{.*#+}} xmm0 = <u,4,5,30>
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; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_constant_insertion_v4i32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movl $30, %eax
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; SSSE3-NEXT: movd %eax, %xmm0
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; SSSE3-NEXT: movl $4, %eax
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; SSSE3-NEXT: movd %eax, %xmm1
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; SSSE3-NEXT: movl $5, %eax
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; SSSE3-NEXT: movd %eax, %xmm2
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; SSSE3-NEXT: movd %edi, %xmm0
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSSE3-NEXT: movd %edi, %xmm1
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; SSSE3-NEXT: movaps {{.*#+}} xmm0 = <u,4,5,30>
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; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_constant_insertion_v4i32:
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; SSE41: # BB#0:
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; SSE41-NEXT: movd %edi, %xmm0
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; SSE41-NEXT: movl $4, %eax
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; SSE41-NEXT: pinsrd $1, %eax, %xmm0
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; SSE41-NEXT: movl $5, %eax
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; SSE41-NEXT: pinsrd $2, %eax, %xmm0
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; SSE41-NEXT: movl $30, %eax
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; SSE41-NEXT: pinsrd $3, %eax, %xmm0
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3,4,5,6,7]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_constant_insertion_v4i32:
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; AVX: # BB#0:
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; AVX-NEXT: vmovd %edi, %xmm0
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; AVX-NEXT: movl $4, %eax
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; AVX-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
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; AVX-NEXT: movl $5, %eax
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; AVX-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
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; AVX-NEXT: movl $30, %eax
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; AVX-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX1-LABEL: combine_constant_insertion_v4i32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vmovd %edi, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_constant_insertion_v4i32:
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; AVX2: # BB#0:
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; AVX2-NEXT: vmovd %edi, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]
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; AVX2-NEXT: retq
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%a0 = insertelement <4 x i32> undef, i32 %f, i32 0
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%ret = shufflevector <4 x i32> %a0, <4 x i32> <i32 undef, i32 4, i32 5, i32 30>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x i32> %ret
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