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AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP

Browse Source 
Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48195

llvm-svn: 335316
This commit is contained in:
Tom Stellard 2018-06-22 02:34:29 +00:00
parent e41569733d
commit d9853a4c72
6 changed files with 68 additions and 0 deletions
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4
lib/Target/AMDGPU/AMDGPUGISel.td
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@ -26,6 +26,10 @@ def gi_vop3mods :
GIComplexOperandMatcher<s32, "selectVOP3Mods">,
GIComplexPatternEquiv<VOP3Mods>;
def gi_vop3omods :
GIComplexOperandMatcher<s32, "selectVOP3OMods">,
GIComplexPatternEquiv<VOP3OMods>;
class GISelSop2Pat <
SDPatternOperator node,
Instruction inst,

9
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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@ -537,6 +537,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
switch (I.getOpcode()) {
default:
break;
case TargetOpcode::G_SITOFP:
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FADD:
case TargetOpcode::G_FPTOUI:
@ -582,6 +583,14 @@ AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
}};
}
InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const {
return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
}};
}
InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {

2
lib/Target/AMDGPU/AMDGPUInstructionSelector.h
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@ -78,6 +78,8 @@ private:
InstructionSelector::ComplexRendererFns
selectVOP3Mods0(MachineOperand &Root) const;
InstructionSelector::ComplexRendererFns
selectVOP3OMods(MachineOperand &Root) const;
InstructionSelector::ComplexRendererFns
selectVOP3Mods(MachineOperand &Root) const;
const SIInstrInfo &TII;

3
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -91,6 +91,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
setAction({G_FPTOSI, S32}, Legal);
setAction({G_FPTOSI, 1, S32}, Legal);
setAction({G_SITOFP, S32}, Legal);
setAction({G_SITOFP, 1, S32}, Legal);
setAction({G_FPTOUI, S32}, Legal);
setAction({G_FPTOUI, 1, S32}, Legal);

36
test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir Normal file
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@ -0,0 +1,36 @@
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @sitofp(i32 addrspace(1)* %global0) {ret void}
...
---
name: sitofp
legalized: true
regBankSelected: true
# GCN-LABEL: name: sitofp
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
%0:sgpr(s32) = COPY $sgpr0
; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s64) = COPY $vgpr3_vgpr4
; sitofp s
; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0
%3:vgpr(s32) = G_SITOFP %0
; sitofp v
; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0
%4:vgpr(s32) = G_SITOFP %1
G_STORE %3, %2 :: (store 4 into %ir.global0)
G_STORE %4, %2 :: (store 4 into %ir.global0)
...
---

14
test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir Normal file
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@ -0,0 +1,14 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: test_sitofp_f32_to_i32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_sitofp_f32_to_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SITOFP %0
...