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[ARM] Make sure we don't transform unaligned store to stm on Thumb1.

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This isn't likely to come up in practice; the combination of compiler
flags required to hit this issue should be rare. Found by inspection.
This commit is contained in:
Eli Friedman 2021-06-21 14:24:31 -07:00
parent bb7326c8ea
commit d98eee18e6
2 changed files with 22 additions and 0 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -18169,6 +18169,8 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
auto *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1));
if (!RHS || RHS->getZExtValue() != 4)
return false;
if (Alignment < Align(4))
return false;
Offset = Op->getOperand(1);
Base = Op->getOperand(0);

20
test/CodeGen/Thumb/ldm-stm-postinc.ll
View File

@ -79,3 +79,23 @@ define void @j(i32* %a, i32* readnone %b) {
._crit_edge: ; preds = %.lr.ph, %0
ret void
}
; Make sure we don't transform str->stm when unaligned loads are allowed.
; CHECK-LABEL: @nostrictalign
; CHECK: str r2, [r0]
define void @nostrictalign(i32* %a, i32* readnone %b) "target-features"="-strict-align" {
%1 = icmp eq i32* %a, %b
br i1 %1, label %._crit_edge, label %.lr.ph
.lr.ph: ; preds = %.lr.ph, %0
%i.02 = phi i32 [ %2, %.lr.ph ], [ 0, %0 ]
%.01 = phi i32* [ %3, %.lr.ph ], [ %a, %0 ]
%2 = add nsw i32 %i.02, 1
store i32 %i.02, i32* %.01, align 1
%3 = getelementptr inbounds i32, i32* %.01, i32 1
%4 = icmp eq i32* %3, %b
br i1 %4, label %._crit_edge, label %.lr.ph
._crit_edge: ; preds = %.lr.ph, %0
ret void
}